WO2004027995A2

WO2004027995A2 - Integrated circuit comprising an sstl (stub series terminated logic) pre-driver stage using regulated power supply and method for performing an sstl operation

Info

Publication number: WO2004027995A2
Application number: PCT/US2003/024817
Authority: WO
Inventors: Brian W. Amick; Lynn Warriner; Claude R. Gauthier; Tri K. Tran
Original assignee: Sun Microsystems, Inc.
Priority date: 2002-09-19
Filing date: 2003-08-08
Publication date: 2004-04-01
Also published as: GB0506134D0; AU2003259060A8; WO2004027995A3; AU2003259060A1; GB2408642A; GB2408642B

Abstract

A SSTL memory interface pre-driver stage (24) that uses a voltage regulator (32) to generate “virtual” supply and ground voltages is provided. The “virtual” supply, being lower than a power supply voltage of the pre-driver stage (24), and the “virtual” ground voltage, being greater than a zero volt ground voltage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage (24) uses a biasing circuit (30) to bias the voltage regulator (32), formed by a transistor arranged in a source follower configuration, to generate the “virtual” supply and ground voltages off which a voltage translator stage (36) of the pre-driver stage operates to generate an output of the pre-driver stage (24).

Description

SSTL PRE-DRIVER DESIGN USING REGULATED POWER SUPPLY

Cross-reference to related applications

The present application claims priority from U.S. Patent Application Serial Nos. 10/247,127 and 10/247,082, both filed on September 19, 2002.

Background of Invention

[0001] As shown in Figure 1, a typical computer system 10 includes at least a microprocessor 12 (often referred to and known as "CPU") and some form of memory 14. The microprocessor 12 has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system 10. Specifically, Figure 1 shows the computer system 10 having the microprocessor 12, memory 14, integrated circuits (ICs) 16 that have various functionalities, and communication paths 19, i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system 10.

[0002] In order to keep pace with improving technologies, computer system and circuit designers are constantly trying to improve and get the most out of then- designs through the most cost-effective means. As faster versions of a particular CPU become available, a designer will often try to improve the throughput of their existing design by simply increasing the CPU clock frequency. However, after a certain point, the speed of the system's main memory becomes a limiting factor in optimizing the throughput of the system. To this end, designers have produced faster memories, which, in turn, has necessitated high-speed memory interfaces.

[0003] One type of design that has been used for high-speed memory interface applications involves the use of stub series termination logic (SSTL). SSTL is a standard created by the Joint Electron Device Engineering Council (JEDEC) to provide a termination scheme for high speed signaling in applications such as DDR-SDRA . SSTL specifies particular switching characteristics such that high operating frequencies are available. As operating frequencies continue to increase and as the demand for faster memory interfaces has and continues to grow, the STTL interface standard continues to enjoy wide acceptance.

Summary of Invention

[0004] According to one aspect of one or more embodiments of the present invention, an integrated circuit comprises a biasing circuit arranged to generate a bias signal, a voltage regulator arranged to receive the bias signal and generate a regulated voltage on a terminal thereof, and a voltage translator stage, operatively connected to the terminal, arranged to output a voltage dependent on an input thereto, where the regulated voltage is arranged to serve as one of a virtual power supply voltage for the voltage translator stage and a virtual ground reference voltage for the voltage translator stage, where the virtual power supply voltage is less than a power supply voltage of the voltage regulator, and where the virtual ground reference voltage is greater than zero.

[0005] According to another aspect of one or more embodiments of the present invention, a method for performing a stub series termination logic operation comprises generating a bias signal dependent on one of a power supply voltage and a ground voltage, generating a regulated voltage dependent on the bias signal and one of the power supply voltage and the ground voltage, and generating an output signal dependent on an input signal, where the generating the output signal is dependent on the regulated voltage, and where the regulated voltage is one of less than the power supply voltage and greater than the ground voltage.

[0006] According to another aspect of one or more embodiments of the present invention, an integrated circuit having a core and a memory comprises stub series termination logic circuitry interfaced between the core and the memory, where the stub series termination logic circuitry is arranged to operate off of one of a power supply voltage and a ground voltage, and where the stub series termination logic circuitry comprises: a pre-driver stage arranged to receive an input signal from the core, where the pre-driver stage comprises a voltage regulator arranged to operate off of one of the ground voltage and the power supply voltage and generate a regulated voltage on a terminal thereof, where one of a minimum value of the regulated voltage is greater than the ground voltage and a maximum value of the regulated voltage is less than the power supply voltage, and a voltage translator stage, operatively connected to the terminal, arranged to output a signal dependent on the input signal and the regulated voltage; and an output buffer stage arranged to receive and buffer the output signal.

[0007] Other aspects and advantages of the invention will be apparent from the following description and the appended claims.

Brief Description of Drawings

[0008] Figure 1 shows a typical computer system.

[0009] Figure 2 shows a memory interface in accordance with an embodiment of the present invention.

[0010] Figure 3 shows a block diagram of a pre-driver stage in accordance with an embodiment of the present invention.

[0011] Figure 4 shows a circuit diagram of a pre-driver stage in accordance with an embodiment of the present invention.

[0012] Figure 5 shows a circuit diagram of a voltage translator in accordance with an embodiment of the present invention.

[0013] Figure 6 shows a circuit diagram of a voltage translator in accordance with an embodiment of the present invention. [0014] Figure 7 shows a memory interface in accordance with an embodiment of the present invention.

)15] Figure 8 shows a block diagram of a pre-driver stage in accordance with an embodiment of the present invention.

[0016] Figure 9 shows a circuit diagram of a pre-driver stage in accordance with an embodiment of the present invention.

[0017] Figure 10 shows a circuit diagram of a voltage translator in accordance with an embodiment of the present invention.

Detailed Description

[0018] In circumstances when a memory interface using SSTL technology is integrated on-chip, there is a likelihood that the supply voltage for the SSTL interface will exceed the voltage tolerances of low- voltage transistors that are designed to operate at voltages below that of the SSTL interface. If a large voltage is placed across one of these low-voltage transistors, the gate oxide layer of the transistor may break down, which, in turn, could cause circuit malfunction.

[0019] The present invention relates to a pull-down pre-driver stage and a pull- up pre-driver stage of a SSTL interface. Both the SSTL pull-down pre-driver and the SSTL pull-up pre-driver use a voltage regulator device to generate a "virtual power supply," in the case of the SSTL pull-down pre-driver, and a "virtual ground" voltage reference, in the case of the SSTL pull-up pre-driver, off which particular circuitry operates to generate a low voltage swing signal dependent on an input to pre-driver stage from a core portion of a microprocessor, where the pre-driver stage operates off of a supply voltage greater than the "virtual power supply" and the "virtual ground."

[0020] Figure 2 shows a block diagram of a SSTL interface 20 in accordance with an embodiment of the present invention. In Figure 2, a core signal, core 22 (from a core region (not shown) of the microprocessor on which the SSTL interface 20 is implemented) having a logic value of '0' or T serves an input to a pre-driver stage 24 that operates off of a supply voltage Vdd 26 (I/O power supply voltage). However, due to the types of transistors (not shown) used in the SSTL interface 20, the supply voltage Vdd 26 cannot be placed on the transistors (not shown) without damaging them. Accordingly, the pre-driver stage 24, using a voltage regulator (not shown) (described in detail below with reference to Figures 3 and 4) generates a "virtual power supply," or regulated voltage, that facilitates the generation of a low voltage swing signal 27 to an output buffer stage 28, where the low voltage swing signal 27 has a voltage swing between 0 and a voltage value less than Vdd 26. Thus, the pre-driver stage 24 may be referred to as a "pull-down pre-driver." Those skilled in the art will understand that the pre-driver stage 24 must provide some gain to the output buffer stage 28 due to the fact that output buffer stage 28 itself may be very large and complex. Figure 3 shows a block diagram of a SSTL pre-driver stage 24 in accordance with an embodiment of the present invention. In Figure 3, the pre- driver stage 24 includes a biasing circuit 30, a voltage regulator 32, and a voltage translator stage 36. The biasing circuit 30 generates a bias signal, bias 31, that is used to bias the voltage regulator 32. The voltage regulator 32, operating off of Vdd 26 and dependent on the bias signal 31, generates a regulated or 'virtual' power supply voltage, virrual_supply 34, off which the voltage translator stage 36 operates. This 'virtual' power supply voltage 34 is less than Vdd 26 and is used by the voltage translator stage 36 to generate a low voltage swing signal 27 to the output buffer stage (28 in Figure 2) dependent on the input core signal (22 in Figure 2). As described below with reference to Figure 4, the voltage regulator 32 is arranged to maintain the voltage on the 'virtual' supply 34 even when the voltage translator stage 36 draws current from the voltage regulator 32. ^rn 22] Figure 4 shows a circuit diagram of a SSTL pre-driver stage 24 in accordance with an embodiment of the present invention. In Figure 4, the biasing circuit 30 includes a plurality of resistors 40 that form a voltage divider that generates the bias signal 31 to the voltage regulator 32. The voltage regulator 32 is implemented using an NMOS device 42 that is arranged in a source follower configuration. Particularly, the bias signal 31 is operatively connected to a gate 44 of the NMOS device 42, Vdd 26 is operatively connected to drain terminal 46 of the NMOS device 42, and the 'virtual' power supply voltage 34 is operatively connected to a source terminal 48 of the NMOS device 42. This source follower configuration causes the source terminal 48 to be a pulled to voltage equal to a voltage of the bias signal 31 at the gate terminal 44 minus the threshold voltage of the NMOS device 42. For example, if the bias signal 31 is at 2 volts and the threshold voltage of the NMOS device 42 is 0.5 volts, the source terminal 48, and hence, the 'virtual' power supply voltage 34 will be at 1.5 volts.

[0023] Those skilled in the art will understand that, in one or more other embodiments, a biasing circuit using a structure other than a voltage divider may be used. For example, a biasing circuit may use active devices, bandgap references, etc. In other words, any biasing circuit that generates one or more bias signals is within the scope of the present invention.

[0024] When the voltage translator stage 36 draws current from the voltage regulator 32, the 'virtual' power supply voltage 34 at the source terminal 48 of the NMOS device 42 starts to decrease, which, in turn, causes the NMOS device 42 to switch 'on,' i.e., conduct more current, which, in turn, pulls up the voltage at the source terminal 48 of the NMOS device 42 back to the desired 'virtual' power supply voltage 34.

[0025] Figure 5 shows a circuit diagram of an exemplary voltage translator 50 that may be used as part of the voltage translator stage 36 shown in Figures 3 and 4. The voltage translator 50 is made up of a differential stage formed by PMOS transistors 52, 54, 56, and 58, a first inverter formed by PMOS transistor 60 and NMOS transistor 62, NMOS transistor 64, NMOS transistor 66, and a second inverter formed by PMOS transistor 68 and NMOS transistor 70.

[0026] Core signal 22 serves as an input to the voltage translator 50. When core signal 22 goes 'high,' NMOS transistor 64 switches 'on,' which, in turn, causes an input to PMOS transistor 56 to get connected to 'low,' i.e., ground 72, via 'on' NMOS transistor 64. Moreover, when core signal 22 goes 'high,' NMOS transistor 62 switches 'on,' which, in turn, causes an input to PMOS transistor 58 to get connected to 'low' via 'on' NMOS transistor 62. Because both PMOS transistors 56 and 58 are 'on,' virtual supply voltage 34 (from the voltage regulator 32 shown in Figures 3 and 4) gets connected to an input of NMOS transistor 70, which, in turn, causes NMOS transistor 70 to switch 'on, which, in turn, causes the voltage translator 50 to output 'low' to the output buffer (not shown).

[0027] When core signal 22 goes 'low,' PMOS transistor 60 switches 'on,' which, in turn, causes the input to NMOS transistor 66 to get connected to 'high, i.e., Vdd 74 (I/O power supply voltage), via 'on' PMOS transistor 60. In turn, NMOS transistor 66 switches 'on' causing an input to PMOS transistor 68 to get connected to 'low' via 'on' NMOS transistor 66. When PMOS transistor 68 switches 'on,' the voltage translator 50 outputs virtual supply voltage 34 to the output buffer (not shown) via 'on' PMOS transistor 68.

[0028] Figure 6 shows a circuit diagram of another exemplary voltage translator

80 that may be used as part of the voltage translator stage 36 shown in Figures 3 and 4. The voltage translator 80 is made up of a delay chain formed by PMOS transistors 82, 84, 86, 88, and 90 and NMOS transistors 92, 94, 96, 98, and 100, PMOS transistor 102, an inverter formed by PMOS transistor 104 and NMOS transistor 106, NMOS transistor 108, PMOS transistor 110, an inverter formed by PMOS transistor 112 and NMOS transistor 114, and an inverter formed by PMOS transistor 116 and NMOS transistor 118.

29] Core signal 22 serves as an input to the voltage translator 80. When core signal 22 goes 'high,' NMOS transistor 106 switches 'on,' which, in turn, causes a 'low,' i.e. ground 120, to get passed through NMOS transistor 108 (which is 'on' due to its input being connected to virtual supply voltage 34) to an input of PMOS transistor 104 which, in turn, switches 'on' causing virtual supply voltage 34 to get connected to an input of NMOS transistor 118. In turn, NMOS transistor 118 switches 'on' causing the voltage translator 80 to output 'low' to the output buffer (not shown).

[0030] When core signal 22 goes 'low,' PMOS transistor 104 switches 'on.'

Before the 'low' on core signal 22 can propagate down the delay chain formed by PMOS transistors 82, 84, 86, 88, and 90 and NMOS transistors 92, 94, 96, 98, and 100, the delay chain outputs 'low' to an input of PMOS transistor 102, which, in turn, causes PMOS transistor 102 to be 'on.' Because PMOS transistors 102 and 104 are 'on' for some finite amount of time, a 'high,' i.e., Vdd 122 (I/O power supply voltage), passes through 'on PMOS transistors 102 and 104 and NMOS transistor 108 to an input of NMOS transistor 114, which, in turn, causes NMOS transistor 114 to switch 'on.' When NMOS transistor 114 switches 'on,' an input to PMOS transistor 116 gets connected to 'low' via 'on' NMOS transistor 114. Because the 'low' at the input of PMOS transistor 116 causes PMOS transistor 116 to switch 'on,' the voltage translator 80 outputs virtual supply voltage 34 to the output buffer (not shown) via 'on' PMOS transistor 116. Moreover, PMOS transistor 110 uses feedback from the input of the inverter formed by PMOS transistor 116 and NMOS transistor 118 to maintain a voltage at the input of the inverter formed by PMOS transistor 112 and NMOS transistor 114 when the voltage translator 80 is outputting the virtual supply voltage 34.

[0031] Figure 7 shows a block diagram of an exemplary SSTL interface 220 in accordance with an embodiment of the present invention. In Figure 7, a core signal, core 222 (from a core region (not shown) of the microprocessor on which the SSTL interface 220 is implemented) having a logic value of '0' or '1' serves an input to a pre-driver stage 224 that operates off of a supply voltage Vdd 226. However, due to the types of transistors (not shown) used in the SSTL interface 220, the supply voltage Vdd 226 cannot be placed across the transistors (not shown) without damaging them. Accordingly, the pre- driver stage 224, using a voltage regulator (not shown) (described in detail below with reference to Figures 8 and 9) generates a "virtual ground," or regulated voltage, that facilitates the generation of a low voltage swing signal

227 to an output buffer stage 228, where the low voltage swing signal 227 has a voltage swing between some value above 0, e.g., 1 volt, and Vdd 226. Thus, the pre-driver stage 224 may be referred to as a "pull-up pre-driver." Those skilled in the art will understand that the pre-driver stage 224 must provide some gain to the output buffer stage 228 due to the fact that output buffer stage

228 itself may be very large and complex. Figure 8 shows a block diagram of an exemplary SSTL pre-driver stage

224 in accordance with an embodiment of the present invention. In Figure 8, the pre-driver stage 224 includes a voltage translator stage 231 (described in detail with reference to Figure 10), a biasing circuit 232, a voltage regulator 234, and a gain stage 229. The biasing circuit 232 generates a bias signal, bias 230, that is used to bias the voltage regulator 234. The voltage regulator 234, operating off of Vdd 226 (I/O power supply) and dependent on the bias signal 230, generates a regulated or 'virtual' ground reference voltage, virtual_ground 236, which is used by the voltage translator stage 231 and the gain stage 229 as a ground voltage reference. This 'virtual' ground reference voltage 236 is greater than the typical 0 volt ground voltage and is used by the gain stage 229 to generate a low voltage swing signal 227 the output buffer stage (228 in Figure 7)) dependent on a voltage generated by the voltage translator stage 231. The voltage translator stage 231 generates the voltage to the gain stage 229 dependent on the input core signal (222 in Figure 7). As described below with reference to Figure 9, the voltage regulator 234 is arranged to maintain the voltage on the 'virtual' ground reference voltage 236 even when the voltage translator stage 231 or the gain stage 229 draws current from the voltage regulator 232.

[0033] Figure 9 shows a circuit diagram of an exemplary SSTL pre-driver stage

224 in accordance with an embodiment of the present invention. In Figure 9, the biasing circuit 232 includes a plurality of resistors 240 that form a voltage divider that generates the bias signal 230 to the voltage regulator 234. The voltage regulator 234 is implemented using a PMOS device 242 that is arranged in a source follower configuration. Particularly, the bias signal 230 is operatively connected to a gate terminal 244 of the PMOS device 242, ground is operatively connected to a drain terminal 246 of the PMOS device 242, and the 'virtual' ground reference voltage 236 is operatively connected to a source terminal 248 of the PMOS device 242. Moreover, the source terminal 248 is connected to some large resistance 249 (that is used to provide a small amount of biasing current to the PMOS device 242) that is connected to Vdd 226. This source follower configuration of the PMOS device 242 causes the source terminal 248 to be pulled to a voltage equal to a voltage of the bias signal 230 at the gate terminal 244 plus the threshold voltage of the PMOS device 242. For example, if the bias signal 230 is at 0.5 volts and the threshold voltage of the PMOS device 242 is 0.5 volts, the source terminal 248, and hence, the 'virtual' ground reference voltage 236 will be at approximately 1 volt.

[0034] Those skilled in the art will understand that, in one or more other embodiments, a biasing circuit using a structure other than a voltage divider may be used. For example, a biasing circuit may use active devices, bandgap references, etc. In other words, any biasing circuit that generates one or more bias signals is within the scope of the present invention.

[0035] When the voltage translator stage 231 or the gain stage 229 draws current from the voltage regulator 234, the voltage of the 'virtual' ground reference voltage 236 at the source terminal 248 of the PMOS device 242 starts to increase, which, in turn, causes the PMOS device 242 to switch 'on,' i.e., conduct more current, which, in turn, pulls down the voltage at the source terminal 248 of the PMOS device 242 back to the desired voltage of the 'virtual' ground reference voltage 236.

[0036] The gain stage 229 has an inverter formed by PMOS transistor 250 and

NMOS transistor 252. The input to this inverter is operatively connected to an output from the voltage translator stage 231. When the voltage translator 231 outputs 'high,' the gain stage 229 outputs the virrual_ground 236 voltage. Conversely, when the voltage translator 231 outputs 'low,' the gain stage 229 outputs Vdd 226 to the output buffer (228 in Figure 7).

[0037] Figure 10 shows a circuit diagram of an exemplary voltage translator stage 231 in accordance with an embodiment of the present invention. In Figure 10, the input core signal 222 serves as an input to NMOS transistor 272 and an inverter formed by PMOS transistor 276 and NMOS transistor 278. When the input core signal 222 is 'high,' NMOS transistor 272 is 'on,' which, in turn causes a ground voltage, i.e., a 'low,' to propagate through NMOS transistor 268 (which is controlled by bias signal bias" 237) and PMOS transistor 264 (which is controlled by virtual_ground 236 (from the voltage regulator 234 shown in Figures 8 and 9)). This 'low' then serves as an input to PMOS transistor 262, which, in turn, causes the voltage translator stage 231 to output Vdd due to the connection between the output 255 of the voltage translator stage 231 and Vdd though 'on' PMOS transistor 262.

[0038] When the core signal 222 is 'low,' the inverter formed by PMOS transistor 276 and NMOS transistor 278 outputs 'high' to an input of NMOS transistor 274, which, in turn, causes a 'low' to propagate through NMOS transistor 270 (which is controlled by bias signal bias" 237) and PMOS transistor 266 (which is controlled by virtual_ground 236 (from the voltage regulator 234 shown in Figures 8 and 9)). This 'low' then propagates to the output 255 of the voltage translator stage 255.

)39] Those skilled in the art will understand that, in one or more embodiments, the bias voltages bias' (in Figure 9) and bias" (in Figure 10) may be derived or generated from the biasing circuit 232 (shown in Figures 8 and 9).

[0040] Further, those skilled in the art will understand that, in one or more embodiments, any voltage translator may be used in the present invention.

[0041] Advantages of the present invention may include one or more of the following. In one or more embodiments, because a SSTL pre-driver stage uses a voltage regulator to generate a 'virtual' supply voltage, low- voltage transistors, that would otherwise be damaged if directly operated off of a supply voltage of the pre-driver stage, may be used. Accordingly, performance may be increased without an increase in power consumption.

[0042] In one or more embodiments, because a SSTL pre-driver stage uses a voltage regulator to generate a 'virtual' ground reference voltage, low-voltage transistors, that would otherwise be damaged if directly operated between a supply voltage of the pre-driver stage and zero volts (typical ground voltage), may be used. Accordingly, performance may be increased without an increase in power consumption.

[0043] Because a voltage translator typically requires that its supply be equal to the voltage that is can translate to, translating at a high voltage with low- voltage transistors may cause circuit damage. Accordingly, in one or more embodiments of the present invention, because an appropriate regulated voltage is supplied to the translator, transistors and other circuitry are not susceptible to damage.

[0044] In one or more embodiments, because the buffering of a signal from a microprocessor uses an I/O power supply, the power supply of the microprocessor may be changed or designed independent of the buffering. In other words, the microprocessor power supply voltage may be changed without affecting the I/O interface.

[U045] In one or more embodiments, because a SSTL pre-driver stage uses a voltage regulator with a voltage translator, the pre-driver stage draws very little DC current, which, in turn, reduces power consumption.

[0046] While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.

Claims

An integrated circuit, comprising: a biasing circuit arranged to generate a bias signal; a voltage regulator arranged to receive the bias signal and generate a regulated voltage on a terminal thereof, wherein the biasing circuit; and a voltage translator stage, operatively connected to the terminal, arranged to output a voltage dependent on an input thereto, wherein the regulated voltage is arranged to serve as one of a virtual power supply voltage for the voltage translator stage and a virtual ground reference voltage for the voltage translator stage, wherein the virtual power supply voltage is less than a power supply voltage of the voltage regulator, and wherein the virtual ground reference voltage is greater than zero.

[2] The integrated circuit of claim 1, further comprising: a gain stage arranged to generate an output dependent on the voltage from the voltage translator stage, wherein the virtual ground reference voltage is arranged to serve as a ground reference voltage for the gain stage.

[3] The integrated circuit of claim 2, further comprising an output stage operatively connected to the output of the gain stage.

[4] The integrated circuit of claim 2, wherein the voltage regulator is arranged to maintain the regulated voltage on the terminal when at least one of the voltage translator stage and the gain stage draws current from the voltage regulator.

[5] The integrated circuit of claim 1, wherein the voltage regulator comprises a device arranged in a source follower configuration. ^rΛ1 The integrated circuit of claim 1, wherein the voltage regulator comprises a transistor, and wherein the terminal is a source terminal of the transistor.

The integrated circuit of claim 6, wherein a gate terminal of the transistor is operatively connected to the bias signal, and wherein a drain terminal of the transistor is operatively connected to the power supply voltage.

[8] The integrated circuit of claim 6, wherein a gate terminal of the transistor is operatively connected to the bias signal, and wherein a drain terminal of the transistor is operatively connected to ground.

[9] The integrated circuit of claim 1, wherein a maximum voltage of a signal outputted from the voltage translator stage is less than the power supply voltage.

[10] The integrated circuit of claim 1, wherein a minimum voltage of a signal outputted from the voltage translator stage is greater than ground.

[11] The integrated circuit of claim 1, wherein the biasing circuit comprises a plurality of resistors connected in series.

[12] The integrated circuit of claim 1, wherein the biasing circuit, the voltage regulator, and the voltage translator stage are part of a stub series termination logic pre-driver circuit.

[13] The integrated circuit of claim 1, wherein the biasing circuit operates independent of the regulated voltage.

[14] A method for performing a stub series termination logic operation, comprising: generating a bias signal dependent on one of a power supply voltage and a ground voltage; generating a regulated voltage dependent on the bias signal and one of the power supply voltage and the ground voltage; and generating an output signal dependent on an input signal, wherein the generating the output signal is dependent on the regulated voltage, and wherein the regulated voltage is one of less than the power supply voltage and greater than the ground voltage.

[15] An integrated circuit having a core and a memory, comprising: stub series termination logic circuitry interfaced between the core and the memory, wherein the stub series termination logic circuitry is arranged to operate off of one of a power supply voltage and a ground voltage, and wherein the stub series termination logic circuitry comprises: a pre-driver stage arranged to receive an input signal from the core, wherein the pre-driver stage comprises: a voltage regulator arranged to operate off of one of the ground voltage and the power supply voltage and generate a regulated voltage on a terminal thereof, wherein one of a minimum value of the regulated voltage is greater than the ground voltage and a maximum value of the regulated voltage is less than the power supply voltage, and a voltage translator stage, operatively connected to the terminal, arranged to output a signal dependent on the input signal and the regulated voltage; and an output buffer stage arranged to receive and buffer the output signal.