GB2241845A

GB2241845A - Voltage adjusting circuit

Info

Publication number: GB2241845A
Application number: GB9101041A
Authority: GB
Inventors: Yutaka Arita
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1990-01-18
Filing date: 1991-01-17
Publication date: 1991-09-11
Anticipated expiration: 2011-01-17
Also published as: GB2241845B; GB9101041D0; DE4101419C2; DE4101419A1; JPH03214659A

Abstract

A supply voltage adjusting circuit of a MOSFET device is disclosed in which an integrated circuit of a memory circuit or a logic circuit having a field effect transistor and voltage lowering circuits 10 distributed around the integrated circuit are formed on the same substrate. DC voltage of 3V which is a suitable operation level of the memory circuit or the logic circuit can be supplied, and uneven voltage at various portions caused by different length of interconnections can be prevented. The voltage lowering circuits may comprise a single transistor or a darlington connected combination, in association with thresholding diodes and connected in the voltage supply path. <IMAGE>

Description

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TITLE OF THE INVENTION

Supply Voltage Adjusting Circuit of a Field Effect

Type Semiconductor Device BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a supply voltage adjusting circuit for driving a field effect type transistor and, more specifically, to a supply voltage adjusting circuit of a field effect type semiconductor device which lowers voltage applied from an external power supply to suitable operation level of the field effect type transistor. Description of the Background Art

A standard operation level of a memory or a logic is circuit having integrated field effect type transistors has been 5V, since an operation level of a transistortransistor-logic (TTL) is 5V. Accordingly, power supply circuits of 5V have meet the demand. However, in order to increase speed of operation and degree of integration of memories and logic circuits, Metal-OxideSemiconductor Field Effect Transistors (MOSFET) having the gate length shorter than 0.5 gm have been developed, and large-scale integrated circuits (LSI) having these MOSFETs with short gate length integrated thereon have come to be practically used. Since a suitable operation

1,. --- 11 level of the MOSFET having the short gate length is 3V, the supply o voltage must be lowerd from 5V to 3V.

Fig. 7 is a block diagram in which an external power supply is connected to a field effect type semiconductor device. Referring to the figure, an external power supply 1 applies supply voltage of 5V, which is supplied to other circuits such as a supply voltage adjusting circuit 2 and a CPU. The above mentioned supply voltage adjusting circuit 2 lowers the voltage applied from the external power supply from 5V to 3V to apply the same to the field effect type semiconductor device 3. The field effect type semiconductor device is formed on a substrate 4. On the peripheral portions of the substrate 4, arranged are power supply terminals 5 and input terminals 6 for exchanging data with external circuits (for example a central processing unit, CPU). Supply lines Q are arranged connecting the above mentioned power supply terminals 5, memory cell arrays 9, a decoder 8, and controlling portions 7. The voltage of 3V form the supply terminal 5 is supplied to the memory cell arrays 9, the decoder 8, and the controlling portions 7 through the supply lines Q. The controlling portions 7 are connected to the input/output terminals 6, and the controlling portions 7 control input/output of data.

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The decoder 8 provided at the central portion of the substrate decodes instructions from the controlling portions 7 to read data from or write data to a memory at a prescribed address in the memory cell arrays 9.

By separately providing a supply voltage adjusting circuit for lowering the voltage to 3V in addition to the power supply of 5V, the field effect type semiconductor device can be driven at a suitable level.

However, separate provision of the supply voltage adjusting circuit has a disadvantage that the area of the printed circuit board on which the field effect type semiconductor device is formed is increased, and it leads to higher cost.

In addition, the length of.power supply lines arranged in the substrate 3 are different, so that voltages applied to the controlling portions 7, the decoder 8, and memory cell arrays 9 become uneven dependent on the arrangement, which may prevent stable operation. SUMMARY OF THE INVENTION

Therefore, one object of the present invention is to provide a supply voltage adjusting circuit of a field effect type semiconductor device in which it is not necessary to separately provide a supply voltage setting circuit.

Another object of the present invention is to lower, in a MOSFET device, the supply voltage to the operation level of the MOSFET without reducing degree of integration thereof.

A further object of the present invention is to set the supply voltage to the operation level of the MOSFET and to decrease the number of necessary manufacturing steps to set the voltage to the operation level in the M10SFET device.

Briefly stated, in the present invention, an integrated circuit including a field effect transistor, a power supply terminal to be connected to an external power supply, and a plurality of voltage lowering circuits for lowering power supply voltage supplied through the supply terminal to a suitable operation level of the field effect transistor are formed on the same substrate, the voltage lowering circuits arranged distributed on the periphery of the integrated circuit.

In operation, even if a DC voltage at high potential is inputted from the external power supply, the voltage lowering crcuits formed in the field effect type semiconductor device lower the supply voltage to a suitable operation level of the field effect transistor, whereby the field effect type transistor can be accurately driven. By distributing a plurality of voltage lowering circuits around the integrated circuit, potentials at various portions can be prevented from being uneven derived from difference in length of interconnection.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram showing one embodiment of a supply voltage adjusting circuit of a field effect type semiconductor device in accordance with the present invention; Fig. 2 shows a connection between the peripheral portion of the memory cell array and the voltage lowering circuit; Fig..3 is a cross sectional view of the portion surrounded by a broken line of Fig. 2; Fig. 4A is a schematic diagram of a logic circuit as an example of the field effect type semiconductor device;

Fig. 4B is an equivalent circuit diagram thereof; Fig. SA is a cross sectional view showing another embodiment; Fig. 5B is an equivalent circuit diagram thereof; Fig. 6 is a cross sectional view showing a dynamic RAM as an example of the field effect type semiconductor device; and

Fig. 7 is a block diagram in which an external power-supply is connected to a field effect type semiconductor device. Description of Preferred Embodiments

Fig. 1 is a block diagram showing one eibodiment cf, a supply voltage adjusting circuit of a field effect type semiconductor device in accordance with the present invention. Referring to the figure, the external power supply 1, the substrate 4, the power supply terminal 5, the input/output terminals 6, the controlling portions 7, the decoder 8 and the memory cell arrays 9 are the same as those shown in Fig. 7.

The feature of the present embodiment is provision of voltage lowering circuits 10 arranged distributed on the periphery of the integrated circuits such as the controlling portions 7, the decoder 8 and the memory cell arrays 9 on the substrate 3.

The voltage lowering circuit 10 lowers the voltage of 5V supplied through the power supply terminal 5 to about 3V which is the operation level of a MOSFET having the gate length not longer than 0.5 lim. The voltage 1 (3V) is applied to the controlling portions 7, the decoder 8 and the memory cell arrays 9. The controlling portions 7 control the decoder 8 and the memory cell arrays 9 in response to a signal from a CPU (not shown) or the like, and control input/output of data through the input/output terminals 6. The decoder 8 decodes instructions inputted through the controlling portions 7 to write data and to read data from memory cells of prescribed addresses.

Fig. 2 shows a connection between the peripheral portion of the memory cell array 9 and the voltage lowering circuit 10.

Referring to the figure, the power supply terminal is connected to the collector of an NPN type transistor 10a through the power supply line 1. The base of the transistor 10a is connected to the source of a P channel type MOSPET10b. N channel type MOSFETs10c are connected in series to the source of the P type MOSFET10b. Therefore, a reference voltage determined by the product of the threshold voltage of the N type MOSFET x the number of the N type MOSFETs10c is applied to the base of the transistor 10a. The NPN ty-pe transistor 10a lowers the voltage 5V approximately to the potential of the reference voltage. However, since the threshold potential of the transistor 10a itself is about 0.7 V, the reference voltage should preferably be set at about 3.7 V so as to set the output voltage to 3V. Instead of the NPN type transistor 10a, an N type MOSFET may be formed. However, when an N type MOSFET is used, the output voltage changes as V. = VG - % - r 21D dependent on the change of consumed current caused by the load (such as memory cells). In the equation, the reference character ID denotes drain current, P denotes mutual conductance, VG represents gate voltage and VTE represents the threshold voltage.

The memory cells 9a are formed of N type MOSFETs or the like having the gate length of 0.5[im, and they are connected at intersections between the word line W-L and bit line pair BL, BL. Complementary MOSFETs 8a and multiinput AND gates 8b are portions of the decoder 8, which output write signal.read signal to a prescribed word line WL to raise the memory cells 9a on the word line WL. The raised memory cell 9a writes data from the bit line pair BL, BL and outputs data to the bit line pair BL, BL.

Fig. 3 is a cross sectional view of the portion surrounded by a broken line of Fig. 2. A static RAM is shown in the figure as an example. Referring to the figure, the NPN transistor 10a, the P type MOSFET 10b and the N type MOSFET 10c of the voltage lowering circuit 10 are formed simultaneously with the formation of the memory cell array 9.

When the N type MOSFET of the static RAM is formed, for example, a P type well region is formed by diffusion in an N type substrate 4, two N regions are formed on the P type well, and a gate electrode of 0.5ptm is formed between the N regions with an insulator posed therebetween. As to the P type MOSFET, two P regions are formed on the N type substrate, and the gate electrode is arranged between the P regions. Simultaneously with the formation of the P type well, a P type well region is formed by diffusion to form the NPN transistor 10a, and an emitter region is formed simultaneously with the N regions (source, drain). The base region is formed simultaneously with the P region of the P type MOSFET. The N type substrate 3 is used as the collector. The P type MOSFET 10b and the N type MOSFET 10c can be simultaneously formed with the complementary-metal oxide semiconductor C-MOS 8a. In order to prevent latch up between the NPN transistor 10a and the C-MOS 8a and P type MOSFET 10b, N+ guard bands are provided between the transistor 10a and the C-MOS 8a and between the transistor 10a and the P type MOSFET 10b. The guard band is spaced apart by a distance d is from the C-MOS 8a and from the P type MOSFET 10b, respectively.

As described above, the NPN transistor 10a, the P type MOSFET 10b and the N type MOSFET 10c can be formed in parallel with the formation of the memory cells 9. Since the voltage lowering circuits 10 are distributed, the length of interconnection can be made even, the supply voltage applied to various portions such as the controlling portions 7, decoder 8, and the memory cells 9 is made uniform, preventing possible malfunction. In addition, it is not necessary to enlarge the area of the substrate 4 to form the transistors 10a in marginal spaces around the memory cells 9.

Fig. 4A is a schematic diagram of a logic circuit as an example of the field effect type semiconductor device, and Fig. 4B is an equivalent circuit diagram thereof.

Referring to the figures, the logic circuit 11 comprises a P type MOSFET, an N type MOSFET and a C-MOS including a P type MOSFET and an N type MOSFET each having the gate length not longer than 0.5gm, integrated therein. The voltage lowering circuit 10 is formed on the same substrate by the same manufacturing steps as the P type MOSFETs and the N type MOSFETs of the logic circuit 11. A guard band (not shown) is provided z 1 between the logic circuit 11 and the voltage lowering circuit 10, and the guard band and the logic circuit 11 is spaced apart by a distance d, which is short enough not to affect the degree of integration.

Although only one logic circuit 11 is shown in the figure, a plurality of logic circuits are formed on the substrate, and the voltage lowering circuits 10 are distributed around the plurality of logic circuits 11.

Fig. 5A is a cross sectional view showing another embodiment, and Fig. 5B is an equivalent circuit diagram thereof.

This embodiment is different from that of Fig. 1 in that transistors 10al, 10a2 and 10a3 are Darlington connected. The three stages of transistors 10al, 10a2 and 10a3 are formed simultaneously with the formation of the memory cell arrays 9 and the logic circuits 11, as in the above embodiment. By providing a plurality of stages of transistors, the current capacity can be increased, and the MOSFETs can be driven with stable voltage. Since three stages of Darlington connection is employed, the reference voltage is set higher by 0.7 x 3V, in consideration of the fall of the voltage of about 0.7 x 3V. Although a Darlington circuit of three stages is shown in the present embodiment, a Darlington circuit of two stages or four or more stages may be used.

Fig. 6 is a cross sectional view showing a dynamic RAM as an example of the field effect type semiconductor device. Referring to the figure, in a case of a dynamic RAM, when a P type MOSFET is formed, an N type well is formed by diffusion in a P type substrate, P regions are formed in the N type well region, which P regions will be the drain and the source, and a gate electrode is arranged on a channel. A P- having lower impurity concentration is formed by diffusion on the N type well, and on the Pregion, an N region is f ormed as a collector. Namely, different from the formation of the static PAY-, described above, a step of forming the Pregion to form the NPN transistor 10a is added.

By the above described method, the transistor 10a of the voltage lowering circuit 10 can be formed in the dynamic RAM.

As described above, in the present invention, the voltage lowering circuits are formed together with the memory circuits and logic circuits formed of field effect type transistors on the same substrate, whereby it becomes unnecessary to provide separately a supply voltage setting circuit in order to drive the field effect type transistors. Consequently, it is not necessary to enlarge the printed circuit board as in the conventional device, and the cost can be lowered. By distributing the voltage lowering circuits, the length of interconnections between the voltage lowering circuits and the loads can be made approximately uniform, which prevent influence of voltage lowering caused by the different lengths of interconnection, and therefore the field effect type transistors can be operated stably.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

Claims

WHAT IS CLAIMED IS

1. A supply voltage adjusting circuit of a field effect type semiconductor device, comprising, on a substrate, an integrated circuit including a field effect type transistor, power supply terminal to be connected to an external power supply, and plurality of voltage lowering means for lowering a supply voltage supplied through the power supply terminal to a suitable operation level of the field effect type transistor, said voltage lowering means arranged distributed around said integrated circuit.

2. A supply voltage adjusting circuit according to claim 1, wherein said supply voltage adjusting circuit comprises a bipolar transistor connected in series between the power supply terminal and a semiconductor integrated circuit, and a reference voltage setting circuit applying a reference voltage to a control terminal of the bipolar transistor.

3. A supply voltage adjusting circuit according to claim 1, wherein said substrate is N type, and a P region and an N region formed simultaneously with a MOSFET serve as the base and the emitter of the bipolar transistor.

4. A supply voltage adjusting circuit according to claim 1, wherein said substrate is P type, wherein an N-well is formed simultaneously with formation of a P type MOSFET, a P- region is f ormed by dif f usion af ter the f ormation of the Nwell to provide the base of the bipolar transistor, an N region is formed on said P- region simultaneously with formation-of an N type MOSFET to provide a collector of the bipolar transistor.

5.

A supply voltage adjusting circuit according to claim 2,1 wherein said reference voltage setting circuit comprises at least one MOSFET formed simultaneously with formation of the semiconductor integrated circuit.

6. a supply voltage adjusting circuit according to claim 3, wherein said supply voltage adjusting circuit comprises an 1.

N + guard band formed between an NPN type bipolar transistor and a P type MOSFET.

7. A supply voltage adjusting circuit of a field effect type semiconductor device, constructed, adapted and arranged substantially as described hereinbefore with reference to and as shown in figures 1 to 6 of the drawings.

Published 1991 at The Pateni Office. Concepi House. Cardifi Road. Newport. Gwent NP9 1 RH. Furiher copies mai. be obtained from Sales Branch. Unit 6. Nine Mile Point, Cik-mfelinfach- Cross Kevs. Newport. NPI 7HZ. Printed by Multiplex techniques ltd. St Mary Cray- Kent- 1