JP2791522B2 - Mask ROM and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM and a method of manufacturing the same, and more particularly, to a mask ROM which is advantageous for increasing the capacity.
And its manufacturing method.

[0002]

2. Description of the Related Art Memory ICs that are currently used can be roughly classified according to their write functions. RWMs (read / write memories) which can be freely written together with read-out after manufacture, and read-only memories which cannot be written after manufacture. ROM (read only memory) used. The ROM is used for storing fixed information such as character patterns because the stored information remains even after the power is turned off.
Further, the ROM is capable of electrically changing stored information after manufacture and erasing stored information by irradiation with ultraviolet rays.
PROM (Erasable and Program)
and a mask ROM in which information is written in a manufacturing process and whose stored information cannot be changed after manufacturing. The mask ROM stores character patterns on CRT displays and BAS on personal computers.
Often used to store fixed data such as IC programs.

[0003] Mask ROMs already commercialized at present
Memory array section generally includes MOS transistors arranged in a matrix. This MOS transistor is used as a memory cell. On the other hand, when a MOS transistor is formed on a semiconductor substrate, three regions of a source, a drain, and a gate are required. These three
The dimensions of one region must be large enough to function as a MOS transistor, and cannot be reduced without limit. Therefore, contrary to the recent demand for miniaturization of semiconductor integrated circuit devices, MOS
As long as transistors are used, there is naturally a limit to miniaturization of the area of the entire memory array section. In particular, this problem becomes particularly serious as the storage capacity of the mask ROM increases. On the other hand, demands for increasing the storage capacity of memory ICs including a mask ROM have been increasing in recent years. Therefore, a mask ROM for responding to conflicting demands for miniaturization of various semiconductor integrated circuit devices including a memory IC and an increase in storage capacity of the memory IC has been proposed.
Consideration is being given to both miniaturization of each memory cell and increase in the number of bits of information stored in each memory cell.

[0004] First, a mask ROM devised from the viewpoint of miniaturization of each memory cell will be described. According to such an improved mask ROM, an element having a diode structure is used as a memory cell instead of an element having a MOS transistor structure.

FIG. 16 shows the structure of a memory array of an improved mask ROM disclosed in Japanese Patent Publication No. 61-1904. FIG. 16A is a plan view, and FIG.
FIGS. 17B and 17C are cross-sectional views of the memory cell array shown in FIG. Referring to FIG. 16, this memory cell array
It is formed on a semiconductor substrate 40 of single crystal silicon. The substrate 40 has an insulating film (not shown) formed of a silicon oxide film on its surface. On this substrate 40, a number of strip-shaped N-type polysilicon layers 49 are provided in parallel. Further, the insulating layer 41 is provided on the entire surface of the semiconductor substrate 40 including the polysilicon layer 42. An opening, that is, a contact hole 44 is selectively provided in the insulating layer 41. By introducing impurities into the polysilicon layer 42 below the contact hole 44, a P-type polysilicon region 45 is formed. On the insulating layer 41 and the contact holes 44, a number of parallel strip-shaped conductive layers 43 are provided so as to cross the polysilicon layer 42. Contact hole 44 is selectively provided at the intersection of polysilicon layer 42 and conductive layer 43. Each of the strip-shaped polysilicon layers 42 corresponds to a different word line, and each of the strip-shaped conductive layers 43 corresponds to a different bit line.

As can be seen from FIG. 16A, the intersections between the plurality of strip-shaped polysilicon layers 42 and the plurality of strip-shaped conductive layers 43 form a matrix. Further, referring to FIGS. 16B and 16C, a PN junction is formed in polysilicon layer 42 below contact hole 44 only at the intersection where contact hole 44 is provided. Therefore, when a forward voltage is applied to the conductive layer 43 at the intersection where the contact hole 44 is provided, a current flows through the polysilicon layer 42. On the other hand, even if a forward voltage is applied to the conductive layer 43 at the intersection where the contact hole 44 is not provided, the conductive layer 43 and the polysilicon layer 42 are insulated by the insulating layer 41, so that the polysilicon layer 42
No current flows through Therefore, when a certain bit line is selected, a predetermined voltage is applied thereto, and a certain word line is selected to determine the presence or absence of a current flowing therethrough, the conductive layer 43 corresponding to the selected bit line is selected. It can be determined whether or not a contact hole is provided at the intersection with the polysilicon layer 42 corresponding to the word line. Therefore, the presence or absence of the contact hole is made to correspond to the logical values 1 and 0, respectively,
If the formation pattern of the contact hole is determined according to the information to be stored in the mask ROM, the stored information can be read from the manufactured mask ROM as in the related art. That is, instead of using one MOS transistor as a conventional memory cell, one PN junction, that is, one diode is used. Therefore, the area required for one memory cell is determined by the respective widths of conductive layer 43 and polysilicon layer 42.

[0007] The minimum value of the width of the conductive layer 43 and the polysilicon layer 42 is determined by the limit value of the line and space in the current manufacturing technology. Therefore, by reducing these widths (to the extent that contact holes 44 can be provided), the area occupied by one memory cell on the substrate can be made much smaller than in the past. Therefore, it is possible to obtain a much smaller mask ROM than when a MOS transistor is used as a memory cell as in the related art.

Next, a manufacturing process of a mask ROM having a memory cell array as shown in FIG.
19 will be described with reference to FIG. 17 to 19 are cross-sectional views showing an example of a manufacturing process of such a mask ROM.

First, as shown in FIG. 17A, an N-type impurity is selectively diffused on the main surface of a P-type substrate 111 having a low impurity concentration to form an N-well region 112 as an island.
Is formed. Next, oxide film 113 is formed on the main surface of substrate 111, including on N well region 112.
(B)). Oxide film 113 forms a memory cell array portion A, a P-channel MOS transistor region B constituting a peripheral portion of memory cell array portion A, and an N-channel MOS transistor region.
An oxide film for element isolation is formed thick at a boundary portion between the S transistor regions C, and is formed thin in each of the regions A, B and C so that the permeability of impurities is not impaired. Next, it corresponds to the memory cell array section A.
On the main surface of the substrate 111, the N-type polysilicon layer 4 of FIG.
The conductive layer 114 corresponding to No. 2 is formed. Conductive layer 114
Are arranged as a plurality of strip-shaped conductive layers perpendicular to the main surface to form word lines (FIG. 17C).

Subsequently, as shown in FIG. 18A, a polysilicon layer 11 is formed as a gate electrode and a wiring layer in each of a P-channel MOS transistor region B and an N-channel MOS transistor region C which are peripheral portions.
A conductive layer including the metal layer 5 and the metal layer 116 is formed on the main surface of the substrate 111, and an oxide film 113 for insulation is formed again on the main surface of the substrate 111. next,
As shown in FIG. 18B, the memory cell array unit A
, An opening 201 is selectively provided in an oxide film 113 and a register material 202 laminated on the oxide film 113. The polysilicon layer 114 below the opening 201
By introducing a P-type impurity into P-type impurity, a P-type polysilicon region 203 is formed. Subsequently, an N-type region 117 forming a drain and a source is formed in the N-channel MOS transistor region C by selectively diffusing an N-type impurity on the main surface of the substrate 111. further,
A P-type region 118 serving as a source and a drain of a P-channel MOS transistor is also formed on N well 112 by selectively diffusing a P-type impurity (FIG. 1).
8 (c)). Thereafter, an insulating film 119 is formed on the entire main surface of the substrate 111 in order to fill and flatten the steps on the entire main surface of the substrate 111. Next, as shown in FIG. 18D, a contact hole 120 is selectively formed in the insulating layer constituted by the insulating film 119 and the oxide film 113. The contact hole 120 is formed so as to expose the P-type polysilicon region 203 in the memory cell array portion A and to expose the surface of the N-type region 117 in the N-channel MOS transistor region.
The OS transistor region B is provided such that the surface of the P-type region 118 is exposed.

Subsequently, as shown in FIG. 19, a conductive layer 121 made of a metal such as aluminum is selectively formed on the insulating film 119 so as to enter the contact hole 120. In the memory cell array section A, the conductive layer 121 is an N-type polysilicon layer 1 forming a word line.
A plurality of strips are formed on the insulating film 119 so as to be orthogonal to each of the fourteen. Each of the plurality of conductive layers 121 corresponds to one bit line. On the other hand, in peripheral portions B and C, conductive layer 121 forms a wiring connected to the source and drain of the MOS transistor.

In the case of the mask ROM manufactured as described above, only the one corresponding to the memory cell MC from which data is to be read out of the plurality of strip-shaped conductive layers 121 each forming one word line. A positive voltage is applied, and the presence or absence of a current flowing through a plurality of band-shaped conductive layers 114 each forming one bit line, corresponding to the memory cell MC, is detected. According to the detection result, it is determined whether the storage data of the memory cell MC is a logical value “0” or “1”. This memory cell MC has a P-type region 1
If there is a PN junction formed by the N-type region 17 and the N-type region 114, the PN junction becomes forward-biased in response to the application of a voltage to the conductive layer 121 as a bit line, so that a corresponding word line is formed. A current flows through the conductive layer 114. In the selected word line, there is a possibility that the contact hole 120 exists at the intersection with another unselected bit line. However, a PN junction exists in each of the contact holes 120 and these are in a reverse bias state, so that the current flowing through the word line 114 does not flow out to other unselected bit lines. If the memory cell MC does not have a PN junction, no contact hole 120 is formed between the memory cell MC and the corresponding bit line, so that no current flows through the memory cell MC.

FIGS. 20 and 22A are cross-sectional views showing the structure of each memory cell in a conventional mask ROM devised from the viewpoint of increasing the number of bits of data stored in each memory cell.

FIG. 20 shows that each memory cell has one MOS transistor.
A case is shown in which a multi-level semiconductor memory device in which a plurality of bits of information are stored in each memory cell is realized using a conventional mask ROM memory cell structure including transistors.

Referring to FIG. 20, each memory cell is formed as a drain and a source on a semiconductor substrate 31, respectively, and has an impurity diffusion layer 32 having a polarity opposite to that of semiconductor substrate 31.
a and 32b, and a gate electrode 33 formed on the semiconductor substrate 31 via an insulating film 34 so as to extend between the impurity diffusion layers 32a and 32b. Semiconductor substrate 3
Reference numeral 1 denotes, for example, a P ^- type semiconductor substrate having a low impurity concentration, and the gate electrode 33 is formed of, for example, polysilicon or the like. Unlike a conventional mask ROM that stores one-bit data, each memory cell is stored in a portion corresponding to a portion between the source 32b and the drain 32a on the surface of the semiconductor substrate 31, that is, in the channel region 35, that is, in the memory cell. An impurity having the same polarity as the impurity added to the drain 32a and the source 32b is added by ion implantation or the like at a concentration corresponding to the power data. The concentration of the impurity added to the channel region 35 of the memory cell constituting one memory array is set to a plurality of types.

The threshold voltage of the MOS transistor increases as the gate voltage required to cause a so-called inversion layer having a polarity opposite to that of the semiconductor substrate 31 in the channel region 35 increases. The higher the impurity concentration in the channel region 35, the closer the electrical polarity of the channel region 35 to that of the source 32b and the drain 32a. An inversion layer is formed in the channel region 35 without increasing the applied voltage (when the substrate 31 is N-type) so much. Therefore, by changing the concentration of the impurity added to the channel region 35 for each memory cell, 1
The electrical characteristics of the MOS transistors constituting the memory cells included in one memory array are set to a plurality of types.

That is, if the concentration of the impurity added to the channel region 35 is m, the memory cell included in one memory array has the highest impurity concentration in the channel region 35, and therefore the threshold voltage is low. The impurity concentration in the lowest first memory cell group, the channel region 35, is lower than that in the first memory cell group, so that the second memory has a higher threshold voltage than that of the first memory cell group. .., The channel region 35 is classified into the m-th memory cell group having the lowest impurity concentration and therefore having the highest threshold voltage.

FIG. 21 shows the relationship between the gate potential of a MOS transistor having four different threshold voltages V _TH1 , V _TH2 , V _TH3 , and V _TH4 , and the current Ids flowing between the drain 32a and the source 32b. It is a graph which shows a relationship. In FIG. 21, curve 4
1, 42, 43, and 44 are a MOS transistor having a threshold voltage V _TH1 and a threshold voltage V _TH1 , respectively.
MOS transistor having a threshold voltage V _TH2 higher than _TH1 , a MOS transistor having a threshold voltage V _TH3 higher than the threshold voltage V _TH2 , and a threshold higher than the threshold voltage V _TH3 The current Ids and the gate potential V of the MOS transistor having the voltage V _TH4
Shows the relationship with _G. FIG. 21 shows the drain 32a
And source 32b at 5V and 0V, respectively.

As can be seen from the curves 41 to 44, as the impurity concentration of the channel region 35 decreases, the electrical characteristics of the MOS transistor are set to the enhancement type. As the impurity concentration increases, the electrical characteristics of the MOS transistor increase. Is set to be more depletion type. Therefore, by setting the gate potential V _G of these four MOS transistors the same potential V0b, the magnitude of the current Ids flowing between the drain 32a and the source 32b is greatest in the MOS transistor having a threshold voltage V _TH1 Value I1 and the threshold voltage V
_{In the} MOS transistor having the threshold voltage V _TH3 , the MOS transistor having the threshold voltage V _TH3 has a value I2 smaller than I1.
The value becomes I3 which is smaller than I2 in the transistor, and becomes 0 in the MOS transistor having the threshold voltage V _TH4 . That is, the magnitude of the current Ids flowing between the drain 32a and the source 32b differs between these four types of MOS transistors. Therefore, these 4
The stored data of the type of MOS transistors, the gate potential V _G, the potential of the drain 32a, and the potential of the source 32b respectively V0b, 5V, the current flowing when the OV magnitude I1, I2, depending on I3,0 If four types of data different from each other are used, a mask ROM in which 2-bit information is stored in one memory cell in advance is realized.

That is, a drain 32a, a source 32b, and a gate 33 of a memory cell from which stored data is to be read.
Are set to 5 V, 0 V, and V0b, respectively, and the magnitude of the current Ids flowing between the drain 32a and the source 32b is detected.
It is possible to determine which of the four types of data is.

Further, such a conventional general mask R
A multivalued memory obtained without using the OM memory cell structure is disclosed in Japanese Patent Application Laid-Open No. 58-122694.

FIG. 22 (a) shows an example of Japanese Patent Application Laid-Open No. 58-12269.
FIG. 5 is a cross-sectional view showing a memory cell structure in the multi-level memory shown in FIG. FIG. 23 is a graph showing electrical characteristics of the memory cell having the structure shown in FIG.

FIG. 22B is a plan view showing the structure of the memory cell array of this multi-valued memory. As shown in FIG. 22B, a plurality of electrode conductors 51 are formed in a band shape, and a plurality of electrode conductors 53 are formed in a band shape so as to intersect with the plurality of electrode conductors 51. Each of the intersections 500 of the plurality of electrode conductors 51 and 53 is used as one memory cell. FIG. 22A shows a cross-sectional structure of a portion corresponding to one of these intersections 500.

Referring to FIG. 22, each memory cell includes an electrode conductor 51 formed of aluminum, an insulator 52 formed on the electrode conductor 51, and an electrode formed of Pb on the insulator 52. And a conductor 53. The insulator 52 is formed of Al ₂ O ₅ . At the boundary between the insulator 52 and the electrode conductor 53, an additional substance 54 such as benzene, benzoic acid or the like is provided according to data stored in the memory cell.
Is added.

Referring to FIG. 23, electrode conductors 51 and 5
As you increase the voltage V applied between 3 and reaches the magnitude V _T corresponding to the energy of the specific excitation mode to the voltage addition material 54, by inelastic tunneling electrode conductor 51 and 53 The current I flowing therebetween increases rapidly. The voltage V _T, for example, if the additive material 54 is benzene, a 0.36V, the additive material 54 is 0.4V if der benzoate. Thus, the type of material 54 to be added to the boundary between the insulator 52 and the electrode conductor 53, surge point V _T of the current I flowing between the electrodes conductors 51 and 53 are different. If such an additional substance 54 is not added to the boundary between the insulator 52 and the electrode conductor 53, such an inelastic tunnel effect does not occur, so that the voltage applied between the electrode conductors 51 and 53 is increased. However, the current I does not increase rapidly.

Therefore, if the rate of increase dI / dV of the current I flowing between the electrode conductors 51 and 53 with respect to the voltage V applied between the electrode conductors 51 and 53 is detected, it is determined whether there is a sharp increase point V _T of the current I. whether and, depending on the magnitude of the voltage V at the surge point V _T, presence and type of additive material between the insulator 52 and the electrode conductor 53 of the memory cell can be determined. Therefore, if two or more types of substances are used as the additive substance 54, a plurality of bits of data can be stored in one memory cell.

For example, when two types of benzene and benzoic acid are used as the additive substance 54, one memory cell array includes a memory cell to which the additive substance 54 is not added, a memory cell to which benzene is added as the additive substance 54, And three types of memory cells to which benzoic acid is added as the additive substance 54. Therefore, if the storage data of these three types of memory cells are made to correspond to the three types of data in accordance with the presence or absence of the additional substance 54 at the boundary between the insulator 52 and the electrode conductor 53 and the type of the additional substance 54, The increase rate dI / d in each memory cell
By detecting V, it is determined which of the three types of data is stored data of each memory cell by determining whether or not there is a sudden increase point V _T of the current I and between the electrode conductors 51 and 53 at the sudden increase point V _T. Can be determined based on the magnitude of the voltage V. In other words, in FIG.
If two or more types of substances are added, the number of sudden increases in the current flowing between the electrode conductors 51 and 53 becomes two or more, so that a portion corresponding to the intersection between the electrode conductors 51 and 53 has two bits or more. Information can be stored, and a multi-valued memory is realized.

[0028]

As described above, in view of miniaturization of each memory cell, in a semiconductor memory device proposed as a mask ROM which is advantageous for increasing the capacity, each word line has one word line. A plurality of strip-shaped first
A conductive layer and a plurality of strip-shaped second layers provided so as to be orthogonal to the first conductive layers and each forming one bit line;
A PN junction for selectively electrically connecting the first conductive layer and the second conductive layer is provided at a portion corresponding to the intersection with the conductive layer. Each of these intersections functions as one memory cell. According to such a mask ROM, memory cells can be miniaturized, which is advantageous for increasing the capacity. However, since it is necessary to selectively form a PN junction,
The manufacturing process is not always simple.

At present, a mask ROM already commercialized
Many of those proposed as mask ROM type semiconductor storage devices using memory cells having a simple structure that is completely different from and advantageous in increasing the capacity are often formed by one memory cell formed by one PN junction. Type of mask ROM.

On the other hand, in the conventional multilevel memory, the magnitude of the current flowing between the drain and the source in the MOS transistor is variable depending on the impurity concentration in the channel region, This is realized by utilizing the fact that the point of sudden increase due to the inelastic tunnel effect is variable depending on the type of substance added to the boundary between the insulator and one of the conductors. However, such a conventional multi-valued memory has the following problems.

First, when a plurality of bits of data are stored in one memory cell by setting the impurity concentration in the channel region in multiple stages, the structure of each memory cell is the field effect transistor type as shown in FIG. Become. Therefore, each memory cell requires a region corresponding to a gate, a drain, and a source on a semiconductor substrate. For this reason, although the amount of information that can be stored in each memory cell increases, the number of memory cells that can be formed on one chip cannot be increased so much. There is.
Further, the memory cells on the same chip are
5, it is necessary to make three or more types with different impurity concentrations, so that the process of ion implantation into the channel region 35 becomes complicated.

On the other hand, in a multi-valued memory utilizing the inelastic tunnel effect (see FIG. 22), each of intersections 500 of strip-shaped conductors 51 and 53 formed with an insulator 52 interposed therebetween is used as one memory cell. Therefore, the area required for each memory cell is determined only by the width of conductors 51 and 53. Therefore, by reducing these widths, the area occupied by each memory cell can be made much smaller than when a MOS transistor is used as each memory cell. Therefore, such a multi-valued memory is superior to the above-described multi-valued memory in terms of improving the degree of integration of the storage device. However, the memory cells must be divided into a plurality of types (including those to which the additional substance 54 is not added) in which the type of the additional substance 54 added to the interface between the insulator 52 and the conductor 53 is different. The additive material 54 must be selectively added to the interface between the conductor and the conductor 53. For this reason, in order to store more information in one memory cell, the types of substances added to the interface between the insulator 52 and the conductor 53 must be increased. Therefore, it is difficult to control in the manufacturing stage.

Accordingly, an object of the present invention is to solve the above-mentioned problems, to improve the integration density of memory cells on a chip without using a PN junction, and to store data in one memory cell. An object of the present invention is to provide a large-capacity mask ROM capable of increasing the amount of information to be obtained.

[0034]

According to an aspect of the present invention, a mask ROM according to the present invention includes a semiconductor substrate having a main surface and a semiconductor substrate having a main surface. A plurality of first signal lines formed at intervals; an insulating film formed on the plurality of first signal lines with a film thickness controlled in accordance with data to be stored in the mask ROM; A plurality of second signal lines formed thereon. The plurality of second signal lines are arranged at right and left intervals so as to intersect each of the plurality of first signal lines at a plurality of intersections. The insulating film is formed at any one of a plurality of predetermined thicknesses at each of the portions corresponding to the plurality of intersections.

The plurality of predetermined thicknesses are all set in response to the application of a high voltage between the corresponding first signal line and the corresponding second signal line.
The thickness may be a range in which a tunnel current can flow between signal lines, or may include both a thickness in a range in which such a tunnel current cannot flow and a thickness in a range in which a tunnel current can flow.

According to another aspect, a mask ROM according to the present invention includes a semiconductor substrate having a main surface, a plurality of parallel first signal lines extending in a column direction on the main surface, and a plurality of the first signal lines. An insulating film formed on the first signal line with a film thickness controlled in accordance with data to be stored in the mask ROM; a plurality of parallel second signal lines formed on the insulating film; A tunnel current detecting means for detecting the presence or absence of a tunnel current flowing through the first signal line or the second signal line to generate an output data signal.

The plurality of second signal lines extend in the row direction so as to cross each of the plurality of first signal lines at a plurality of intersections. The insulating film is formed at a plurality of intersections by the mask RO.
M has predetermined first and second thicknesses according to data to be stored in M.

According to still another aspect, a mask ROM according to the present invention includes a semiconductor substrate having a main surface, a plurality of first signal lines extending in a column direction on the main surface, and a plurality of first signal lines. An insulating film formed on one signal line by controlling the film thickness in accordance with data to be stored in the mask ROM; a plurality of parallel second signal lines formed on the insulating film; Sensing means for sensing an amount of current flowing through the signal line or the second signal line to generate an output data signal.

The plurality of second signal lines extend in the row direction so as to cross each of the plurality of first signal lines at a plurality of intersections. The insulating film has predetermined first and second thicknesses at portions corresponding to the plurality of intersections according to data to be stored in the mask ROM. At the intersection where the insulating film has the first thickness, a first tunnel current is generated, and at the intersection where the insulating film has the second thickness, a second tunnel current having a magnitude different from the first tunnel current is generated.
Is applied between any one of the first signal lines and any one of the second signal lines. The sensing means comprises the first
A data output signal is generated by sensing whether the current of the signal line or the current of the one second signal line is the first tunnel current or the second tunnel current.

According to still another aspect, a method of manufacturing a mask ROM according to the present invention includes the steps of: forming a plurality of first signal lines on a main surface of a semiconductor substrate at right and left intervals; Forming an insulating film on the first signal line, and arranging a plurality of second signal lines on the insulating film so as to intersect each of the plurality of first signal lines at a plurality of intersections. And forming.

In the step of forming the insulating film, the portions corresponding to the plurality of intersections are stored in any one of a plurality of predetermined thicknesses in accordance with data to be stored in the mask ROM. The method further includes the step of: The plurality of types of thicknesses cause a tunnel between the corresponding first signal line and the corresponding second signal line in response to application of a high voltage between the corresponding first signal line and the corresponding second signal line. At least one thickness where current can flow
Including one.

[0042]

According to one aspect, the mask ROM includes a plurality of first ROMs.
The insulating film interposed between the signal line and the plurality of second signal lines has at least one thickness in a range where a tunnel phenomenon can occur at a portion corresponding to an intersection between the first signal line and the second signal line. The thickness is set to any one of a plurality of predetermined thicknesses. For this reason, if the portion corresponding to the intersection of the first signal line and the second signal line is made to correspond to the same number of different data as the number of types of the film thickness in accordance with the thickness of the insulating film, the first At each intersection of the signal line and the second signal line, data of the number of bits corresponding to the number of types of film thickness can be stored. That is, each intersection constitutes one memory cell storing one or more bits of data.

According to another aspect, in the mask ROM according to the present invention, the insulating film interposed between the first signal line and the plurality of second signal lines includes the insulating film interposed between the first signal line and the second signal line. Each portion corresponding to the intersection has a predetermined first thickness or a predetermined second thickness. According to this aspect,
Since the tunnel current detecting means for detecting a tunnel current from the first signal line or the second signal line is provided, the first thickness is so thin as to cause a tunnel phenomenon and the second thickness is so small as not to cause the tunnel phenomenon. If a high voltage is applied to the insulating film interposed at the intersection of one first signal line and one second signal line, the tunnel current detection means Only when the thickness is the first thickness, the generation of the tunnel current is detected.

According to still another aspect, in the mask ROM according to the present invention, in each of the portions corresponding to the intersections of the first signal line and the second signal line, the first portion of the mask ROM is in a range where the tunneling phenomenon occurs in the insulating film. Or the second thickness. Further, according to this aspect, whether the current generated in the first signal line or the second signal line matches the magnitude of the first tunnel current flowing through the insulating film having the first thickness, There is provided a sensing means for sensing whether the current value matches the magnitude of the second tunnel current flowing through the insulating film having the second thickness.
A data signal corresponding to the thickness of the insulating film interposed at the intersection of one first signal line and one second signal line is generated from the sensing means.

According to still another aspect, the method of manufacturing a mask ROM according to the present invention is configured as described above, and the thickness of the insulating film at the intersection of the first signal line and the second signal line is thus set. Are manufactured in a plurality of thicknesses, including a thickness at which tunneling can occur. Therefore, a high voltage is applied to the insulating film interposed at the intersection of one first signal line and one second signal line via the one first signal line and the one second signal line. For example, a tunnel current having a magnitude corresponding to the thickness of the insulating film at this intersection may be a first tunnel current corresponding to this intersection.
It flows to the signal line or the second signal line. Therefore, by detecting the magnitude (including 0) of this tunnel current, the thickness of the insulating film at this intersection can be known.

[0046]

FIG. 1 is a diagram showing the structure of a memory cell array section of a mask ROM according to one embodiment of the present invention. 1A is a plan view, and FIGS. 1B and 1C are cross-sectional views of the memory cell array shown in FIG. 1A taken along broken lines A and B, respectively. FIG. 1 (b)
3C and 3C show the cross-sectional structure of the memory cell array in a slightly simplified manner.

Referring to FIG. 1, the memory cell array of the mask ROM has a plurality of strip-shaped conductive layers 3 formed on a single-crystal silicon substrate 1 in parallel with each other, and is orthogonal to the plurality of strip-shaped conductive layers 3. And a plurality of strip-shaped conductive layers 6 formed in parallel on conductive layer 3 with oxide film 4 interposed therebetween. Each of the band-shaped conductive layers 3 corresponds to one bit line, and each of the other band-shaped conductive layers 6 corresponds to one word line. The conductive layer 3 is formed by an impurity diffusion layer, and the conductive layer 6 is formed by polysilicon or the like. As in the case of the mask ROM shown in FIG. 16, each intersection 5 between the strip-shaped conductive layer 3 forming a bit line and the strip-shaped conductive layer 6 forming a word line corresponds to one memory cell 5. However, in this embodiment, each memory cell 5 does not include a PN junction. In this embodiment, the storage data of each memory cell is determined in advance according to the thickness of oxide film 4 between conductive layers 3 and 6 in the memory cell region. That is, the memory cells 5 in the memory cell array are classified into a memory cell 5a having a thin oxide film between the conductive layers 3 and 6, and a memory cell 5b having a thick oxide film 4 between the oxide films 3 and 6. The thickness of oxide film 4 between conductive layers 3 and 6 in memory cell 5a is such that electrons move from conductive layer 3 to conductive layer 6 via oxide film 4 in response to application of a high voltage to conductive layer 6. Thin enough to cause a so-called tunnel phenomenon.
On the other hand, the thickness of oxide film 4 between conductive layers 3 and 6 in memory cell 5b is so large that such a tunnel phenomenon does not occur. The thickness of oxide film 4 in memory cell 5a is, for example, about 70 ° to 100 °, and the thickness of oxide film 4 in memory cell 5b is, for example, about 400 ° to 500 °. Note that an isolation layer 2 for electrically isolating the memory cells 5 from each other is provided below the oxide film 4.

FIG. 5 shows the electric field strength E induced by the oxide film 4 provided between the two conductive layers 3 and 6,
6 is a graph showing a relationship between a current I _OX flowing between two conductive layers 3 and 6; The electric field strength E depends on the voltage V applied between these two conductive layers 3 and 6 and the thickness t of the oxide film 4.
_{From OX} , it is calculated by V / t _OX .

Referring to FIG. 5, the thickness t _OX of oxide film 4 is 1
If it is very thin at about 0 °, as can be seen from curve 1,
If the voltage applied between conductive layers 3 and 6 is greater than 0 V, a current always flows between conductive layers 3 and 6 via oxide film 4. That is, if the thickness of oxide film 4 between conductive layers 3 and 6 is too small, oxide film 4 no longer functions as an insulating film.

However, if the thickness t _OX of oxide film 4 is, for example, 1
In the case of about 00 °, as can be seen from curve 2, the voltage applied between conductive layers 3 and 6
If it is not large enough to induce a high electric field of about MV / cm, no current flows between conductive layers 3 and 6 via oxide film 4. 10M between the conductive layers 3 and 6
When a high voltage that induces a high electric field of about V / cm is applied, electrons in the oxide film 4 move to the conductive layer on the high potential side due to a tunnel phenomenon, thereby oxidizing between the conductive layers 3 and 6. An electric current flows through the membrane 4.

If the thickness t _OX of oxide film 4 is as large as about several hundreds of mm, the tunnel phenomenon described above will occur no matter how large the voltage applied between conductive layers 3 and 6 is. No current flows between the conductive layers 3 and 6 via the oxide film 4.

Therefore, a high voltage is applied to any one of the plurality of strip-shaped conductive layers 6 so as to generate an electric field having a strength of about 10 MV / cm in the oxide film 4 having a thickness of about 70 ° to 100 °. When the voltage is applied and one of the plurality of strip-shaped conductive layers 3 is grounded, there exists between the conductive layers 3 and 6 at the intersection of the one strip-shaped conductive layer 3 and the one strip-shaped conductive layer 6. When the thickness of the oxide film 4 is small, a current (tunnel current) flows from the one conductive layer 6 to the one conductive layer 3 due to a tunnel phenomenon. However, if the oxide film 4 existing between the conductive layers 3 and 6 at this intersection is thick, a tunnel phenomenon does not occur, and no current flows through the one conductive layer 3. That is, depending on the presence or absence of the tunnel oxide film in each memory cell, the presence or absence of the current flowing through the strip-shaped conductive layer 3 corresponding to the memory cell is determined. Therefore,
If data "0" and "1" correspond to the presence or absence of a tunnel oxide film in each memory cell, data can be read from each memory cell 5. Therefore, if a tunnel oxide film is selectively provided in advance at the intersection between the strip-shaped conductive layers 3 and 6 according to the data pattern to be stored in the memory cell array, the memory cell array functions as a read-only memory. .

As for the tunnel current, see, for example, the document “Electronic Material Series” “Submicron Device I”.
I "P. 27-P. 34 ".

FIG. 2 is a schematic block diagram showing the entire configuration of the mask ROM of this embodiment. FIG. 2 shows a case where memory cells are arranged in a matrix of 3 rows × 3 columns in a memory cell array for simplicity. Further, in FIG. 2, the memory cell 5a having a tunnel oxide film and the memory cell 5b having no tunnel oxide film in FIG. 1 are represented by symbols.

Referring to FIG. 2, memory cell array 300
Are three bit lines B1 to B3 and three word lines W1
To W3, and the memory cells Mij (i =
1, 2, 3: j = 1, 2, 3). Bit lines B1 to
B3 and the word lines W1 to W3 correspond to the strip-shaped conductive layers 3 and 6, respectively, in FIG. The memory cells M12, 21, and M23 are memory cells having no tunnel oxide film (memory cell 5b in FIG. 1), and the other memory cells M11, M13, M22, M31,
M32 and M33 are memory cells having a tunnel oxide film (memory cell 5a in FIG. 1).

To read data from memory cell array 300, address buffer 310, X decoder 320, control circuit 330, Y decoder 340, Y gate 350, sense circuit 360, output buffer 370, and high voltage application circuits 381-383 Is provided. The high voltage application circuits 381, 382, and 383 each have X
It is provided between decoder 320 and word lines W1, W2, and W3. Sense circuit 360 includes three sense amplifiers 361-363. Y gate 350 includes an N-channel MOS transistor YG1 connected between bit line B1 and sense amplifier 361, an N-channel MOS transistor YG2 connected between bit line B2 and sense circuit 362, and a bit line B3. -Channel MOS transistor YG3 connected between the memory cell and sense amplifier 363
And ON of transistors YG1, YG2, YG3
/ OFF is the output signal Y of the Y decoder 340, respectively.
1, Y2, and Y3. High voltage application circuits 381, 382, and 383 are controlled by output signals X1, X2, and X3 of X decoder 320, respectively.

Address buffer 310 buffers an externally applied address signal to address terminals A0-Am to provide X decoder 320 and Y decoder 340.
Give to. The X decoder 320 is used for the address buffer 31
0, and decodes the address signal from the high voltage application circuit (any one of 381 to 383) provided corresponding to any one of the three word lines W1 to W3.
Only the potential level of the control signal (any one of X1 to X3) to be applied to the high voltage application circuit is set to a value that can activate the high voltage application circuit. The activated high voltage application circuits 381 to 383 apply a high voltage of, for example, about 10 to 15 V to the corresponding word lines W1 to W3. Therefore, a high voltage is applied to only one of the word lines W1 to W3 corresponding to the address signal.

The Y decoder 340 is connected to the address buffer 3
10 and decodes the address signal from bit line B1.
B3 connected to one of the transistors YG1 to YG3, and controls only the potential of a control signal (any of Y1 to Y3) for controlling the conduction state of the transistor (any of YG1 to YG3). , N-channel MOS transistor
The voltage is raised to a potential that can be set to the N state. Therefore, of the transistors YG1 to YG3, only those connected to the bit line corresponding to the address signal are turned on. Thus, only one bit line corresponding to the address signal is electrically connected to the corresponding sense amplifier in sense circuit 360. Sense amplifiers 361, 362,
And 363 are transistors YG1 and YG, respectively.
2, and the presence or absence of a current flowing through YG3 is detected, and a data signal corresponding to the detection result is supplied to output buffer 370. Output buffer 370 includes sense amplifiers 361-36.
3 buffers the data signal output and supplies it to data output terminals OUT0 to OUTn.

FIG. 6 shows the sense amplifier 361 in FIG.
363 is a circuit diagram illustrating a configuration example. FIG. FIG. 6 representatively shows a configuration of one sense amplifier 361. In the following description, a low-active signal is indicated by a “/”.

Referring to FIG. 6, when sense amplifier activation signal / SE is at the low level, sense amplifier 361
Operates to read data stored in any one of the memory cells connected to bit line B1. Activation signal / S
When E is at a low level, the P-channel MOS transistor Q1 and the N-channel MOS transistor Q2 are turned on and off, respectively.
A high-level potential is applied from a normal voltage source Vcc that supplies V. Thereby, N-channel MOS transistors Q4 and Q6 are both turned on. Between the transistor Q6 and the normal voltage source Vcc, a P-channel MOS transistor
5 is connected.

Therefore, transistors Q4 and Q6
Is turned on, the gate potential of N-channel MOS transistor Q3 is raised by normal voltage source Vcc. On the other hand, N-channel MOS transistor Q7
Is in the OFF state in response to the low-level activation signal / SE. Therefore, the gate potential of the transistor Q3 becomes higher than the threshold voltage of the transistor Q3, and the transistor Q3 is turned on.

As a result, the potential of node N3 starts to decrease, and the current flowing through transistors Q4 and Q6 decreases. Therefore, the potentials of nodes N1 and N2 begin to decrease. However, when the potential of node N1 becomes lower than the threshold voltage of transistor Q3, transistor Q3
3 is turned off, the potential of the node N3 starts to rise again by the current supplied from the transistor Q1. Thereby, transistors Q4 and Q6
The current flowing to the nodes N1 and N2
Potential rises again.

As a result, when the potential of the node N1 exceeds the threshold voltage of the transistor Q3, the transistor Q3 is turned on again to lower the potential of the node N3.

By repeating such a circuit operation, the potentials of nodes N1 and N2 are stabilized to a certain value, for example, the potential of node N1 is stabilized to about 1V. Therefore, when the transfer gate YG1 is turned on, the bit line B1
Is applied with about 1V.

For example, when reading data from memory cell M21, a high voltage of, for example, about 10 V is applied to word line W2. However, since the memory cell M21 has no tunnel oxide film, no current flows through the bit line B1.
Therefore, the potentials of nodes N1 and N2 are
It is kept at a constant value as described above.

For example, when reading data from memory cell M11, the above-described high voltage is applied to word line W1. Since the memory cell M11 has a tunnel oxide film, the bit line B1 responds to the application of such a high voltage.
Current flows through Therefore, the transfer gate YG
When 1 is turned on, the potential of the node N1 starts to decrease from the above-described constant value. Thereby, the node N
The potential of 1 drops below the threshold voltage of the transistor Q3, the potential of the node N3 rises due to the turning off of the transistor Q3, the current flowing through the transistors Q4 and Q6 increases due to the rise of the potential of the node N3, Node N due to increase in current flowing through Q6
1 and N2, the conduction of the transistor Q3 due to the rise of the potential of the node N1, the fall of the potential of the node N3 due to the ON state of the transistor Q3, the decrease of the current flowing through the transistors Q4 and Q6 due to the fall of the potential of the node N3, and The circuit operation of lowering the potential of nodes N1 and N2 due to the decrease in the current flowing through transistors Q4 and Q6 starts to be repeated again. As a result, node N
The potential of 1, that is, the potential of the bit line B1 and the potential of the node N2 are each stabilized at a value lower than the above-described constant value.

As described above, the potential of the node N2 is stabilized to a different value depending on whether or not a current flows through the bit line B1, after the transfer gate YG1 is turned on.

The threshold voltage of inverter G1 is set to a value between the potential at node N2 when no current flows through bit line B1 and the potential at node N2 when current flows through bit line B1. . Therefore, the output voltage S _OUT of the inverter G1 is applied to the transfer gate YG when reading data from the memory cell M21 having no tunnel oxide film.
1 in response to conduction, and at the time of reading data from the memory cell M11 having the tunnel oxide film, it goes high in response to conduction of the transfer gate YG1.

Control circuit 330 outputs a negative active chip enable signal CE for instructing whether or not this mask ROM chip should operate, and a data signal output from output buffer 370 to data output terminals OUT0 to OUTn. Buffering a negative active output enable signal OE, which instructs whether to inhibit or allow the operation. Further, the control circuit 330 controls the Y decoder 340 and the output buffer 3 based on these buffered signals.
A control signal for enabling or disabling the operation of each of the 70 is output.

Each of bit lines B1 to B3 is connected to Y gate 35
While the corresponding transistors YG1 to YG3 in 0 are in the ON state, the corresponding sense amplifiers 361 to 363 are grounded.

As described above, in this mask ROM, the word line and the bit line connected to the memory cell from which data is to be read for data reading are respectively provided.
High voltage and ground potential are applied. Next, the data reading principle of the mask ROM will be described with reference to FIG. FIG. 3 is a diagram showing a difference in electrical characteristics between a memory cell having a tunnel oxide film and a memory cell having no tunnel oxide film.

FIG. 3 shows the magnitude of the current flowing through the bit line connected to the memory cell 5a having the tunnel oxide film and the magnitude of the current flowing through the bit line connected to the memory cell 5b having no tunnel oxide film. The size is shown in tabular format.

In this table, _VL indicates a potential in a range where a tunnel phenomenon cannot occur in a memory cell having a tunnel oxide film, and _VH indicates a potential in a memory cell having a tunnel oxide film. A potential range, for example, 10 V to 15 V is shown.

Referring to FIGS. 1 and 3, a ground potential and a high voltage are applied to a bit line (conductive layer 3) and a word line (conductive layer 6) corresponding to memory cell 5a having a tunnel oxide film, respectively. Then, a current flows from the corresponding word line to the ground via the tunnel oxide film 4 and the corresponding bit line. The magnitude of this current is several tens of μ
It is about A. However, if the potential of the word line connected to the memory cell 5a having the tunnel oxide film is not such a high voltage but a potential in the range of _VL , a high electric field sufficient to cause a tunnel phenomenon in the oxide film 4 is obtained. , No tunnel current flows. Therefore, in such a case, no current flows through the corresponding bit line. next,
It is assumed that the corresponding bit line is floating. In such a case, since the corresponding bit line is not electrically connected to any, no current flows through the corresponding bit line regardless of the potential of the corresponding word line.

On the other hand, even if a ground potential and a high potential are applied to the bit line and the word line corresponding to memory cell 5b having no tunnel oxide film, conductive layers 3 and 6
Since there is a thick oxide film 4 between them, no tunnel current flows between them. That is, no current flows through the bit line corresponding to the memory cell 5b having no tunnel oxide film regardless of the potential of the word line corresponding to the memory cell 5b. The memory cell 5 having no tunnel oxide film
Regarding b, if the corresponding bit line is in a floating state, no current flows through the bit line regardless of the potential of the corresponding word line.

Therefore, by configuring the peripheral circuit for reading data from the memory cell array as shown in FIG. 2, data can be read only from desired memory cells in the memory cell array. For example, in FIG. 2, the memory cells M22 are connected to the address terminals A0 to Am.
It is assumed that an external address signal designating the address is given. In this case, the high voltage application circuit 382 is activated by the X decoder 320, while the Y decoder 3 is activated.
40 turns on the transistor YG2.
As a result, only the potential of the word line W2 becomes a high potential of about 10 to 15 V, and the potentials of the other word lines W1 and W3 become V
_The potential becomes low within the range of _L, the ground potential is applied only to the bit line B2, and the other bit lines B1 and B3 enter a floating state. Therefore, they are connected to word lines W1 and W3 to which no high potential is applied (hereinafter referred to as unselected word lines). None of the six memory cells M11 to M13 and M31 to M33 can pass a current to the corresponding bit lines B1 to B3 regardless of whether or not they have a tunnel oxide film. Further, the transistor Y in the OFF state among the transistors YG1 to YG3 included in the Y gate 350
Bit lines (hereinafter, referred to as unselected bit lines) B1 and B3 connected to G1 and YG3 have memory cells M11, M21, and M31 respectively connected thereto.
No current flows regardless of whether M13, M23, and M33 have a tunnel oxide film. Therefore, a word line at a high potential (hereinafter referred to as a selected word line)
W2 and the ON-state transistor Y in the Y gate 350
The structure of a memory cell (hereinafter referred to as a selected memory cell) M22 provided corresponding to an intersection with a bit line (hereinafter referred to as a selected bit line) B2 connected to G2 (the tunnel oxide film is referred to as a selected bit line). Only) determines whether there is a current flowing through the selected bit line B2. Since the memory cell M22 has a tunnel oxide film, a current flows through the bit line B2. The sense circuit 362 detects this current and outputs a data signal corresponding to a logical value “0” or “1”. Conversely, if the selected memory cell does not have a tunnel oxide film, no current flows through the selected bit line, and none of the sense amplifiers 361-363 detect the current. In this case, the sense amplifier 3
61 to 363 output a data signal corresponding to a logical value opposite to the logical value of the data signal output when the current is detected. Therefore, output buffer 370 outputs the storage data of the memory cell located at the address indicated by the address signal.

FIG. 4 is a circuit diagram showing an example of the configuration of the high voltage application circuits 381-383. FIG. 21 representatively shows a high voltage application circuit 381.

Referring to FIG. 4, high voltage application circuit 381
Is connected between P-channel MOS transistor 400 and N-channel MOS transistor 410 receiving the corresponding output signal X1 of X decoder 320 via N-channel MOS transistor 430 at the gate, and between high voltage source Vpp and the gates of transistors 400 and 410 And a P-channel MOS transistor 420 provided at the same time. Transistors 400 and 410 are connected in series between high voltage source Vpp supplying a high voltage of about 10 V to 15 V and ground to form an inverter. The connection point between transistors 400 and 410 is connected to corresponding word line W1 and the gate of transistor 420. As the high voltage Vpp, a high voltage of about 10 to 15 V, for example, 12.5 V is constantly output.

The transistor 430 has a predetermined control signal φ.
Is received by the gate, and is turned on for a certain period during data reading. When the logic level of the control signal X1 is high, the transistor 410 is turned on, and the ground potential is supplied to the word line W1. At the same time, the transistor 420 is turned on.
The high potential supplied to the gate of the transistor 410 via the gate fixes the transistor 410 to the ON state. However, when the logic level of the signal X1 becomes low, the transistor 400 is turned on, so that a high potential of 10 to 15 V is supplied to the word line W1 from the high voltage source Vpp. At the same time, since the transistor 420 is turned off, a high potential is not applied to the gate of the transistor 400 from the high voltage source Vpp, so that the transistor 400 is fixed to the on state.

When the logic level of the gate potential of transistors 400 and 410 is determined by output signal X1 of X decoder 320, control signal φ goes low and transistor 430 is turned off. As a result, the output potential of the X decoder 320 does not affect the potential of the input terminal of the high voltage application circuit 381.

Generally, the output potential range of X decoder 320 is 0 V to 5 V. That is, the X decoder 320
Is configured to output 5 V as a high-level potential and output 0 V as a low-level potential. Therefore, when the transistor 430 is always on, when the signal X1 is at the high level, the gates of the transistors 400 and 410 are electrically connected to the high voltage source Vpp by the transistor 420 while the X decoder 32
0 to a potential lower than the output potential of the high voltage source Vpp is supplied. As a result, the gate potential of transistors 400 and 410 decreases. In order to avoid such a phenomenon, the transistor 430 is connected to the high voltage application circuit 381 by X.
The decoder 320 is turned ON only for the time required to take in the output signal X1 of the decoder 320.

When the word line W1 is to be set to a low potential within the range _VL , that is, a high-level potential is applied as the signal X1 to the high voltage applying circuit 381 via the transistor 430.
When the transistor 420 is not present, the gate potential of the transistor 400 becomes a potential (5 V) lower than the source potential (the output potential of the high voltage source Vpp of 10 V to 15 V). Therefore, the transistor 41
Since not only 0 but also the transistor 400 is turned on, the potential of the word line W1 does not drop to the original potential corresponding to the low level. However, when the transistor 420 exists, in such a case, the output potential of the high voltage source Vpp is supplied to the gate of the transistor 400 by the transistor 420 which is turned on. Therefore, such a problem does not occur because the transistor 400 is turned off.

The high voltage application circuits 382 and 383 also have
A circuit having the configuration shown in FIG. 21 may be used. When a circuit having the configuration shown in FIG. 21 is used for each of high voltage applying circuits 381 to 383, X decoder 320 corresponds to a word line connected to a memory cell indicated by an address signal from address buffer 310. A low-level signal is output only to the high-voltage application circuit provided, and a high-level signal is output to the other high-voltage application circuits. Thus, a high voltage is applied only to the word line corresponding to the memory cell indicated by the address signal.

As described above, in the memory cell array of the mask ROM of the present embodiment, the first
Each of the vertically overlapping portions of the strip-shaped conductive layer and the second strip-shaped conductive layer forming the word line form one memory cell. The data stored in each memory cell is determined by the thickness of the oxide film existing between the first band-shaped conductive layer and the second band-shaped conductive layer in that region. Therefore, the area required for one memory cell is determined by the width of the first band-shaped conductive layer and the width of the second band-shaped conductive layer. The minimum of these widths is determined by the line and space limits of current manufacturing technology. Therefore, as in the case of the conventional mask ROM in which one memory cell is formed by one PN junction, by reducing these widths, the area occupied by one memory cell on the semiconductor substrate is extremely reduced. can do. That is, according to the mask ROM of the present embodiment, the MO
It is possible to obtain a micro mask ROM which is much more advantageous in increasing the capacity than when an S transistor is used.

Next, an example of a method of manufacturing the mask ROM of this embodiment will be described with reference to FIGS. 7 to 9 are partial cross-sectional views showing a first example of the manufacturing process of the mask ROM of the present embodiment. 10 to 12 are partial cross-sectional views showing a second example of the manufacturing process of the mask ROM of this embodiment. 7 to 12 are cross-sectional views of the mask ROM of the present embodiment, taken along a broken line A in FIG.

First, as shown in FIG. 7A, the main surface of the P-type substrate 111 having a low impurity concentration corresponds to the peripheral portions B and C other than the memory cell array portion A where the memory cell array is to be formed. N-type impurities are selectively introduced into portions where the N-well 112 is formed. N-well 112 is located at P of peripheral portions B and C.
A channel MOS transistor is formed in a P-channel MOS transistor region B where a channel MOS transistor is to be formed. Next, an oxide film 113 is formed on the main surface of the substrate 111 including on the N well 112 by a selective oxidation method or the like. The oxide film 113
As shown in FIG. 7B, the memory cell array units A,
P channel MOS transistor B and N channel M
An oxide film for element isolation is formed thick between the N-channel MOS transistor region C where the OS transistor is to be formed and between the regions MC where the memory cells are to be formed in the memory cell array portion A, and in other regions, It is formed thin so as not to impair the permeability of impurities. Next, a conductive layer 200 formed by the polysilicon layer 115 and the metal layer 116 corresponding to the peripheral portions B and C is selectively formed on the main surface of the substrate 111 (see FIG. 7C). . The conductive layer 200 is a P-channel MOS
It is used as a gate in each of transistor region B and N-channel MOS transistor region C.

Subsequently, substrate 11 corresponding to memory cell array portion A and N-channel MOS transistor region C is formed.
An N-type impurity is selectively implanted on the main surface of substrate 1, and a P-type impurity is selectively implanted on the main surface of substrate 111 corresponding to P-channel MOS transistor region B. Thus, in the memory cell array portion A, the P-channel MOS transistor region B, and the N-channel MOS transistor region C, a plurality of band-shaped N-type impurity diffusion layers 122 and P-channel MO
A P-type impurity diffusion layer 118 functioning as a source and a drain of the S transistor and an N-type impurity diffusion layer 117 functioning as a source and a drain of the N-channel MOS transistor are formed. Each of the N-type diffusion layers 122 is used as one bit line. Next, in order to eliminate the level difference between the surfaces of the peripheral portions B and C, the insulating film 1 is formed only on the portion corresponding to the peripheral portions B and C on the main surface of the substrate 111 including the oxide film 113 and the conductive layer 200.
19 are formed (see FIG. 8A). Next, FIG.
As shown in (b), a contact hole 120 is selectively formed in the insulating film 119. In P channel MOS transistor region B, contact hole 120 is provided such that P type impurity diffusion layer 118 is exposed, and N
In channel MOS transistor region C, contact hole 120 is provided such that N-type impurity diffusion layer 117 is exposed. Next, as shown in FIG.
A portion of the oxide film 113 corresponding to each of the regions MC where the memory cells are to be formed is selectively processed according to the stored data so as to have a thickness at which a tunnel phenomenon can occur. As a result, a tunnel oxide film 123 is formed at a predetermined position corresponding to the data stored in the memory cell array.

Finally, a conductive layer 124 made of a metal such as aluminum is selectively formed on oxide film 113, tunnel oxide film 123, and insulating film 119. FIG.
, A plurality of conductive layers 124 are formed in the memory cell array portion A in a strip shape so as to be orthogonal to each of the N-type impurity diffusion layers 122. In the memory cell array section A, one conductive layer 124 is used as one bit line. In peripheral portions B and C, conductive layer 124 is formed of MOS.
It is used as a wiring connected to the source and the drain of the transistor.

According to such a manufacturing method, the step of storing data in the memory cell array, that is, the step of selectively forming a tunnel oxide film in a region where each memory cell is to be formed, is a method of manufacturing a mask ROM. Incorporated later in the process. On the other hand, which memory cell in the memory cell array is provided with the tunnel oxide film is determined by the mask ROM.
Depends on the data to be stored. Therefore, after receiving the designation of the data from the user (mask ROM
From the viewpoint of shortening the period (turnaround time) from receiving the order of manufacture of the product to delivery of the ordered product to the user, the step of forming the tunnel oxide film requires the mask ROM chip as in the above example. It is more advantageous to incorporate it in the latter half of the manufacturing process.

Next, another manufacturing method will be described. First, an N well 112 and an oxide film 113 are formed on the main surface of a P-type substrate 111 having a low impurity concentration in the same order as in the above-described example of the manufacturing method (see FIGS. 10A and 10B). ). Next, an N-type impurity is selectively implanted only into a portion corresponding to the memory cell array portion A in the main surface of the substrate 111. As a result, as shown in FIG. 10C, a plurality of band-shaped N-type impurity diffusion layers 122 each used as one word line and extending in a direction perpendicular to the paper surface are formed.

Next, only a portion of the oxide film 113 corresponding to each of the regions MC where the memory cells are to be formed,
Processing is selectively performed according to data to be stored in the memory cell array section A so as to have a thickness at which a tunnel phenomenon can occur. As a result, as shown in FIG. 11A, the tunnel oxide film 123 is formed in some of the regions MC where the memory cells are to be formed. Thereafter, a conductive layer 200 having a two-layer structure including the polysilicon layer 115 and the metal layer 116 is selectively formed on the oxide film 113 including the tunnel oxide film 123 (see FIG. 11B). In the memory cell array section A, the conductive layer 200
Are formed in a plurality of strips so as to be orthogonal to each of the N-type impurity diffusion layers 122. Each of these strip-shaped conductive layers 200 is used as one word line. In the peripheral portions B and C, the conductive layer 200 is used as a gate electrode. Next, of the main surface of the substrate 111, a P-channel MOS
P-type impurities are selectively implanted into portions corresponding to transistor regions B, and N-type impurities are selectively implanted into portions of the main surface of substrate 111 corresponding to N-channel MOS transistor regions C. As a result, FIG.
, A P-type impurity diffusion layer 118 used as a source and a drain is formed in a P-channel MOS transistor region B, and an N-type impurity diffusion layer 117 used as a source and a drain also in an N-channel MOS transistor C Is formed. Next, an insulating film 119 is formed on the entire main surface of the substrate 111 in order to reduce the steps on the surfaces of the memory cell array portion A and the peripheral portions B and C.

Next, as shown in FIG. 12A, a contact hole 120 is selectively formed in the insulating film 119. In the memory cell array portion A, the contact hole 120 is provided so that the conductive layer 200 is exposed.
In P channel MOS transistor region B, contact hole 120 is provided such that P type impurity diffusion layer 118 is exposed. In N channel MOS transistor region C, contact hole 120 is provided such that N type impurity diffusion layer 117 is exposed. Finally, FIG.
As shown in (b), a conductive layer 121 made of a metal such as aluminum is selectively formed on the insulating film 119 so as to fill the contact hole 120. In the memory cell array portion A, the conductive layer 121 is provided as a wiring connected to the conductive layer 200 having a two-layer structure as a word line. In the peripheral portions B and C, the conductive layer 12
Reference numeral 1 is used as a wiring connected to the source and drain of the MOS transistor.

As described above, according to this manufacturing method, the step of forming a tunnel oxide film for storing data in the memory cell array is incorporated in the first half of the mask ROM manufacturing step. However, there is an advantage that an insulating film for planarizing the surface of the substrate need not be selectively formed only in a part of the region, and that the word line and the gate electrode of the MOS transistor can be formed simultaneously. .

As described above, since the manufacturing method of the mask ROM of this embodiment is not unique, if a manufacturing method according to the structural conditions and purpose of the product is selected from the possible manufacturing methods, Good.

Next, two methods will be described as specific examples of a method of forming a tunnel oxide film in the steps shown in FIGS. 9 and 11A. In the first method, only a portion corresponding to a region where a memory cell having a tunnel oxide film is to be formed in the oxide film 113 in FIGS. It is a method to remove until it becomes. FIG.
FIG. 3 is a cross-sectional view for explaining a second method. FIG.
2 shows a sectional view of a portion corresponding to a region where one memory cell having a tunnel oxide film is to be formed. According to the second method, first, a contact hole-shaped opening is provided in oxide film 113 such that N-type impurity diffusion layer 122 serving as a word line is exposed (FIG. 13A,
(B)). Thereafter, as shown in FIG. 13C, the surface of the exposed N-type diffusion layer 122 and the oxide film 113 are exposed.
The surface is thinly oxidized. As a result, a thin oxide film 123 that can cause a tunnel phenomenon is formed only in the portion of the N-type diffusion layer 122 where the opening is provided.

FIG. 14A is a sectional view showing the structure of an arbitrary memory cell in a mask ROM according to another embodiment of the present invention. FIG. 14B is a plan view and a cross-sectional view showing the structure of the memory cell array in the mask ROM of this example.

Referring to FIG. 14A, in the mask ROM of this embodiment, each memory cell has a first conductive layer 12 formed by an N type impurity diffusion layer on a P ⁻ type semiconductor substrate 11. And an insulating film 14 formed of silicon oxide or the like on the conductive layer 12, and a second conductive layer 1 formed of metal or polysilicon on the insulating film 14.
3 is included. Insulating film 1 on N-type impurity diffusion layer 12
The thickness of 4 is so small that electrons move from the conductive layer 13 to the N-type impurity diffusion layer 12 through the insulating film 14 in response to application of a high voltage to the conductive layer 13, that is, a so-called tunnel phenomenon occurs. . A portion where the film thickness is adjusted to such a thickness (a portion surrounded by a broken line in the figure) is called a tunnel oxide film. The thickness of the tunnel oxide film in each memory cell is determined according to data to be stored in the memory cell.

Next, prior to the structure of the memory cell array, the operation principle of the memory cells in the mask ROM of this embodiment will be described with reference to FIG. FIG.
Is the thickness t _TUN of the tunnel oxide film 15 and the current J _TUN that flows between the conductive layers 12 and 13 by a tunnel phenomenon when a constant high electric field is applied between the conductive layers 12 and 13 (hereinafter referred to as a tunnel current). 6 is a graph showing a relationship with the graph.

For the tunnel current, see, for example, the document “Analysis and Modeling of Floating-Gate EEPROM Ce”.
lls (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL,
ED-33, NO. 6, JUNE 1986, P835-844) ".

According to the above document, when an electric field having a magnitude represented by E _TUN is applied between the conductive layers 12 and 13, the tunnel oxide film 15 is formed between the conductive layers 12 and 13.
The magnitude J _{TUN of the} current flowing through is expressed by the following equation.

[0101]

(Equation 1)

In the above equation (1), α and β both represent constants. Here, the electric field E _{TU N,} using a voltage applied VTUN in the film thickness t _TUN and the conductive layer 13 of the tunnel oxide film 15 is expressed by the following equation.

[0103]

(Equation 2)

Therefore, the above equations (1) and (2)
Then, the voltage V_TUNFlow when applying
Channel current J_TUNThe size of the tunnel oxide film 15
Thickness t _TUNYou can ask for each. FIG.
Tunnel referenced based on equations (1) and (2)
Oxide film thickness t_TUNAnd tunnel current J_TUNShows the relationship
Is done.

As can be seen from FIG. 15, when the thickness t _TUN of the tunnel oxide film is very large, the tunnel current J
The size of _{TUN is} a very small value that is hardly affected by the thickness t _TUN of the tunnel oxide film. However, the film thickness t _TUN
Is sufficiently thin, the tunnel current J _TUN becomes sufficiently large, and greatly changes according to the thickness t _TUN of the tunnel oxide film 15. For example, when applied voltage V _TUN to conductive layer 13 is about 25 V, current J _TUN flowing between conductive layers 12 and 13 through tunnel oxide film 15 having a thickness t _TUN of 10 nm is about several tens μA. . Therefore, in a given memory cell, by applying a voltage of a predetermined magnitude to the conductive layer 13 and detecting the magnitude of the tunnel current flowing at this time, the thickness of the tunnel oxide film 15 in this memory cell can be determined. Can be.

Therefore, if memory cells in the memory cell array are divided into three or more types having different thicknesses of the tunnel oxide film 15, data of a plurality of bits is stored in one memory cell. For example, when memory cells are formed into three types having different thicknesses of the tunnel oxide film 15,
If the storage data of these three types of memory cells are made to correspond to the three types of data according to the thickness of the tunnel oxide film 15, the conductive layer 13 of the memory cell from which the storage data is to be read has a predetermined size (for example, 25V). By detecting the magnitude of the tunnel current flowing between the conductive layers 12 and 13 of the memory cell when the voltage of (3) is applied, which of the three types of data is stored in the memory cell is detected. Can be determined.

More specifically, as can be seen from FIG. 15, if the magnitude of the voltage V _TUN applied to the conductive layer 13 is the same,
A memory cell having a _smaller thickness t _TUN of the tunnel oxide film 15 has a larger tunnel current J _TUN . Therefore, the above 3
Type of tunnel current flowing through the memory cell having a tunnel oxide film 15 of the thinnest thickness t _TUN1 of the memory cell size I _TUN1, the thickest thickness t _TUN3 tunnel oxide film 1
Of the tunnel current flowing through the memory cell having
_TUN3, and magnitude I of a tunnel current flowing through the memory cell having the oxide film 15 of these intermediate thickness t _{TUN2 TUN2}
It is possible to read the stored data, that is, the thickness of the tunnel oxide film 15 of the desired memory cell, by determining which of the above two cases corresponds to the magnitude of the detected tunnel current.

Next, the structure of the memory cell array in the mask ROM of this embodiment will be described with reference to FIG. FIG. 14B illustrates a case where three types of data can be stored in each memory cell.

The memory cell array includes a plurality of first conductive layers 12 formed in a band shape on a P ⁻ type semiconductor substrate 11 and a semiconductor substrate 1 including the plurality of band-shaped first conductive layers 12.
1, an insulating film 14 formed over the entire surface,
A plurality of strip-shaped second conductive layers formed in parallel to each other so as to be orthogonal to each of the plurality of first conductive layers; The thickness of the insulating film 14 at the intersection 100 between the first conductive layer 12 and the second conductive layer 13 is, for example, t in FIG.
_TUN1 , _tTUN2 , and _tTUN3 are preliminarily formed at the time of manufacturing. Each of these intersections 100 is 1
Used as one memory cell. In FIG. 14A,
A cross-sectional view of any one of these intersections 100 is shown.

Therefore, this memory cell array has
Memory cell 1 having tunnel oxide film 15 having a thickness of _TUN1
Including a 00a, a memory cell 100b having a film thickness of the tunnel oxide film 15 t _TUN2, and a memory cell 100c having a film thickness of the tunnel oxide film 15 of t _TUN3. To read data stored in any one of the memory cells in the memory cell array, the potential of one of the plurality of first conductive layers 12 corresponding to the memory cell and the plurality of second conductive layers 1
3, one of which corresponds to this memory cell is set to a predetermined high potential (for example, about 25 V) and 0
V, and at this time, a current flowing through the first or second conductive layer 12 or 13 corresponding to the memory cell may be detected as the above-described tunnel current J _TUN .

As described above, according to the present embodiment, the amount of data stored in one memory cell is increased by utilizing the fact that the magnitude of the tunnel current varies depending on the thickness of the tunnel oxide film. . The tunnel oxide film 15 is, for example, an electrically erasable and reproducible (EEPROM) which is a read-only memory device that can be electrically written and erased.
A memory cell can be formed by applying a conventionally used technique when forming a memory cell in a manufacturing process of a programmable read only memory. Therefore, the memory cell array of the present embodiment is realized by a relatively simple manufacturing process using the conventional manufacturing technology.

The occupied area of each memory cell on semiconductor substrate 11 is determined by the width of first conductive layers 11 and 13. Therefore, since the minimum value of the occupied area is determined by the limit value of the line and space in the current manufacturing technology, each memory cell of the mask ROM can be made much smaller than the memory cell of the field effect transistor type. .

As described above, according to the present embodiment, a plurality of bits of data are stored in each memory cell in advance, and
A memory cell array that is advantageous for increasing the capacity of memory cells on a chip can be obtained by a relatively simple manufacturing process. Therefore, the amount of information that can be stored in the same area in the semiconductor memory device is drastically increased by the application of the conventional manufacturing technology, so that a large-capacity mask ROM is realized.

In the above embodiment, the first conductive layer 12, the second conductive layer 13, and the insulating film 14 are formed on the P ⁻ type semiconductor substrate.
Is shown, but the same effect can be obtained even if these are formed on an N ⁻ type semiconductor substrate. Also, the first conductive layer 12, the second conductive layer 13, and the insulating film 1
4 is an impurity diffusion layer, a metal or polysilicon,
And it is not necessarily formed of silicon oxide, and may be formed of another material as long as data can be read on the above-described principle.

Further, in the memory cell array of the above embodiment, the thickness of the tunnel oxide film of the memory cell is three types, but when the thickness of the tunnel oxide film of the memory cell is divided into four or more types. However, the same effect as in the above embodiment can be obtained.

Note that the specific numerical values such as the voltage value and the current value shown in the description of the above embodiment are standard values obtained based on current manufacturing technology, experimental data, and the like.
In practice, it may vary according to various conditions.

[0117]

As described above, according to the present invention, by setting the thickness of the insulating film at the intersection of the first strip-shaped conductive layer and the second strip-shaped feature point layer to be two or more, the mask RO can be formed.
The degree of integration of memory cells in M can be greatly improved. Further, the thickness of the insulating film at the intersection is set to three or more types in a range where a tunnel phenomenon can occur, or three types of thicknesses in a range in which a tunnel phenomenon cannot occur and two or more in a range where a tunnel phenomenon can occur. By doing the above, 1
Since the amount of information stored in one memory cell increases to 2 bits or more, the storage capacity of the mask ROM dramatically increases.

Therefore, it is possible to obtain a mask ROM which can miniaturize and simplify the structure of each memory cell and is extremely advantageous for increasing the storage capacity.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view showing a structure of a memory cell array of a mask ROM according to one embodiment of the present invention.

FIG. 2 is a schematic block diagram illustrating an overall configuration of a mask ROM of the present embodiment.

FIG. 3 is a diagram showing a difference in electrical characteristics between a memory cell having a tunnel oxide film and a memory cell not having a tunnel oxide film in the mask ROM of the present embodiment.

FIG. 4 is a circuit diagram showing an example of a specific configuration of a high voltage application circuit in FIG. 2;

FIG. 5 shows the magnitude of a current flowing between two conductive layers via an oxide film interposed between the two conductive layers,
5 is a graph showing a relationship between an electric field expected in an oxide film by applying a voltage between two conductive layers.

FIG. 6 is a circuit showing a configuration amount of a sense amplifier in FIG. 2;

FIG. 7 is a cross-sectional view showing a part of the manufacturing process included in the first example of the manufacturing method of the mask ROM according to the embodiment.

FIG. 8 is a cross-sectional view showing another manufacturing step included in the first manufacturing method example.

FIG. 9 is a cross-sectional view showing still another manufacturing process included in the first manufacturing method example.

FIG. 10 is a cross-sectional view showing a part of the manufacturing process included in the second example of the manufacturing method of the mask ROM of the present embodiment.

FIG. 11 is a cross-sectional view showing another manufacturing step included in the second manufacturing method example.

FIG. 12 is a cross-sectional view showing still another manufacturing step included in the second manufacturing method example.

FIG. 13 is a cross-sectional view illustrating an example of a method for forming a tunnel oxide film in an example.

FIG. 14 is a sectional view and a plan view showing the structure of a memory cell array and each memory cell in a mask ROM according to another embodiment of the present invention.

FIG. 15 is a diagram for explaining the operation principle of the memory cell in the mask ROM of the example.

FIG. 16 shows a mask R using a PN junction as a memory cell.
It is the top view and sectional drawing which show the memory array structure of OM.

FIG. 17 shows a mask R using a PN junction as a memory cell.
It is sectional drawing which shows a part of manufacturing process contained in the manufacturing method of OM.

FIG. 18 shows a mask R using a PN junction as a memory cell.
It is sectional drawing which shows the other manufacturing process contained in the manufacturing method of OM.

FIG. 19 shows a mask R using a PN junction as a memory cell.
It is sectional drawing which shows the further another manufacturing process contained in the manufacturing method of OM.

FIG. 20 is a cross-sectional view showing a structure of each memory cell in a conventional multilevel memory using one MOS transistor as one memory cell.

21 is a diagram for explaining the operation principle of the memory cell having the structure shown in FIG.

FIG. 22 is a cross-sectional view showing a structure of each memory cell and a plan view showing a structure of a memory cell array in a conventional multi-valued memory using an inelastic tunnel effect.

FIG. 23 is a diagram for explaining the operation principle of each memory cell in a conventional multilevel memory using an inelastic tunnel effect.

[Explanation of symbols]

1,11,111 Semiconductor substrate 3,12 First conductive layer 6,13 Second conductive layer 14 Insulating film 15 Tunnel oxide film 5,5a, 5b, 100,100a, 100b, 100
c Memory cell 2 Isolation layer 4, 113, 119 Oxide film 112 N well 115 Polysilicon layer 116 Metal layer 117 N-type impurity diffusion layer forming source and drain of MOS transistor 118 P-type forming source and drain of MOS transistor Impurity diffusion layer 120 Contact hole 122 N-type impurity diffusion layer forming a bit line 123 Tunnel oxide film 121, 124 Conductive layer for wiring 200 Conductive layer of two-layer structure In the drawings, the same reference numerals indicate the same or corresponding parts.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-58-209155 (JP, A) JP-A-59-168664 (JP, A) JP-A-2-150063 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H01L 27/10 H01L 27/112 H01L 21/8246

Claims (4)

(57) [Claims] 1. A mask ROM in which predetermined data is stored in advance at the time of manufacture, comprising: a semiconductor substrate having a main surface; and a plurality of left and right spaces formed on the main surface of the semiconductor substrate. A first signal line; an insulating film formed on the plurality of first signal lines; and a left and right space on the insulating film so as to intersect each of the plurality of first signal lines at a plurality of intersections. A plurality of second signal lines formed in a gap, wherein the insulating film is formed of a plurality of predetermined thicknesses corresponding to the data at each of the portions corresponding to the plurality of intersections. At least one of the plurality of thicknesses of the insulating film is responsive to application of a high voltage between the corresponding first signal line and the corresponding second signal line. Between the first signal line and the corresponding second signal line. Mask ROM having a thickness within a range in which a tunnel current can flow. 2. A mask ROM for storing data, comprising: a semiconductor substrate having a main surface; a plurality of parallel first signal lines extending in a column direction on the main surface of the semiconductor substrate; An insulating film formed on the plurality of first signal lines; and a plurality of parallel second films extending in the row direction on the insulating film so as to intersect each of the plurality of first signal lines at a plurality of intersections. And two signal lines, wherein the insulating film has first and second thicknesses at the plurality of intersections according to the data, and among the plurality of intersections, the insulating film is the first A predetermined voltage that causes a first tunnel current to occur at an intersection having a thickness of, and the insulating film causes a second tunnel current to occur at an intersection having the second thickness. Responsive to the current of the first signal line or the second signal line applied to the insulating film Te, wherein the first and second tunneling current sensing, further comprising sensing means for generating a data output signal in response to said sensing, the mask ROM. 3. A mask ROM for storing data, comprising: a semiconductor substrate having a main surface; a plurality of parallel first signal lines extending in a column direction on the main surface of the semiconductor substrate; An insulating film formed on the plurality of first signal lines; and a plurality of parallel second films extending in the row direction on the insulating film so as to intersect each of the plurality of first signal lines at a plurality of intersections. And a second signal line, wherein the insulating film has first and second thicknesses at the plurality of intersections in accordance with the data, and a tunnel current of the first signal line or the second signal line. A mask ROM further comprising a tunnel current detecting means for detecting presence / absence and generating an output data signal. 4. A method of manufacturing a mask ROM in which predetermined data is stored in advance at the time of manufacturing, wherein a plurality of first ROMs are provided on a main surface of a semiconductor substrate at right and left intervals.
Forming a signal line; forming an insulating film on the plurality of first signal lines; forming a plurality of second signal lines on the insulating film;
Forming at intervals left and right so as to intersect with each of the signal lines at a plurality of intersections, wherein the step of forming the insulating film includes forming each portion of the insulating film corresponding to the plurality of intersections. , Corresponding to the data,
The method further includes the step of forming at least one of a plurality of predetermined thicknesses, wherein at least one of the plurality of thicknesses corresponds to the first signal line and the corresponding second signal line. A method for manufacturing a mask ROM, wherein the mask ROM is formed so as to have a thickness within a range in which a tunnel current can flow between the first signal line and the corresponding second signal line in response to application of a high voltage therebetween.