JP3314185B2 - Logic circuit with power control function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit composed of field effect transistors, and more particularly, to a power control transistor connected between a logic circuit group and a power supply so that an operation state and a standby state of the logic circuit group are changed. And a logic circuit having a power control function for reducing standby current by controlling conduction / interruption of a power control transistor.

[0002]

2. Description of the Related Art In recent years, low voltage operation of integrated circuits has been promoted in order to meet the demand for portable electronic devices. As an example of such a technology, the Institute of Electronics, Information and Communication Engineers, 1994
MTC-MOS (Multi-Thre) as shown in, for example, FIG.
hold CMOS) circuit.

In such an MTC-MOS circuit, each of the logic circuits LG of the logic circuit group LGA is constituted by a field effect transistor having a low threshold value (Vtl).
The power supply terminal of A is connected to the pseudo power supply line VDDV. A power control transistor Qs (threshold voltage Vts) having a high threshold voltage is connected between the pseudo power supply line VDDV and the first power supply line VDD, and a logic circuit SCG is connected to its gate SL. ing. In the example shown in FIG. 8, the transistor Qs is a P-channel field-effect transistor, the potential of the first power supply line VDD is V1, the potential of the second power supply line VSS is V2, and V2 is "0" potential. It is.

Here, the logic circuit SCG is a circuit for generating a signal for determining the potential of the gate terminal SL, that is, a signal for controlling the state of the transistor Qs, and is hereinafter referred to as a sleep control circuit. Also, in FIG. 8, V1 / V2 is described at the gate end SL of the transistor Qs, which means that the potential level of the gate end SL is determined to be the V1 level when the potential is high and the V2 level when the potential is low. are doing.
FIG. 9 shows a specific example of the sleep control circuit SCG, in which the output circuit of the sleep control circuit SCG is configured by an inverter INV. Here, the inverter INV
Is connected to the first power supply line VDD and the low potential side power supply end to the second power supply line VSS.
The level signals V1 and V2 are output to the gate terminal SL of the transistor Qs. Note that each field effect transistor forming the inverter INV is a transistor having a high threshold voltage.

Next, the MTC-MO constructed as described above
The operation of the S circuit will be described. Sleep control circuit SC
G sets the gate end SL of the transistor Qs to the V2 level when the logic circuit group LGA is active. As a result,
The transistor Qs conducts, the potential of the pseudo power supply line VDDV becomes the same level as the potential V1 of the power supply line VDD, and the logic circuit group LGA executes a logic operation. Generally, the speed performance of a CMOS circuit is proportional to the square of the voltage obtained by subtracting the threshold voltage of the transistor from the power supply voltage. Therefore, 1V
If the threshold voltage of the transistor is low even if the power supply voltage is lowered to such an extent, such a CMOS circuit such as the MTC-MO
The S circuit, that is, the logic circuit group LGA operates at high speed. Therefore, the logic circuit LG configuring the logic circuit group LGA has one
The threshold voltage is sufficiently reduced so that high-speed operation is possible even with an extremely low power supply voltage of V or less.

However, when the threshold voltage is lowered, there is a problem that the leakage prevention capability generally decreases and the standby current increases. For this reason, in the technology of the MTC-MOS circuit, such a problem is avoided by introducing a power control function called sleep control. That is, the logic circuit group LGA
In a standby state in which does not operate, the logic circuit group LGA is set to a sleep state. Specifically, the potential of the gate end SL of the transistor Qs is set to the V1 level to
s is turned off. When the threshold voltage of transistor Qs increases by 0.1 V, the leak voltage decreases by 1/1.
Since the threshold voltage can be reduced to 0, normally, the threshold voltage of the transistor Qs is set to be higher than the threshold voltage of each transistor constituting the logic circuit group LGA by 0.3 V or more.
As a result, the leakage current at the time of standby generated by the low threshold transistors of the logic circuit group LGA is almost completely cut, and the ultra-low power characteristic of the logic circuit group LGA at the time of standby is realized.

[0007]

The speed performance of such an MTC-MOS circuit, which is considered to be a promising low-voltage high-speed circuit technology, at the time of active, is determined by the pseudo power supply line VDD.
V, the sleep control transistor Q
s of the current supply capacity. Here, the gate-source voltage of the transistor Qs is Vgs, and the threshold voltage is Vs
ts, the current supply capability of the transistor Qs is | V
gs-Vts |.

In the prior art, the potential at the gate end SL at the time of activation when the transistor Qs is turned on is V2 (that is, "0" potential). Therefore, the transistor Qs
The value representing the current supply capability at the time of active is | Vgs−Vts | = | −V1−Vts |. As can be seen from this equation alone, even if V1 becomes smaller due to the lowering of the voltage, if | Vts | is set to be small at the same time, the current supply capability of the MTC-MOS circuit in the active state can be increased. However, the threshold voltage | Vts | cannot be reduced for the reason described later.

According to the prior art, the specific potential relationship for turning off the sleep control transistor Qs during standby of the MTC-MOS circuit will be described. The source potential is V1 and the gate potential is V1. The voltage Vgs is “0”. Here, the amount of off-leakage current that determines the amount of current consumed during standby of the MTC-MOS circuit is proportional to exp (− | Vts | / A) (A is a proportional constant), and therefore the threshold voltage | Vts Even if | is lowered by 0.1 V, the leak current increases by about one digit, and the threshold voltage | Vts | cannot be reduced.

As described above, the sleep control transistor Q
In order to suppress the leakage current at the time of standby of the MTC-MOS circuit, the transistor Qs
Needs to be sufficiently large. However, when the threshold voltage | Vts | is increased, M
When the TC-MOS circuit is active, sufficient current supply capability cannot be obtained to the pseudo power supply line VDDV. As a result, there is a problem that the MTC-MOS circuit cannot perform high-speed logic operation when active. . Therefore, an object of the present invention is to realize a high-speed operation when the MTC-MOS circuit is active and to reduce a standby current in a standby state.

[0011]

SUMMARY OF THE INVENTION In order to solve such a problem, the present invention provides a logic circuit group including field-effect transistors, and a high-level power supply terminal of the logic circuit group is connected to a first common terminal. Connected to the pseudo power supply line (VDDV),
Of the first power supply line (VD) having the first power supply level (V1) via the first field-effect transistor
D), and the low-level power supply terminals of the group of logic circuits are connected to a common second pseudo power supply line (VSSV),
In the logic circuit connecting the second pseudo power supply line to the second power supply line (VSS) having the second power supply level (V2) via the second field effect transistor, the gate of the first field effect transistor It applies a potential of the second power level and the same level or first larger third than the power supply level of the power supply level (V3) to terminal, to the gate terminal of the second field effect transistor the first power level The same level as or the fourth power supply level smaller than the second power supply level.
Of the power supply level (V4).

Further, a first connection means for connecting the first pseudo power supply line to the first power supply line without passing through the first field effect transistor, and a second connection means without passing through the second field effect transistor. One of the second connection means for connecting the pseudo power supply line to the second power supply line is provided. Further, the logic circuit group is constituted by field effect transistors having a low threshold voltage, and the first and second field effect transistors are constituted by field effect transistors having a high threshold voltage.
Further, the logic circuit group is constituted by a field effect transistor having a low threshold voltage, and the first or second field effect transistor is constituted by a field effect transistor having a high threshold voltage.

[0013]

The potential of the third power supply level, which is the same as the second power supply level or higher than the first power supply level, is applied to the gate of the first field effect transistor.
A potential at the same level as the first power supply level or at a fourth power supply level smaller than the second power supply level is applied to the gate terminal of the field effect transistor. As a result, when the logic circuit group is active, the first and second transistors can be provided with a gate potential that is more conductive than in the conventional case, and a pseudo power supply line that supplies current to the logic circuit group can be supplied to the first and second transistors. Therefore, the logic circuit group can operate at high speed even at a low voltage because a sufficient current supply capability can be provided. Further, at the time of standby of the logic circuit group, a stronger gate potential than in the conventional case can be applied to the first and second transistors.
Even if the threshold voltage of each transistor is low, the leakage current is suppressed, and thus the standby current of the logic circuit group can be reduced. Further, one of the first connection means and the second connection means is provided. As a result, the circuit can be constructed economically.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a logic circuit having a power control function according to the present invention, and shows a first embodiment of the second invention. In this figure, the circuit of this embodiment includes a first power supply line VDD, a logic circuit group LGA which is composed of logic circuits LG and realizes a desired logic operation, and a pseudo power supply line VDDV to which a power supply end of the logic circuit group LGA is connected. , A power control (sleep control) transistor Qx having a low threshold voltage inserted between the pseudo power supply line VDDV and the first power supply line VDD, a sleep control circuit SCG, and a second power supply line VSS. Further, each logic circuit LG is constituted by a field effect transistor having a low threshold voltage.

In this embodiment, the threshold voltage of the transistor Qx, which is a P-channel field-effect transistor, is Vtx, and the gate end thereof is SL. Also,
The potential of the first power supply line VDD is set to V1, the second power supply line VSS
Is V2, and V2 is a “0” potential. In addition, the sleep control circuit SCG is a circuit that controls the on / off state of the transistor Qx by determining the potential of the gate terminal SL of the transistor Qx. The sleep control circuit SCG has a level V3 higher than the potential V1 of the first power supply line VDD. Level and V
A two-level output potential is generated.

Next, the operation of the embodiment circuit configured as described above will be described. The sleep control circuit SCG puts the logic circuit group LGA into a sleep state when the logic circuit group LGA is on standby. That is, in this case, the transistor Q
The potential of the gate end SL of x is set to V3, and the transistor Qx is set to a strong cutoff state. Specifically, a transistor Qx which is a P-channel field-effect transistor
Is set to Vgs = V3−V1> 0, and a strong cutoff state is set.

Here, the off-leakage current that determines the standby current amount of the logic circuit group LGA is expressed as expｅｘ (− | Vg
s |-| Vtx |) / A｝ (A is a proportional constant). From this equation, the threshold voltage | Vt of the transistor Qx
It can be seen that even if x | is reduced, the leakage current can be suppressed to a sufficiently small value because the gate-source voltage Vgs of the transistor Qx is effective, and the standby current of the logic circuit group LGA can be cut off. Therefore, by configuring the transistor Qx with a low-threshold transistor, the leakage reduction performance equivalent to the MTC-MOS circuit, which conventionally required two-level transistors with high / low threshold voltage, is reduced. It can be realized only by transistors having a threshold voltage.

Next, when the logic circuit group LGA is active, the gate end SL of the transistor Qx is set to the V2 level ("0" potential). Then, the transistor Qx becomes conductive, the pseudo power supply line VDDV acts as the power supply line VDD, and the logic circuit group LGA executes a desired logic operation.
Here, | Vgs−Vtx | representing an index of current supply capability
│Vgs-Vtx│ = │-V1-Vtx│.

As described above, in this embodiment, the threshold voltage | Vtx of the transistor Qx is different from that of the prior art.
Even if | is not increased, the generation of leak voltage can be sufficiently suppressed, and the standby current of logic circuit group LGA can be reduced. Therefore, even when the power supply voltage V1 of the first power supply line VDD is reduced to allow the LSI operation of the logic circuit group LGA to be performed at a low voltage, the pseudo voltage can be reduced by reducing the threshold voltage | Vtx | of the transistor Qx. A sufficient current supply capability can be given to the power supply line VDDV. As a result, the logic circuit group LGA supplied with power from the pseudo power supply line VDDV can execute a logic operation at high speed even at a low voltage.

FIG. 2 is a block diagram showing a second embodiment of the second invention. In the first embodiment, the sleep control transistor Qx is a P-channel transistor and is inserted on the high potential power supply side. However, an N-channel transistor having a low threshold voltage as shown in FIG. It is also possible to use Qxn. That is, in this case, the power supply terminal on the high potential side of the logic circuit group LGA is connected to the first power supply line VD.
D, and the power supply terminal on the low potential side of the logic circuit group LGA is connected to the pseudo power supply line VSSV. The N-channel transistor Qxn (threshold voltage Vtxn) is connected between the pseudo power supply line VSSV and the second power supply line VSS. Here, the gate end of the transistor Qxn is SL
N, the potential of the gate end SLN is determined by the output of the sleep control circuit SCG. The sleep control circuit SC
G outputs V1 as a high-level output and V4 level lower than the potential V2 of the second power supply line VSS as a low-level output.

In the circuit of the second embodiment configured as described above, the sleep control circuit SCG puts the logic circuit group LGA into a sleep state when the logic circuit group LGA is on standby. That is, specifically, the potential of the gate end SLN of the transistor Qxn is set to V4. Then, the transistor Qx
The gate-source voltage Vgs of n becomes Vgs = − | V4 | <0, and the transistor Qxn is in a strong cutoff state. Therefore, even when the transistor Qxn is formed of a transistor having a low threshold voltage, generation of a leak current can be suppressed, and the standby current of the logic circuit group LGA can be almost completely cut off.

When the logic circuit group LGA is active, the gate end SLN of the transistor Qxn is set to the V1 level. Then, the transistor Qxn becomes conductive, the pseudo power supply line VSSV acts as the second power supply line VSS, and the logic circuit group LGA executes a desired logic operation. Here, considering | Vgs-Vtxn | representing an index of current supply capability, | Vgs-Vtxn | = | V1-Vtxn |

As described above, in this embodiment, the threshold voltage Vtx of the transistor Qxn is different from that of the prior art.
There is no need to increase n. Therefore, the first power supply line VD
Even if the power supply voltage V1 of D is lowered, sufficient current supply capability can be given to the pseudo power supply line VSSV by reducing the threshold voltage Vtxn of the transistor Qxn. As a result, similar to the first embodiment, the pseudo power supply line VSS
The logic circuit group LGA supplied with power from V can execute a logic operation at high speed even at a low voltage.

FIG. 3 is a block diagram showing a third embodiment of the second invention. In the third embodiment, the sleep control circuit SCG generates an output potential of V3 level higher than V1 and a V4 lower level of V2 lower than V2. Here, when the logic circuit group LGA is on standby, it operates in the same manner as in the first embodiment, and has the same effect. next,
When the logic circuit group LGA is active, the gate end SL of the transistor Qx having a low threshold voltage is set to the V4 level. Then, the transistor Qx is turned on, the pseudo power supply line VDDV behaves as the first power supply line VDD, and the logic circuit group LGA executes a desired logic operation. Here, considering | Vgs-Vtx |, which represents an index of the current supply capability, | Vgs-Vtx | = | V4-V1-Vtx |, which can be increased by | V4 | compared to the first embodiment. it can. Therefore, sufficient current supply capability can be given to the pseudo power supply line VDDV, and the logic circuit group LGA
Can be expected to operate even faster. The other detailed connections and operations are the same as in the first embodiment, and a description thereof will be omitted.

FIG. 4 is a block diagram showing an embodiment of the first invention. In this embodiment, the pseudo power supply lines VDD are provided on the high potential power supply side and the low potential power supply side of the logic circuit group LGA, respectively.
V and VSSV, a sleep control transistor Qx is connected between the first power supply line VDD and the pseudo power supply line VDDV, and the second power supply line VSS and the pseudo power supply line VS
This is an example in which a sleep control transistor Qxn is connected to an SV. Note that the transistors Qx and Qxn are transistors having a low threshold voltage.

Here, during standby of the logic circuit group LGA, the sleep control circuit SCG outputs a voltage such that the potential of the gate terminal SL of the transistor Qx becomes V3 and the potential of the gate terminal SLN of the transistor Qxn becomes V4.
When the logic circuit group LGA is active, the sleep control circuit SCG outputs a voltage such that the potential of the gate terminal SL of the transistor Qx becomes V2 and the potential of the gate terminal SLN of the transistor Qxn becomes V1. As described above, this embodiment of the first invention is a combination of the above-described first and second embodiments of the second invention. Therefore, the operation is the same as that of each of the above-described embodiments, and therefore the description thereof will be omitted. . In addition,
Like the circuit of the first embodiment of the present invention, in a circuit in which sleep control transistors are inserted on both the high-potential power supply side and the low-potential power supply side, similarly to the third embodiment of the second invention, a gate terminal of the transistor Qx is provided. If the low-potential output of SL is V4 and the high-potential output of the gate terminal SLN of the transistor Qxn is V3, the power supply capability of the logic circuit group LGA when it is active can be increased.

FIG. 5 is a block diagram showing an embodiment of the fourth invention. In the circuit of this embodiment, each logic circuit LG of the logic circuit group LGA which performs a desired logic operation is constituted by a field effect transistor having a low threshold voltage in the same manner as described above, and the power supply terminal of the logic circuit group LGA is connected. Pseudo power supply line VDDV
And a sleep control transistor Qxh (threshold voltage Vtxh) inserted between the power supply line VDD and the first power supply line VDD. Here, a sleep control circuit SCG for controlling the transistor Qxh
Outputs a V1 level as a high potential level and a V4 level output voltage lower than the V2 level as a low potential level.

In the embodiment circuit thus configured, when the logic circuit group LGA is active, the sleep control circuit S
CG sets the potential of the gate end SL of the transistor Qxh to V
4 (V4 <0). Then, the transistor Qxh conducts, so that the pseudo power supply line VDDV becomes the first power supply line VD
Acting as D, the logic circuit group LGA performs a desired logic operation. Here, | Vg representing an index of current supply capability
Considering s-Vtxh |, | Vgs-Vtxh | = | V4-V1-Vtxh | Therefore, by increasing | V4 | even if the voltage V1 of the first power supply line VDD is reduced, the pseudo power supply line VD
A logic circuit group LGA that can provide a sufficient current supply capability to the DV and is supplied with current from the pseudo power supply line VDDV.
Thus, high-speed logic operation can be performed even at a low voltage.

On the other hand, when the logic circuit group LGA is on standby, the sleep control circuit SCG puts the logic circuit group LGA into a sleep state. That is, specifically, the transistor Q
The potential at the gate end SL of xh is set to V1. Then, the gate-source voltage Vgs of the transistor Qxh becomes Vgs = 0. Here, the threshold voltage Vt of the transistor Qxh
Since xh is sufficiently larger than the threshold voltage of each transistor constituting the logic circuit group LGA, the standby current of the logic circuit group LGA can be almost completely reduced.

In the circuit of the fourth embodiment, the sleep control transistor Qxh is a P-channel type field effect transistor, but the same applies to an N-channel type field effect transistor. In addition, this fourth invention
The present invention can be similarly applied to the above-described embodiment circuit of the first invention using both a P-channel field-effect transistor and an N-channel transistor as the sleep control transistor. FIG. 6 is a circuit diagram of an embodiment showing the third invention,
This is an example in which the above-described fourth invention is applied to the circuit of the first invention. Note that the transistors Qx, Qx
n is, of course, a transistor having a high threshold voltage. The operation of the circuit of this embodiment is the same as the operation of the circuit of the first invention, and the description thereof will be omitted.

As described above, in a logic circuit in which the power supply terminal of the logic circuit group LGA capable of operating at low voltage and high speed is connected to the power supply via the sleep control transistor,
A logic circuit group LG is connected to the gate end of the sleep control transistor.
A potential different from the power supply potential applied to A is applied. As a result, when the logic circuit group LGA is active, it is possible to apply a gate potential that becomes a conductive state stronger than before to the sleep control transistor. Thus, sufficient current supply capability can be provided, and the logic circuit group LGA can execute a higher-speed logic operation even during low-voltage operation. Further, at the time of standby of the logic circuit group LGA, a gate potential that is in a stronger cutoff state can be applied to the sleep control transistor than before, so that even if the threshold voltage of the sleep control transistor is low, the leakage current is small. And therefore the logic circuit group LGA
Can be sufficiently reduced.

In a conventional logic circuit, a logic circuit group L
The limit of lowering the power supply voltage supplied to the GA has been determined by the threshold voltage of the sleep control transistor. This is because the gate potential of the sleep control transistor is controlled by the power supply potential supplied to the logic circuit group LGA. Therefore, if the power supply voltage is lower than the threshold voltage of the sleep control transistor, the sleep control transistor does not conduct and becomes pseudo. Current cannot be supplied to the power supply line. For this reason, in the present embodiment, by applying a potential different from the power supply potential applied to the logic circuit group LGA to the gate end of the sleep control transistor, the limit of lowering the power supply voltage supplied to the logic circuit group LGA is limited by the sleep control. It can be lower than the threshold voltage of the transistor. As a result, the power consumed by the logic circuit group LGA can be further reduced.

Next, FIG. 7 is a diagram for supplementing each embodiment of each invention shown so far, and includes a sleep control circuit SC.
3 shows a main part of G. As shown in the figure, the output terminal a of the sleep control circuit SCG is connected to the gate terminal SL of the sleep control transistor Qx having a low threshold voltage. The output circuit of the sleep control circuit SCG includes an inverter INV1, and the power supply terminal on the high potential side of the inverter INV1 has a third power supply line VD having a voltage level V3.
D1. The power supply terminal on the low potential side of the inverter INV1 is connected to a fourth power supply line VSS1 having a voltage level V4. Note that the inverter INV1
Are field effect transistors having a high threshold voltage.

Here, the potential level V3 of the third power supply line VDD1 is higher than the potential V1 of the first power supply line VDD, and the potential level V4 of the fourth power supply line VSS1 is higher than the potential level V2 of the second power supply line VSS. Low. By configuring the sleep control circuit SCG in this manner, signals of respective levels V3 and V4 different from the potentials V1 and V2 can be supplied to the gate terminal SL of the sleep control transistor Qx. Of course, each power supply terminal of the inverter INV1 is connected to the first and second power supply lines VDD and VSS, and V1 / V1 is connected to the gate terminal SL.
It is also possible to apply a signal potential of a combination of V4 or a combination of V3 / V2. Further, in this embodiment, although there is no particular description about how to apply V3 and V4 different from the potentials V1 and V2, various methods are conceivable, and as an example, a power supply independent from the outside is provided. Although there is a method of applying the voltage or a method of generating the voltage by various boosting / lowering circuits, it is possible to apply a generally used technique.

[0035]

As described above, according to the present invention, the first power supply line having the first power supply level is connected to the first pseudo power supply line connected to the high potential power supply section of the logic circuit group. for the first gate of the field effect transistor, the second
And a third power supply level potential higher than the first power supply level and connected to the second power supply line having the second power supply level and the low potential power supply section of the logic circuit group. A potential of the fourth power supply level, which is the same as the first power supply level or lower than the second power supply level, is applied to the gate terminal of the second field-effect transistor connecting to the second pseudo power supply line. Therefore, when the logic circuit group is active, the first and second transistors can be provided with a gate potential that is in a stronger conduction state than in the prior art, and the pseudo power supply line that supplies current to the logic circuit group can be supplied to the first and second transistors. Since a sufficient current supply capacity can be given to the logic circuit group, the logic circuit group can operate at high speed even at a low voltage. Further, at the time of standby of the logic circuit group, a gate potential which becomes a stronger cutoff state can be applied to the first and second transistors as compared with the conventional case. And the standby current of the logic circuit group can be reduced. Thereby, there is an effect that the power consumed in the logic circuit portion can be suppressed low.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a second invention of a logic circuit having a power control function according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the second invention.

FIG. 3 is a block diagram showing a third embodiment of the second invention.

FIG. 4 is a block diagram showing an embodiment of the first invention.

FIG. 5 is a block diagram showing an embodiment of the fourth invention.

FIG. 6 is a block diagram showing an embodiment of the third invention.

FIG. 7 is a diagram illustrating a configuration of a sleep control circuit provided in each example circuit.

FIG. 8 is a block diagram showing a configuration of a conventional circuit.

FIG. 9 is a diagram showing a specific example of a sleep control circuit constituting a conventional circuit.

[Explanation of symbols]

LGA: logic circuit group, SCG: sleep control circuit, Qx
... P-channel sleep control transistor (field effect transistor), Qxn N-channel sleep control transistor (field effect transistor), SL, SLN gate terminals, INV1 inverter, V1 to V4.

Claims (4)

(57) [Claims] A logic circuit group is constituted by field-effect transistors, and a high-level power supply terminal of the logic circuit group is connected to a common first pseudo power supply line. A first power supply line having a first power supply level is connected via one field-effect transistor, and a low-level power supply terminal of the logic circuit group is connected to a common second pseudo power supply line. in the logic circuit connecting the second power supply line having a second power level via a second field effect transistor to the second virtual power supply line, to the first gate terminal of the field effect transistor a second power level the same level or applies a first power level a large third power supply level potential than the first power level and the same level to the gate terminal of the second field effect transistor or the second power level and A logic circuit having a power control function and applying a smaller fourth power level of the potential of. 2. The logic circuit having a power control function according to claim 1, wherein: a first connection means for connecting the first pseudo power supply line to the first power supply line without passing through the first field effect transistor; And the second
Logic having a power control function, characterized by having one of the second connection means for connecting the second pseudo power supply line to the second power supply line without passing through the field effect transistor. circuit. 3. The logic circuit having a power control function according to claim 1, wherein said logic circuit group is formed of a field effect transistor having a low threshold voltage, and said first and second field effect transistors are formed. A logic circuit having a power control function, comprising a field-effect transistor having a high threshold voltage. 4. The logic circuit having a power control function according to claim 2, wherein said logic circuit group is formed of a field effect transistor having a low threshold voltage, and said first or second field effect transistor is a threshold. A logic circuit having a power control function, comprising a field-effect transistor having a high value voltage.