WO2004025731A3 - Verfahren zur herstellung von sonos-speicherzellen, sonos-speicherzelle und speicherzellenfeld - Google Patents

Verfahren zur herstellung von sonos-speicherzellen, sonos-speicherzelle und speicherzellenfeld Download PDF

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Publication number
WO2004025731A3
WO2004025731A3 PCT/DE2003/002576 DE0302576W WO2004025731A3 WO 2004025731 A3 WO2004025731 A3 WO 2004025731A3 DE 0302576 W DE0302576 W DE 0302576W WO 2004025731 A3 WO2004025731 A3 WO 2004025731A3
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WO
WIPO (PCT)
Prior art keywords
memory cell
ditch
sonos
created
production
Prior art date
Application number
PCT/DE2003/002576
Other languages
English (en)
French (fr)
Other versions
WO2004025731A2 (de
Inventor
Joachim Deppe
Christoph Ludwig
Christoph Kleint
Josef Willer
Original Assignee
Infineon Technologies Ag
Infineon Technologies Flash Gm
Joachim Deppe
Christoph Ludwig
Christoph Kleint
Josef Willer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Infineon Technologies Flash Gm, Joachim Deppe, Christoph Ludwig, Christoph Kleint, Josef Willer filed Critical Infineon Technologies Ag
Priority to EP03794774A priority Critical patent/EP1535338A2/de
Publication of WO2004025731A2 publication Critical patent/WO2004025731A2/de
Publication of WO2004025731A3 publication Critical patent/WO2004025731A3/de
Priority to US11/072,695 priority patent/US7323388B2/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

In einem Si-Körper (1) wird ein Graben (2) hergestellt, dessen Wände (4) mit einer Stickstoffimplantierung (6) versehen werden. Eine Oxidschicht zwischen den Source-/Drain-Bereichen (5) und einer auf der Oberseite aufgebrachten Wortleitung wächst dicker auf als eine untere Oxidschicht einer als Gate-Dielektrikum an der Grabenwand hergestellte ONO-Speicherschicht. Statt der Stickstoffimplantierung in die Grabenwände kann eine Metallsilizidschicht auf den Oberseiten der Source-/Drain-Bereiche hergestellt werden, um das Oxidwachstum dort zu beschleunigen.
PCT/DE2003/002576 2002-09-04 2003-07-31 Verfahren zur herstellung von sonos-speicherzellen, sonos-speicherzelle und speicherzellenfeld WO2004025731A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP03794774A EP1535338A2 (de) 2002-09-04 2003-07-31 Verfahren zur herstellung von sonos-speicherzellen, sonos-speicherzelle und speicherzellenfeld
US11/072,695 US7323388B2 (en) 2002-09-04 2005-03-04 SONOS memory cells and arrays and method of forming the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10240893A DE10240893A1 (de) 2002-09-04 2002-09-04 Verfahren zur Herstellung von SONOS-Speicherzellen, SONOS-Speicherzelle und Speicherzellenfeld
DE10240893.9 2002-09-04

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/072,695 Continuation US7323388B2 (en) 2002-09-04 2005-03-04 SONOS memory cells and arrays and method of forming the same

Publications (2)

Publication Number Publication Date
WO2004025731A2 WO2004025731A2 (de) 2004-03-25
WO2004025731A3 true WO2004025731A3 (de) 2004-08-19

Family

ID=31724341

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/002576 WO2004025731A2 (de) 2002-09-04 2003-07-31 Verfahren zur herstellung von sonos-speicherzellen, sonos-speicherzelle und speicherzellenfeld

Country Status (5)

Country Link
US (1) US7323388B2 (de)
EP (1) EP1535338A2 (de)
DE (1) DE10240893A1 (de)
TW (1) TWI234240B (de)
WO (1) WO2004025731A2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11854890B2 (en) 2014-11-24 2023-12-26 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Capacitor and method for producing the same

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487523B1 (ko) * 2002-04-15 2005-05-03 삼성전자주식회사 부유트랩형 비휘발성 메모리 소자 및 그 제조방법
DE10226964A1 (de) * 2002-06-17 2004-01-08 Infineon Technologies Ag Verfahren zur Herstellung einer NROM-Speicherzellenanordnung
DE10260185B4 (de) * 2002-12-20 2007-04-12 Infineon Technologies Ag Halbleiterspeicher mit vertikalen Charge-trapping-Speicherzellen und Verfahren zu seiner Herstellung
US7452763B1 (en) * 2003-03-04 2008-11-18 Qspeed Semiconductor Inc. Method for a junction field effect transistor with reduced gate capacitance
DE10324550B4 (de) 2003-05-30 2006-10-19 Infineon Technologies Ag Herstellungsverfahren für eine NROM-Halbleiterspeichervorrichtung
US7759726B2 (en) * 2005-07-12 2010-07-20 Macronix International Co., Ltd. Non-volatile memory device, non-volatile memory cell thereof and method of fabricating the same
US8138540B2 (en) * 2005-10-24 2012-03-20 Macronix International Co., Ltd. Trench type non-volatile memory having three storage locations in one memory cell
JP2009004510A (ja) * 2007-06-20 2009-01-08 Toshiba Corp 不揮発性半導体記憶装置
US8487373B2 (en) 2009-04-29 2013-07-16 Spanion Llc SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same
US8691622B2 (en) * 2012-05-25 2014-04-08 Micron Technology, Inc. Memory cells and methods of forming memory cells
US10643852B2 (en) * 2016-09-30 2020-05-05 Semiconductor Components Industries, Llc Process of forming an electronic device including exposing a substrate to an oxidizing ambient
CN117995883A (zh) * 2022-10-28 2024-05-07 长鑫存储技术有限公司 半导体结构及其制备方法

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US5168334A (en) * 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
US5595927A (en) * 1995-03-17 1997-01-21 Taiwan Semiconductor Manufacturing Company Ltd. Method for making self-aligned source/drain mask ROM memory cell using trench etched channel
EP0783181A1 (de) * 1996-01-08 1997-07-09 Siemens Aktiengesellschaft Elektrisch programmierbare Speicherzellenanordnung und Verfahren zu deren Herstellung
US5943267A (en) * 1996-05-16 1999-08-24 Altera Corporation High-density nonvolatile memory cell
US6239465B1 (en) * 1999-01-27 2001-05-29 Fujitsu, Ltd. Non-volatile semiconductor memory device having vertical transistors with the floating and control gates in a trench and fabrication method therefor
US20020009855A1 (en) * 1999-04-07 2002-01-24 Hyeon-Seag Kim Gate insulator process for nanometer mosfets

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US5168334A (en) * 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
US5595927A (en) * 1995-03-17 1997-01-21 Taiwan Semiconductor Manufacturing Company Ltd. Method for making self-aligned source/drain mask ROM memory cell using trench etched channel
EP0783181A1 (de) * 1996-01-08 1997-07-09 Siemens Aktiengesellschaft Elektrisch programmierbare Speicherzellenanordnung und Verfahren zu deren Herstellung
US5943267A (en) * 1996-05-16 1999-08-24 Altera Corporation High-density nonvolatile memory cell
US6239465B1 (en) * 1999-01-27 2001-05-29 Fujitsu, Ltd. Non-volatile semiconductor memory device having vertical transistors with the floating and control gates in a trench and fabrication method therefor
US20020009855A1 (en) * 1999-04-07 2002-01-24 Hyeon-Seag Kim Gate insulator process for nanometer mosfets

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11854890B2 (en) 2014-11-24 2023-12-26 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Capacitor and method for producing the same

Also Published As

Publication number Publication date
DE10240893A1 (de) 2004-03-18
US20050196923A1 (en) 2005-09-08
TWI234240B (en) 2005-06-11
EP1535338A2 (de) 2005-06-01
TW200408067A (en) 2004-05-16
WO2004025731A2 (de) 2004-03-25
US7323388B2 (en) 2008-01-29

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