WO2004025725A3 - Verfahren zur herstellung eines speicherzellenfeldes mit in gräben angeordneten speichertransistoren - Google Patents

Verfahren zur herstellung eines speicherzellenfeldes mit in gräben angeordneten speichertransistoren Download PDF

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Publication number
WO2004025725A3
WO2004025725A3 PCT/DE2003/002574 DE0302574W WO2004025725A3 WO 2004025725 A3 WO2004025725 A3 WO 2004025725A3 DE 0302574 W DE0302574 W DE 0302574W WO 2004025725 A3 WO2004025725 A3 WO 2004025725A3
Authority
WO
WIPO (PCT)
Prior art keywords
openings
trenches
producing
memory
cell field
Prior art date
Application number
PCT/DE2003/002574
Other languages
English (en)
French (fr)
Other versions
WO2004025725A2 (de
Inventor
Joachim Deppe
Christoph Kleint
Christoph Ludwig
Original Assignee
Infineon Technologies Ag
Joachim Deppe
Christoph Kleint
Christoph Ludwig
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Joachim Deppe, Christoph Kleint, Christoph Ludwig filed Critical Infineon Technologies Ag
Publication of WO2004025725A2 publication Critical patent/WO2004025725A2/de
Publication of WO2004025725A3 publication Critical patent/WO2004025725A3/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Es wird eine Hartmaske (4) aufgebracht, die mit Öffnungen in den Bereichen der für die Speichertransistoren vorgesehenen Gräben und vorgesehener Isolationsgräben (8) versehen wird, in der Anordnung der Öffnungen aufeinanderfolgend jede zweite Öffnung mit Anteilen (62) einer Lackschicht verschlossen wird, durch die nicht verschlossenen Öffnungen hindurch das darunter vorhandene Material bis in eine vorgesehene Tiefe entfernt wird, die verschlossenen Öffnungen geöffnet werden und durch alle Öffnungen hindurch bis in das Halbleitermaterial hinein geätzt wird, so dass abwechselnd Gräben unterschiedlicher Tiefen gebildet werden.
PCT/DE2003/002574 2002-09-04 2003-07-31 Verfahren zur herstellung eines speicherzellenfeldes mit in gräben angeordneten speichertransistoren WO2004025725A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10240916A DE10240916A1 (de) 2002-09-04 2002-09-04 Verfahren zur Herstellung eines Speicherzellenfeldes mit in Gräben angeordneten Speichertransistoren
DE10240916.1 2002-09-04

Publications (2)

Publication Number Publication Date
WO2004025725A2 WO2004025725A2 (de) 2004-03-25
WO2004025725A3 true WO2004025725A3 (de) 2004-08-12

Family

ID=31895653

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/002574 WO2004025725A2 (de) 2002-09-04 2003-07-31 Verfahren zur herstellung eines speicherzellenfeldes mit in gräben angeordneten speichertransistoren

Country Status (3)

Country Link
DE (1) DE10240916A1 (de)
TW (1) TWI258206B (de)
WO (1) WO2004025725A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110349906B (zh) * 2018-04-03 2021-11-09 长鑫存储技术有限公司 一种自对准沟槽的形成方法
KR102634441B1 (ko) * 2018-10-25 2024-02-06 에스케이하이닉스 주식회사 반도체 장치의 제조방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6092632A (ja) * 1983-10-26 1985-05-24 Fujitsu Ltd 半導体装置の製造方法
DE4437581A1 (de) * 1994-10-20 1996-05-02 Siemens Ag Verfahren zur Herstellung einer Festwertspeicherzellenanordnung mit vertikalen MOS-Transistoren
DE19514834C1 (de) * 1995-04-21 1997-01-09 Siemens Ag Festwertspeicherzellenanordnung und Verfahren zu deren Herstellung
US5814547A (en) * 1997-10-06 1998-09-29 Industrial Technology Research Institute Forming different depth trenches simultaneously by microloading effect
US6239465B1 (en) * 1999-01-27 2001-05-29 Fujitsu, Ltd. Non-volatile semiconductor memory device having vertical transistors with the floating and control gates in a trench and fabrication method therefor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6215148B1 (en) * 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
JP2000260887A (ja) * 1999-03-08 2000-09-22 Nec Corp 不揮発性半導体記憶装置およびその製造方法
JP2000357754A (ja) * 1999-06-03 2000-12-26 Texas Instr Inc <Ti> Ｓｔｉを有するフラッシュメモリ内にソースラインをサリサイド化する方法
US20020055228A1 (en) * 2000-09-21 2002-05-09 Ambrose Thomas M. Sidewall process to improve the flash memory cell performance

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6092632A (ja) * 1983-10-26 1985-05-24 Fujitsu Ltd 半導体装置の製造方法
DE4437581A1 (de) * 1994-10-20 1996-05-02 Siemens Ag Verfahren zur Herstellung einer Festwertspeicherzellenanordnung mit vertikalen MOS-Transistoren
DE19514834C1 (de) * 1995-04-21 1997-01-09 Siemens Ag Festwertspeicherzellenanordnung und Verfahren zu deren Herstellung
US5814547A (en) * 1997-10-06 1998-09-29 Industrial Technology Research Institute Forming different depth trenches simultaneously by microloading effect
US6239465B1 (en) * 1999-01-27 2001-05-29 Fujitsu, Ltd. Non-volatile semiconductor memory device having vertical transistors with the floating and control gates in a trench and fabrication method therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 0092, no. 40 (E - 345) 26 September 1985 (1985-09-26) *

Also Published As

Publication number Publication date
DE10240916A1 (de) 2004-03-25
TWI258206B (en) 2006-07-11
TW200408075A (en) 2004-05-16
WO2004025725A2 (de) 2004-03-25

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