WO2004008620A1 - Three-phase current control device - Google Patents

Three-phase current control device Download PDF

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Publication number
WO2004008620A1
WO2004008620A1 PCT/JP2003/008622 JP0308622W WO2004008620A1 WO 2004008620 A1 WO2004008620 A1 WO 2004008620A1 JP 0308622 W JP0308622 W JP 0308622W WO 2004008620 A1 WO2004008620 A1 WO 2004008620A1
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Prior art keywords
phase
arm transistor
current
shunt resistor
transistor
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PCT/JP2003/008622
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French (fr)
Japanese (ja)
Inventor
Akihiro Hitsunoue
Yasuhiro Maruyama
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Kabushiki Kaisha Yaskawa Denki
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Publication of WO2004008620A1 publication Critical patent/WO2004008620A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter

Definitions

  • the present invention relates to current detection of a current control device of a three-phase motor drive device.
  • S 1 S 6 is a semiconductor switch element such as a power MOSFET and an IGBT, forming a three-phase bridge.
  • R1 R2 is a shunt resistor, which detects the U-phase and V-phase output currents by the voltage drop across the shunt resistor.
  • R3 and R10 are voltage dividing resistors. Since the potential at both ends of R 1 R 2 rises to the main circuit voltage between the high voltage P N, the voltage is divided to a voltage that can be input to the subsequent differential amplifier.
  • Al A 2 is a differential amplifier.
  • a voltage proportional to the U-phase current i U and the V-phase current i V is output by amplifying the potential difference between both ends of the divided R l R 2.
  • A3 and A4 are error amplifiers. A3 amplifies and outputs the error between the U-phase current command value and the detected U-phase current value, and A4 amplifies and outputs the error between the V-phase current command value and the detected V-phase current value .
  • B1 is a PWM modulation circuit. It receives the output of the U-phase and V-phase error amplifiers and generates a drive signal for the main circuit switch that is pulse width modulated to eliminate the error.
  • B2 is a gate drive circuit.
  • the drive signal generated by the PWM modulation circuit is amplified and level-shifted to drive the gates (G1 G6) of each switch in the main circuit.
  • the switch S 1 S 6, which is on / off controlled by the G 1 G6 gate drive signal, drives the output terminal potential appropriately to the positive P potential or the N base potential, thereby allowing the U-phase current command and V-phase current A load current i U U V corresponding to the current command is generated.
  • the shunt resistor R 1 R 2 that detects the load current is connected in series between the output terminal of each phase arm and the load, so the potential across the shunt resistor turns on and off the switch.
  • the resistance of the shunt resistor is set as small as possible to minimize heat generation and power loss. Usually, several ⁇ to several tens ⁇ are common. Therefore, the potential difference appearing at both ends of the shunt resistor is very small.
  • FIG. 4 shows the potential at both ends in the presence of the shunt resistor R1.
  • e 1 is the potential on the U-phase arm side of R 1 and is indicated by a solid line.
  • e 2 is the load-side potential of R 1 and is indicated by the broken line.
  • Vd is the potential difference between e1 and e2, and corresponds to the voltage drop caused by the load current.
  • the potential waveform of ele 2 is a rectangular waveform having a large amplitude and a small voltage drop due to the load current superimposed thereon.
  • main circuit voltage Assuming that a load current of 1 A is detected with a resistance value of 1 at 200 $ and a resistance value of 1 ⁇ ⁇ , the voltage drop is 1 OmV, which is only 0.000 V for a voltage swing of 200 V due to switching. 5%.
  • e 1 and e 2 are appropriately divided by a voltage dividing resistor to become e 1 ′ and e 2 ′, respectively, but this ratio does not change. If the potential difference between e 1 ′ and e 2 ′ can be accurately amplified by the differential amplifier A 1, the load current i U can be detected, but this poses a problem.
  • the switching frequency is considered to be a practical limit from several kHz to several tens kHz. It is difficult in the prior art to obtain a high switching frequency and a high-precision current control characteristic in order to reduce the ripple component of the output current or to achieve a high-speed response.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to achieve both a high switching frequency and a high-precision current detection without affecting the switching frequency. .
  • the present invention relates to a three-phase current control device including a main circuit based on a three-phase bridge, a load current detection unit, and a current control unit, wherein the load current detection unit includes: And a shunt resistor R2 provided between the negative terminal N and the lower arm transistor S2 in the same phase as the upper arm transistor S1.
  • a shunt resistor R 3 provided between the upper arm transistor S 3 and the positive terminal P in a different phase from the transistors S 1 and S 2; and a lower resistor in the same phase as the upper arm transistor S 3.
  • a means for calculating a load current based on a current value measured by the shunt resistor R 1 -R 4 provided between the transistor S 4 and the negative terminal N. is there.
  • the upper arm transistor and the lower arm transistor are IGBT.
  • the upper arm transistor and the lower arm transistor are each a power MOS FET.
  • FIG. 1 is a circuit diagram showing an embodiment of the present invention.
  • FIG. 2 is a terminal potential waveform diagram of the current detection shunt resistor according to the embodiment of the present invention.
  • FIG. 3 is a circuit diagram showing a conventional three-phase current control device.
  • FIG. 4 is a terminal potential waveform diagram of a current detection shunt resistor of a conventional three-phase current controller. [Best Mode for Carrying Out the Invention]
  • M is a motor serving as a load for the three-phase current controller
  • P and N are terminals for supplying DC voltage to the main circuit of the three-phase current controller
  • P is the positive side and N is the negative side.
  • the three-phase current controller supplies a variable voltage of a variable frequency to a motor as a load by pulse width modulating the DC voltage.
  • the main circuit consists of two semiconductor elements for each phase of U, V, and W.
  • the upper-arm switching transistor provided between the positive terminal P of the U-phase DC voltage and the output terminal Tu of the U-phase main circuit is S1
  • the upper-arm switching transistor is connected between the terminal Tu and the negative terminal N.
  • the lower-arm switch transistor provided therebetween is designated as S2.
  • the V-phase upper-arm switching transistor and the lower-arm switching transistor are S3 and S4, respectively.
  • the upper-arm switching transistor and the lower-arm switching transistor of the W phase are S5 and S6, respectively.
  • the output terminals of the main circuit section of the V and W phases are Tv and Tw, respectively.
  • the shunt resistor R1 provided in the U phase is provided between the positive terminal P and the upper arm transistor S1, and the shunt resistor R2 is provided between the negative terminal N and the lower arm transistor S2.
  • the shunt resistor R 3 provided for the V phase is connected between the positive terminal P and the upper arm transistor S 3
  • the shunt resistor R 4 is connected to the negative terminal N and the lower transistor. Composed between S4.
  • the semiconductor switches S1 to S6 power MOSFETs, IGBTs, and the like are generally used to form a three-phase bridge.
  • the shunt resistors R1 to R4 detect the current flowing to that node based on the potential difference between both ends.
  • R5 to R12 are voltage dividing resistors. Since the potentials at both ends of Rl and R3 rise to the high-voltage main circuit voltage between P and N, the voltage is divided to a voltage that can be input to the subsequent differential amplifier.
  • V-phase load current i V can be obtained from the potential difference between both ends of R 3 and R 4.
  • A1 to A4 are differential amplifiers. The current values of i1 to i4 are detected from the potential difference between both ends of the shunt resistors R1 to R4.
  • the gain ratios of the gains of the differential amplifiers 81 to 84 and the voltage dividing resistors of the scale 5 to! 12 are appropriately set so that the gains for the current values of i1 to i4 are equal.
  • A5 and A6 are differential amplifiers that perform the operations shown in equations (1) and (2), respectively, and compare them with iU and iV. Output the example voltage.
  • A7 and A8 are error amplifiers that amplify and output deviations between the U-phase current command value and the V-phase current command value and the current detection value of the corresponding phase.
  • B1 is a PWM modulation circuit. Receives the output of the U-phase and V-phase error amplifiers and generates a pulse width modulated drive signal for the main circuit switch that eliminates the error.
  • B 2 is a gate drive circuit. The drive signal generated by the PWM modulator is amplified and level-shifted to drive the gates (G1 to G6) of each switch in the main circuit.
  • the switches S 1 to S 6, which are on / off controlled by the gate drive signals of G 1 to G 6, drive the potential of the output terminal appropriately to the positive potential of P or the base potential of N, so that the U-phase current And load currents iU and iV corresponding to the V-phase current command. Since the W-phase load current i W always has the relationship of i W — (i U + i V), controlling i U and i V allows i W to be uniquely controlled simultaneously.
  • Fig. 2 shows the potentials at both ends of R1 and R2 for detecting the U-phase load current.
  • the potential e 1 of the terminal connected to the P side of the main circuit power supply of R 1 is always in a constant high potential state. Since the potential e 2 of the other terminal of FIG. 4 changes with respect to e 1 by the voltage drop V d 1 due to the current i 1 flowing through R 1, only a very small potential fluctuation occurs.
  • the potential e 4 of the terminal connected to the N side of the main circuit power supply of R 2 is always at a constant base potential. Since the potential e 3 at the other terminal of R 2 changes with respect to e 4 by the voltage drop V d 2 due to the current i 2 flowing through R 2, the potential fluctuates slightly as well. Does not occur.
  • the present invention relates to a three-phase current control device including a main circuit based on a three-phase bridge, a load current detection unit, and a current control unit.
  • a shunt resistor R 1 provided therebetween, a shunt resistor R 2 provided between the negative terminal N and the lower arm transistor S 2 which is in phase with the upper arm transistor S 1, and the transistor S 1,
  • a shunt resistor R 3 provided between the upper arm transistor S 3 and the positive terminal P different from S 2, a lower arm transistor S 4 and a negative terminal N which are in phase with the upper arm transistor S 3.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

A high switching frequency and a highly-accurate current detection can be realized without affection of the switching frequency to the current detection accuracy. In a three-phase current control device, load current detection means includes a shunt resistor (R1) arranged between a positive side terminal (P) and an upper arm transistor (S1), a shunt resistor (R2) arranged between a negative side terminal (N) and a lower arm transistor (S2), a shunt resistor (R3) arranged between an upper arm transistor (S3) having a different phase from the transistors (S1, S2) and the positive side terminal (P), a shunt resistor (R4) arranged between a lower arm transistor (S4) and the negative side terminal (N), and means for calculating a load current according to the current value measured by the shunt resistors (R1 to R4).

Description

明 細書  Specification
三相電流制御装置 .  Three-phase current controller.
[技術分野]  [Technical field]
本発明は三相モ一夕の駆動装置の電流制御装置の電流検出に関する。  The present invention relates to current detection of a current control device of a three-phase motor drive device.
[背景技術]  [Background technology]
従来、 三相電流制御装置は図 3に示すようになつている。 図において、 S 1 S 6 はパワー M〇S FETや I GBTといった半導体スィッチ素子であり、三相ブリッジ を構成している。 Rl R 2はシャント抵抗であり、 それぞれ U相、 V相の出力電流 をシャント抵抗両端の電圧降下によって検出する。 R3 R10は分圧抵抗である。 R l R 2の両端の電位は高電圧の P N間の主回路電圧まで上昇するので、 後段の 差動増幅器に入力可能な電圧まで分圧する。 Al A 2は差動増幅器である。 それぞ れ分圧された R l R 2の両端の電位差を増幅することにより、 U相電流 i Uと V相 電流 i Vに比例した電圧を出力する。 A3 A4は誤差増幅器である。 A3は U相電 流指令値と検出された U相電流値との誤差を増幅して出力し、 A4は V相電流指令値 と検出された V相電流値との誤差を増幅して出力する。  Conventionally, a three-phase current control device is configured as shown in FIG. In the figure, S 1 S 6 is a semiconductor switch element such as a power MOSFET and an IGBT, forming a three-phase bridge. R1 R2 is a shunt resistor, which detects the U-phase and V-phase output currents by the voltage drop across the shunt resistor. R3 and R10 are voltage dividing resistors. Since the potential at both ends of R 1 R 2 rises to the main circuit voltage between the high voltage P N, the voltage is divided to a voltage that can be input to the subsequent differential amplifier. Al A 2 is a differential amplifier. A voltage proportional to the U-phase current i U and the V-phase current i V is output by amplifying the potential difference between both ends of the divided R l R 2. A3 and A4 are error amplifiers. A3 amplifies and outputs the error between the U-phase current command value and the detected U-phase current value, and A4 amplifies and outputs the error between the V-phase current command value and the detected V-phase current value .
B 1は PWM変調回路である。 U相、 V相の誤差増幅器の出力を受け、 誤差を解消 するべくパルス幅変調された、 主回路スィッチのドライブ信号を生成する。 B 2はゲ ートドライブ回路である。 PWM変調回路によって生成されたドライブ信号を主回路 の各スィッチのゲート （G1 G6) をドライブするのに必要な増幅とレベルシフト を行う。 G 1 G6のゲートドライブ信号によってオン ·オフ制御されたスィッチ S 1 S 6は出力端の電位を Pの正電位または Nの基底電位に適切にドライブするこ とにより、 U相電流指令と V相電流指令に相当する負荷電流 i U ί Vを発生させる。 W相の負荷電流 i Wついては、常に i W ( i U+ i V)の関係があるので、 i U i Vを制御すれば、 i Wは同時に一意に制御される。 この他にシャント抵抗をィンバ 一夕出力とモータとの間に入れてモータの各相に流れる電流を検出する技術として 特開平 11一 75396、 特開平 10— 123184がある。  B1 is a PWM modulation circuit. It receives the output of the U-phase and V-phase error amplifiers and generates a drive signal for the main circuit switch that is pulse width modulated to eliminate the error. B2 is a gate drive circuit. The drive signal generated by the PWM modulation circuit is amplified and level-shifted to drive the gates (G1 G6) of each switch in the main circuit. The switch S 1 S 6, which is on / off controlled by the G 1 G6 gate drive signal, drives the output terminal potential appropriately to the positive P potential or the N base potential, thereby allowing the U-phase current command and V-phase current A load current i U U V corresponding to the current command is generated. Since the W-phase load current i W always has a relation of i W (i U + i V), if i U i V is controlled, i W is uniquely controlled at the same time. In addition, Japanese Patent Application Laid-Open Nos. H11-75396 and H10-123184 disclose a technique of detecting a current flowing through each phase of a motor by inserting a shunt resistor between the output of the inverter and the motor.
図 3の従来技術において負荷電流を検出するシャント抵抗 R 1 R 2は各相アーム の出力端と負荷の間に直列に接続されているためにシャント抵抗両端の電位はスィ ツチがオン ·オフする度に基底電位 Nと高電圧の正電位 Pの間を瞬間的に変移するこ とになる。 一方、 シャント抵抗の抵抗値は発熱と電力の損失を最小限に抑えるために なるべく小さな値に設定される。 通常、 数 ηιΩから数十 ηιΩが一般的である。 そのた めシャント抵抗の両端にあらわれる電位差は非常に小さい。  In the prior art shown in Fig. 3, the shunt resistor R 1 R 2 that detects the load current is connected in series between the output terminal of each phase arm and the load, so the potential across the shunt resistor turns on and off the switch. Each time, there is an instantaneous transition between the base potential N and the high positive potential P. On the other hand, the resistance of the shunt resistor is set as small as possible to minimize heat generation and power loss. Usually, several ηιΩ to several tens ηιΩ are common. Therefore, the potential difference appearing at both ends of the shunt resistor is very small.
図 4はシャント抵抗 R 1のある状態での両端の電位を示したものである。 e 1は R 1の U相アーム側の電位であり、 実線で示している。 e 2は R 1の負荷側の電位であ り、 破線で示している。 Vdは e 1と e 2の電位差であり、 負荷電流によって生じた 電圧降下に相当する。 この図に示されるように、 e l e 2の電位波形は大振幅の矩 形波形に負荷電流による微小な電圧降下が重畳されたものとなる。例えば主回路電圧 2 0 0 ¥で 1の抵抗値1 Ο πιΩで 1 Aの負荷電流を検出すると仮定すると、電圧降 下は 1 O mVとなり、スイッチングによる 2 0 0 Vの電圧スイングに対してわずか 0 . 0 0 5 %となる。 e 1、 e 2は分圧抵抗によって、適当に分圧され、それぞれ e 1 ' 、 e 2 ' となるが、 この比率は変らない。 差動増幅器 A 1によって e 1 ' と e 2 ' の電 位差を正確に増幅することができれば、 負荷電流 i Uを検出できることになるが、 こ こで問題が生じる。 FIG. 4 shows the potential at both ends in the presence of the shunt resistor R1. e 1 is the potential on the U-phase arm side of R 1 and is indicated by a solid line. e 2 is the load-side potential of R 1 and is indicated by the broken line. Vd is the potential difference between e1 and e2, and corresponds to the voltage drop caused by the load current. As shown in this figure, the potential waveform of ele 2 is a rectangular waveform having a large amplitude and a small voltage drop due to the load current superimposed thereon. For example, main circuit voltage Assuming that a load current of 1 A is detected with a resistance value of 1 at 200 $ and a resistance value of 1 で πιΩ, the voltage drop is 1 OmV, which is only 0.000 V for a voltage swing of 200 V due to switching. 5%. e 1 and e 2 are appropriately divided by a voltage dividing resistor to become e 1 ′ and e 2 ′, respectively, but this ratio does not change. If the potential difference between e 1 ′ and e 2 ′ can be accurately amplified by the differential amplifier A 1, the load current i U can be detected, but this poses a problem.
差動増幅器 A 1から入力信号である e 1 '、 e 2 ' を見ると、 大振幅のコモンモ一 ド電圧に微小な検出すべき信号電圧が重畳していることになる。一般的に差動増幅器 の C MR R即ちコモンモード電圧除去比は周波数特性を持っており、周波数が高くな るほど悪化する。 従って、 スイッチングの周波数が高くなるほど、 誤差が増加し、 電 流検出精度が低下することになる。 電流検出精度が低下すれば、 結果として電流指令 に対する出力電流の精度も低下する。 この従来技術では、 スイッチング周波数は数 k H zから十数 k H zまでが実用的な限界であると考えられる。出力電流のリップル成 分を低減するため或いは高速な応答を実現するために高いスィツチング周波数と精 度の高い電流制御特性を求めることは従来技術では困難である。  Looking at the input signals e 1 ′ and e 2 ′ from the differential amplifier A 1, a small signal voltage to be detected is superimposed on the large amplitude common mode voltage. Generally, the CMRR of a differential amplifier, that is, the common mode voltage rejection ratio has a frequency characteristic, and becomes worse as the frequency becomes higher. Therefore, as the switching frequency increases, the error increases and the current detection accuracy decreases. If the current detection accuracy decreases, the accuracy of the output current with respect to the current command also decreases as a result. In this prior art, the switching frequency is considered to be a practical limit from several kHz to several tens kHz. It is difficult in the prior art to obtain a high switching frequency and a high-precision current control characteristic in order to reduce the ripple component of the output current or to achieve a high-speed response.
[発明の開示]  [Disclosure of the Invention]
そこで、 本発明は前述の問題点を解決するためになされたものであり、 その目的は スィツチング周波数が電流検出精度に影響することなく、高いスィツチング周波数と 精度の高い電流検出を両立することにある。  Therefore, the present invention has been made to solve the above-described problems, and an object of the present invention is to achieve both a high switching frequency and a high-precision current detection without affecting the switching frequency. .
上記問題を解決するため、本発明は三相プリッジによる主回路と負荷電流検出手段 と電流制御手段を備えた三相電流制御装置において、 前記負荷電流検出手段は、 正側 端子 Pと上ァ一ムトランジスタ S 1との間に設けられたシャント抵抗 R 1と、負側端 子 Nと前記上アームトランジスタ S 1と同相にある下アームトランジスタ S 2との 間に設けられたシャント抵抗 R 2と、 前記トランジスタ S l、 S 2と異なる相の上ァ ームトランジスタ S 3と正側端子 Pとの間に設けられたシャント抵抗 R 3と、前記上 アームトランジスタ S 3と同相にある下ァ一ムトランジスタ S 4と負側端子 Nとの 間に設けられたシャント抵抗 R 4と、前記シャント抵抗 R 1 - R 4によって計測され た電流値に基づいて負荷電流を演算する手段から構成したものである。  In order to solve the above problem, the present invention relates to a three-phase current control device including a main circuit based on a three-phase bridge, a load current detection unit, and a current control unit, wherein the load current detection unit includes: And a shunt resistor R2 provided between the negative terminal N and the lower arm transistor S2 in the same phase as the upper arm transistor S1. A shunt resistor R 3 provided between the upper arm transistor S 3 and the positive terminal P in a different phase from the transistors S 1 and S 2; and a lower resistor in the same phase as the upper arm transistor S 3. And a means for calculating a load current based on a current value measured by the shunt resistor R 1 -R 4 provided between the transistor S 4 and the negative terminal N. is there.
また、 前記上アームトランジスタ、 前記下アームトランジスタを I G B Tとしたも のである。  Further, the upper arm transistor and the lower arm transistor are IGBT.
また、 前記上アーム卜ランジス夕、 前記下アームトランジスタをパワー MO S F E Tとしたものである。  Further, the upper arm transistor and the lower arm transistor are each a power MOS FET.
[図面の簡単な説明]  [Brief description of drawings]
図 1は、 本発明の実施例を示す回路図である。 図 2は、 本発明の実施例の電流検出 シャント抵抗の端子電位波形図である。 図 3は、従来の三相電流制御装置を示す回路 図である。 図 4は、 従来の三相電流制御装置の電流検出シャント抵抗の端子電位波形 図である。 [発明を実施するための最良の形態] FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a terminal potential waveform diagram of the current detection shunt resistor according to the embodiment of the present invention. FIG. 3 is a circuit diagram showing a conventional three-phase current control device. FIG. 4 is a terminal potential waveform diagram of a current detection shunt resistor of a conventional three-phase current controller. [Best Mode for Carrying Out the Invention]
以下、 本発明の実施例を図 1に基づいて説明する。 図において、 Mは三相電流制御 装置の負荷となる電動機、 P、 Nは三相電流制御装置の主回路部に直流電圧を供給す るための端子であり、 正側が P、 負側が Nである。 三相電流制御装置は、 この直流電 圧をパルス幅変調することによって、可変周波の可変電圧を負荷となる電動機へ供給 する。  Hereinafter, an embodiment of the present invention will be described with reference to FIG. In the figure, M is a motor serving as a load for the three-phase current controller, P and N are terminals for supplying DC voltage to the main circuit of the three-phase current controller, and P is the positive side and N is the negative side. is there. The three-phase current controller supplies a variable voltage of a variable frequency to a motor as a load by pulse width modulating the DC voltage.
主回路部は U、 V、 Wの各相毎に 2つの半導体素子から構成される。 U相の直流電 圧の正側端子 Pと U相の主回路部出力端子 T uとの間に設けられた上アーム側スィ ツチングトランジスタを S 1、前記端子 T uと負側端子 Nとの間に設けられた下ァ一 ム側スィッチトランジスタを S 2とする。 U相と同様にして、 V相の上アーム側スィ ツチングトランジスタ、 下アーム側スイッチングトランジスタを各々 S 3、 S 4とす る。 また W相の上アーム側スイッチングトランジスタ、.下アームスイッチングトラン ジス夕も同様にして、 各々 S 5、 S 6とする。 V、 W相の主回路部出力端子を各々 T v、 Twとする。  The main circuit consists of two semiconductor elements for each phase of U, V, and W. The upper-arm switching transistor provided between the positive terminal P of the U-phase DC voltage and the output terminal Tu of the U-phase main circuit is S1, and the upper-arm switching transistor is connected between the terminal Tu and the negative terminal N. The lower-arm switch transistor provided therebetween is designated as S2. Similarly to the U-phase, the V-phase upper-arm switching transistor and the lower-arm switching transistor are S3 and S4, respectively. Similarly, the upper-arm switching transistor and the lower-arm switching transistor of the W phase are S5 and S6, respectively. The output terminals of the main circuit section of the V and W phases are Tv and Tw, respectively.
U相に設けられたシャント抵抗 R 1は正側端子 Pと上アームトランジスタ S 1と の間に、 シャント抵抗 R 2は負側端子 Nと下アームトランジス夕 S 2との間に構成さ れる。 U相と同様にして、 V相に設けられたシャント抵抗 R 3は正側端子 Pと上ァー ムトランジスタ S 3との間に、 シャント抵抗 R 4は負側端子 Nと下ァ一ムトランジス 夕 S 4との間に構成される。  The shunt resistor R1 provided in the U phase is provided between the positive terminal P and the upper arm transistor S1, and the shunt resistor R2 is provided between the negative terminal N and the lower arm transistor S2. Similarly to the U phase, the shunt resistor R 3 provided for the V phase is connected between the positive terminal P and the upper arm transistor S 3, and the shunt resistor R 4 is connected to the negative terminal N and the lower transistor. Composed between S4.
半導体スィッチ S 1〜S 6はパワー MO S F E Tや I G B T等が一般に用いられ、 三相ブリッジを構成している。 シャント抵抗 R 1〜R 4は、 両端の電位差によってそ のノードに流れる電流を検出する。 R 5〜R 1 2は分圧抵抗である。 R l、 R 3の両 端の電位は高電圧の P、 N間の主回路電圧まで上昇するので、 後段の差動増幅器に入 力可能な電圧まで分圧する。  As the semiconductor switches S1 to S6, power MOSFETs, IGBTs, and the like are generally used to form a three-phase bridge. The shunt resistors R1 to R4 detect the current flowing to that node based on the potential difference between both ends. R5 to R12 are voltage dividing resistors. Since the potentials at both ends of Rl and R3 rise to the high-voltage main circuit voltage between P and N, the voltage is divided to a voltage that can be input to the subsequent differential amplifier.
今、 R 1を流れる電流を i 1、 R 2を流れる電流を i 2、 U相に流れる負荷電流を i Uとすると、  Assuming that the current flowing through R1 is i1, the current flowing through R2 is i2, and the load current flowing through the U phase is iU,
i U= i 1— i 2 ( 1 ) 式  i U = i 1— i 2 (1)
となる。 It becomes.
従って、 i 1と i 2をそれぞれ R 1と R 2の両端の電位差から検出すれば、 U相の 負荷電流 i Uを求めることができる。 同様に、  Therefore, if i 1 and i 2 are detected from the potential difference between both ends of R 1 and R 2, the U-phase load current i U can be obtained. Similarly,
i V= i 3 - i 4 ( 2 ) 式  i V = i 3-i 4 (2)
となるので、 R 3、 R 4の両端の電位差から V相の負荷電流 i Vを求めることができ る。 A 1〜A 4は差動増幅器である。 それぞれシャント抵抗 R 1〜R 4の両端の電位 差から i 1〜 i 4の電流値を検出する。 Therefore, the V-phase load current i V can be obtained from the potential difference between both ends of R 3 and R 4. A1 to A4 are differential amplifiers. The current values of i1 to i4 are detected from the potential difference between both ends of the shunt resistors R1 to R4.
八1〜八4の差動増幅器のゲィンと尺5〜! 1 2の分圧抵抗の分圧比は i 1〜 i 4の電流値に対するゲインが等しくなるように適切に設定される。 A 5、 A 6は差動 増幅器であり、 それぞれ （1 ) 式、 （2 ) 式に示される演算を行い、 i U、 i Vに比 例した電圧を出力する。 A 7、 A 8は誤差増幅器であり、 それぞれ U相電流指令値、 V相電流指令値と対応する相の電流検出値の誤差である偏差を増幅して出力する。 B 1は P WM変調回路である。 U相、 V相の誤差増幅器の出力を受け、 誤差を解消する ベくパルス幅変調された、 主回路スィッチのドライブ信号を生成する。 B 2はゲート ドライブ回路である。 PWM変調回路によって生成されたドライブ信号を主回路の各 スィッチのゲート （G 1〜G 6 ) をドライブするのに必要な増幅とレベルシフトを行 う。 The gain ratios of the gains of the differential amplifiers 81 to 84 and the voltage dividing resistors of the scale 5 to! 12 are appropriately set so that the gains for the current values of i1 to i4 are equal. A5 and A6 are differential amplifiers that perform the operations shown in equations (1) and (2), respectively, and compare them with iU and iV. Output the example voltage. A7 and A8 are error amplifiers that amplify and output deviations between the U-phase current command value and the V-phase current command value and the current detection value of the corresponding phase. B1 is a PWM modulation circuit. Receives the output of the U-phase and V-phase error amplifiers and generates a pulse width modulated drive signal for the main circuit switch that eliminates the error. B 2 is a gate drive circuit. The drive signal generated by the PWM modulator is amplified and level-shifted to drive the gates (G1 to G6) of each switch in the main circuit.
G 1〜G 6のゲートドライブ信号によってオン ·オフ制御されたスィッチ S 1〜S 6は出力端の電位を Pの正電位または Nの基底電位に適切にドライブすることによ り、 U相電流指令と V相電流指令に相当する負荷電流 i U、 i Vを発生させる。 W相 の負荷電流 i Wついては、 常に i W=— ( i U+ i V) の関係があるので、 i U、 i Vを制御すれば、 i Wは同時に一意に制御される。  The switches S 1 to S 6, which are on / off controlled by the gate drive signals of G 1 to G 6, drive the potential of the output terminal appropriately to the positive potential of P or the base potential of N, so that the U-phase current And load currents iU and iV corresponding to the V-phase current command. Since the W-phase load current i W always has the relationship of i W = — (i U + i V), controlling i U and i V allows i W to be uniquely controlled simultaneously.
ここで、 図 2に U相負荷電流を検出する R 1、 R 2の両端の電位を示す。 R 1の主 回路電源の P側に接続された端子の電位 e 1は常に一定の高電位の状態にある。 のもう一方の端子の電位 e 2は e 1に対して、 R 1に流れる電流 i 1による電圧降下 V d 1の分だけ変移することになるので、 ごく僅かな電位変動しか生じない。 また、 R 2の主回路電源の N側に接続された端子の電位 e 4は常に一定の基底電位の状態 にある。 R 2のもう一方の端子の電位 e 3は e 4に対して R 2に流れる電流 i 2によ る電圧降下 V d 2の分だけ変移することになるので、 こちらもまた僅かな電位変動し か生じない。  Here, Fig. 2 shows the potentials at both ends of R1 and R2 for detecting the U-phase load current. The potential e 1 of the terminal connected to the P side of the main circuit power supply of R 1 is always in a constant high potential state. Since the potential e 2 of the other terminal of FIG. 4 changes with respect to e 1 by the voltage drop V d 1 due to the current i 1 flowing through R 1, only a very small potential fluctuation occurs. In addition, the potential e 4 of the terminal connected to the N side of the main circuit power supply of R 2 is always at a constant base potential. Since the potential e 3 at the other terminal of R 2 changes with respect to e 4 by the voltage drop V d 2 due to the current i 2 flowing through R 2, the potential fluctuates slightly as well. Does not occur.
A 1の差動増幅器から入力信号である e 1 '、 e 2 ' を見ると一定の直流高電圧に 負荷電流による微小な電圧降下が重畳されたものとなる。即ちコモンモード電圧が一 定の直流電圧になるので、スイッチング周波数による C M R Rの悪化の影響が無くな る。 A 2の差動増幅器についてはさらに高電圧のコモンモード電圧も生ぜず、 C M R Rが悪化する要因は存在しない。 以上のことは V相についても全く同様である。 電流 検出精度がスイッチング周波数によって影響を受けないので、結果として精度の高い 電流制御特性が得られる。  Looking at the input signals e 1 ′ and e 2 ′ from the differential amplifier of A 1, a small voltage drop due to the load current is superimposed on a constant high DC voltage. That is, since the common mode voltage becomes a constant DC voltage, the influence of the deterioration of CMRR due to the switching frequency is eliminated. The A2 differential amplifier does not generate a higher common-mode voltage, and there is no cause for deteriorating CMRR. The same is true for the V phase. Since the current detection accuracy is not affected by the switching frequency, a highly accurate current control characteristic is obtained as a result.
[産業上の利用可能性] ' : [Industrial applicability] ' :
本発明は、三相プリッジによる主回路と負荷電流検出手段と電流制御手段を備えた 三相電流制御装置において、 前記負荷電流検出手段は、 正側端子 Pと上アームトラン ジス夕 S 1との間に設けられたシャント抵抗 R 1と、負側端子 Nと前記上アームトラ ンジス夕 S 1と同相にある下アームトランジスタ S 2との間に設けられたシャント 抵抗 R 2と、 前記トランジスタ S 1、 S 2と異なる相の上アームトランジスタ S 3と 正側端子 Pとの間に設けられたシャント抵抗 R 3と、前記上アームトランジスタ S 3 と同相にある下アームトランジスタ S 4と負側端子 Nとの間に設けられたシャント 抵抗 R 4と、前記シャント抵抗 R 1〜R 4によって計測された電流値に基づいて負荷 電流を演算する手段から構成されている。 これにより検出すべき電圧に含まれるコモ ンモード電圧が一定の直流電圧になり、スィツチング周波数が電流検出精度に影響を 与えないので、高いスイッチング周波数と精度の高い電流制御特性を両立することが できる。 The present invention relates to a three-phase current control device including a main circuit based on a three-phase bridge, a load current detection unit, and a current control unit. A shunt resistor R 1 provided therebetween, a shunt resistor R 2 provided between the negative terminal N and the lower arm transistor S 2 which is in phase with the upper arm transistor S 1, and the transistor S 1, A shunt resistor R 3 provided between the upper arm transistor S 3 and the positive terminal P different from S 2, a lower arm transistor S 4 and a negative terminal N which are in phase with the upper arm transistor S 3. And a means for calculating a load current based on current values measured by the shunt resistors R1 to R4. As a result, the como included in the voltage to be detected Since the switching mode voltage becomes a constant DC voltage and the switching frequency does not affect the current detection accuracy, it is possible to achieve both a high switching frequency and a highly accurate current control characteristic.

Claims

請求の範囲 The scope of the claims
1 . 三相プリッジによる主回路と負荷電流検出手段と電流制御手段を備えた三相電 流制御装置において、  1. In a three-phase current control device equipped with a main circuit, load current detection means and current control means using a three-phase bridge,
前記負荷電流検出手段は、正側端子 Pと上アームトランジスタ S 1との間に設けら れたシャン卜抵抗 R 1と、負側端子 Nと前記上アームトランジスタ S 1と同相にある 下アームトランジスタ S 2との間に設けられたシャント抵抗 R 2と、前記トランジス 夕 S 1、 S 2と異なる相の上ァ一ムトランジスタ S 3と正側端子 Pとの間に設けられ たシャント抵抗 R 3と、前記上アームトランジスタ S 3と同相にある下アーム卜ラン ジス夕 S 4と負側端子 Nとの間に設けられたシャント抵抗 R 4と、前記シャント抵抗 R 1〜R 4によって計測された電流値に基づいて負荷電流を演算する手段から構成 されたことを特徴とする三相電流制御装置。  The load current detecting means includes a shunt resistor R 1 provided between the positive terminal P and the upper arm transistor S 1, and a lower arm transistor which is in phase with the negative terminal N and the upper arm transistor S 1. A shunt resistor R2 provided between the positive terminal P and an upper transistor S3 different from the transistors S1 and S2. And a shunt resistor R 4 provided between the lower arm transistor S 4 having the same phase as the upper arm transistor S 3 and the negative terminal N, and the shunt resistors R 1 to R 4. A three-phase current control device comprising means for calculating a load current based on a current value.
2 . 前記上アームトランジスタ、 前記下ァ一ムトランジスタが I G B Tである請求 項 1記載の三相電流制御装置。  2. The three-phase current controller according to claim 1, wherein the upper arm transistor and the lower arm transistor are IGBTs.
3 . 前記上アームトランジスタ、 前記下アームトランジスタがパワー MO S F E T である請求項 1記載の三相電流制御装置。  3. The three-phase current control device according to claim 1, wherein the upper-arm transistor and the lower-arm transistor have a power of MOSFET.
PCT/JP2003/008622 2002-07-10 2003-07-07 Three-phase current control device WO2004008620A1 (en)

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