JP4106704B2 - Three-phase current controller - Google Patents
Three-phase current controller Download PDFInfo
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- JP4106704B2 JP4106704B2 JP2002200683A JP2002200683A JP4106704B2 JP 4106704 B2 JP4106704 B2 JP 4106704B2 JP 2002200683 A JP2002200683 A JP 2002200683A JP 2002200683 A JP2002200683 A JP 2002200683A JP 4106704 B2 JP4106704 B2 JP 4106704B2
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
【０００１】
【発明の属する技術分野】
本発明は三相モータの駆動装置の電流制御装置の電流検出に関する。
【０００２】
【従来の技術】
従来、三相電流制御装置は図３に示すようになっている。図において、Ｓ１〜Ｓ６はパワーＭＯＳＦＥＴやＩＧＢＴといった半導体スイッチ素子であり、三相ブリッジを構成している。Ｒ１、Ｒ２はシャント抵抗であり、それぞれＵ相、Ｖ相の出力電流をシャント抵抗両端の電圧降下によって検出する。Ｒ３〜Ｒ１０は分圧抵抗である。Ｒ１、Ｒ２の両端の電位は高電圧のＰ、Ｎ間の主回路電圧まで上昇するので、後段の差動増幅器に入力可能な電圧まで分圧する。Ａ１、Ａ２は差動増幅器である。それぞれ分圧されたＲ１、Ｒ２の両端の電位差を増幅することにより、Ｕ相電流ｉＵとＶ相電流ｉＶに比例した電圧を出力する。Ａ３、Ａ４は誤差増幅器である。Ａ３はＵ相電流指令値と検出されたＵ相電流値との誤差を増幅して出力し、Ａ４はＶ相電流指令値と検出されたＶ相電流値との誤差を増幅して出力する。
【０００３】
Ｂ１はＰＷＭ変調回路である。Ｕ相、Ｖ相の誤差増幅器の出力を受け、誤差を解消するべくパルス幅変調された、主回路スイッチのドライブ信号を生成する。Ｂ２はゲートドライブ回路である。ＰＷＭ変調回路によって生成されたドライブ信号を主回路の各スイッチのゲート（Ｇ１〜Ｇ６）をドライブするのに必要な増幅とレベルシフトを行う。Ｇ１〜Ｇ６のゲートドライブ信号によってオン・オフ制御されたスイッチＳ１〜Ｓ６は出力端の電位をＰの正電位またはＮの基底電位に適切にドライブすることにより、Ｕ相電流指令とＶ相電流指令に相当する負荷電流ｉＵ、ｉＶを発生させる。Ｗ相の負荷電流ｉＷついては、常にｉＷ＝−（ｉＵ＋ｉＶ）の関係があるので、ｉＵ、ｉＶを制御すれば、ｉＷは同時に一意に制御される。この他にシャント抵抗をインバータ出力とモータとの間に入れてモータの各相に流れる電流を検出する技術として特開平11−75396、特開平10−123184がある。
【０００４】
図３の従来技術において負荷電流を検出するシャント抵抗Ｒ１、Ｒ２は各相アームの出力端と負荷の間に直列に接続されているためにシャント抵抗両端の電位はスイッチがオン・オフする度に基底電位Ｎと高電圧の正電位Ｐの間を瞬間的に変移することになる。一方、シャント抵抗の抵抗値は発熱と電力の損失を最小限に抑えるためになるべく小さな値に設定される。通常、数ｍΩから数十ｍΩが一般的である。そのためシャント抵抗の両端にあらわれる電位差は非常に小さい。
【０００５】
図４はシャント抵抗Ｒ１のある状態での両端の電位を示したものである。ｅ１はＲ１のＵ相アーム側の電位であり、実線で示している。ｅ２はＲ１の負荷側の電位であり、破線で示している。Ｖｄはｅ１とｅ２の電位差であり、負荷電流によって生じた電圧降下に相当する。この図に示されるように、ｅ１、ｅ２の電位波形は大振幅の矩形波形に負荷電流による微小な電圧降下が重畳されたものとなる。例えば主回路電圧２００ＶでＲ１の抵抗値１０ｍΩで１Ａの負荷電流を検出すると仮定すると、電圧降下は１０ｍＶとなり、スイッチングによる２００Ｖの電圧スイングに対してわずか０．００５％となる。ｅ１、ｅ２は分圧抵抗によって、適当に分圧され、それぞれｅ１’、ｅ２’となるが、この比率は変らない。差動増幅器Ａ１によってｅ１’とｅ２’の電位差を正確に増幅することができれば、負荷電流ｉＵを検出できることになるが、ここで問題が生じる。
【０００６】
差動増幅器Ａ１から入力信号であるｅ１’、ｅ２’を見ると、大振幅のコモンモード電圧に微小な検出すべき信号電圧が重畳していることになる。一般的に差動増幅器のＣＭＲＲ即ちコモンモード電圧除去比は周波数特性を持っており、周波数が高くなるほど悪化する。従って、スイッチングの周波数が高くなるほど、誤差が増加し、電流検出精度が低下することになる。電流検出精度が低下すれば、結果として電流指令に対する出力電流の精度も低下する。この従来技術では、スイッチング周波数は数ｋＨｚから十数ｋＨｚまでが実用的な限界であると考えられる。出力電流のリップル成分を低減するため或いは高速な応答を実現するために高いスイッチング周波数と精度の高い電流制御特性を求めることは従来技術では困難である。
【０００７】
【発明が解決しようとする課題】
そこで、本発明は前述の問題点を解決するためになされたものであり、その目的はスイッチング周波数が電流検出精度に影響することなく、高いスイッチング周波数と精度の高い電流検出を両立することにある。
【０００８】
【課題を解決するための手段】
上記問題を解決するため、本発明は、三相ブリッジによる主回路と、正側端子Ｐと上アームトランジスタＳ１との間に設けられたシャント抵抗Ｒ１、負側端子Ｎと前記上アームトランジスタＳ１と同相にある下アームトランジスタＳ２との間に設けられたシャント抵抗Ｒ２、前記トランジスタＳ１およびＳ２と異なる相の上アームトランジスタＳ３と正側端子Ｐとの間に設けられたシャント抵抗Ｒ３、並びに前記上アームトランジスタＳ３と同相にある下アームトランジスタＳ４と負側端子Ｎとの間に設けられたシャント抵抗Ｒ４で構成し、前記シャント抵抗Ｒ１〜Ｒ４によって計測された電流値に基づいて負荷電流を演算する負荷電流検出手段と、電流制御手段とを備えた三相電流制御装置において、
前記負荷電流検出手段は、前記シャント抵抗Ｒ１の正側端子Ｐ側端子と前記負側端子Ｎとの間に挿入して前記シャント抵抗Ｒ１の前記正側端子Ｐ側端子と前記負側端子Ｎとの間の電圧を分圧して後段の差動増幅器に入力可能な第一の分圧電位を作る第一の分圧手段と、前記シャント抵抗Ｒ１の上アームトランジスタＳ１側端子と前記負側端子Ｎとの間に挿入して前記シャント抵抗Ｒ１の前記上アームトランジスタＳ１側端子と前記負側端子Ｎとの間の電圧を分圧して後段の差動増幅器に入力可能な第二の分圧電位を作る第二の分圧手段と、前記負側端子Ｎを基準として、前記第一の分圧電位と前記第二の分圧電位との電位差を増幅する差動増幅器Ａ１と、前記負側端子Ｎを基準として、前記シャント抵抗Ｒ２の下アームトランジスタＳ２側端子の電位と前記シャント抵抗Ｒ２の負側端子Ｎ側の電位との電位差を増幅する差動増幅器Ａ２と、前記負側端子Ｎを基準として、前記差動増幅器Ａ１の出力電圧と前記差動増幅器Ａ２の出力電圧との電位差を増幅する差動増幅器Ａ５と、前記シャント抵抗Ｒ３の正側端子Ｐ側端子と前記負側端子Ｎとの間に挿入して前記シャント抵抗Ｒ３の前記正側端子Ｐ側端子と前記負側端子Ｎとの間の電圧を分圧して後段の差動増幅器に入力可能な第三の分圧電位を作る第三の分圧手段と、前記シャント抵抗Ｒ３の上アームトランジスタＳ３側端子と前記負側端子Ｎとの間に挿入して前記シャント抵抗Ｒ３の前記上アームトランジスタＳ３側端子と前記負側端子Ｎとの間の電圧を分圧して後段の差動増幅器に入力可能な第四の分圧電位を作る第四の分圧手段と、前記負側端子Ｎを基準として、前記第三の分圧電位と前記第四の分圧電位との電位差を増幅する差動増幅器Ａ３と、前記負側端子Ｎを基準として、前記シャント抵抗Ｒ４の下アームトランジスタＳ４側端子の電位と前記シャント抵抗Ｒ４の負側端子Ｎ側の電位との電位差を増幅する差動増幅器Ａ４と、前記負側端子Ｎを基準として、前記差動増幅器Ａ３の出力電圧と前記差動増幅器Ａ４の出力電圧との電位差を増幅する差動増幅器Ａ６と、を備えたことを特徴とするものである。
また、前記上アームトランジスタ、前記下アームトランジスタをＩＧＢＴとしたものである。
また、前記上アームトランジスタ、前記下アームトランジスタをパワーＭＯＳＦＥＴとしたものである。
【０００９】
【発明の実施の形態】
以下、本発明の実施例を図１に基づいて説明する。図において、Ｍは三相電流制御装置の負荷となる電動機、Ｐ、Ｎは三相電流制御装置の主回路部に直流電圧を供給するための端子であり、正側がＰ、負側がＮである。三相電流制御装置は、この直流電圧をパルス幅変調することによって、可変周波の可変電圧を負荷となる電動機へ供給する。主回路部はＵ、Ｖ、Ｗの各相毎に２つの半導体素子から構成される。Ｕ相の直流電圧の正側端子ＰとＵ相の主回路部出力端子Ｔｕとの間に設けられた上アーム側スイッチングトランジスタをＳ１、前記端子Ｔｕと負側端子Ｎとの間に設けられた下アーム側スイッチトランジスタをＳ２とする。Ｕ相と同様にして、Ｖ相の上アーム側スイッチングトランジスタ、下アーム側スイッチングトランジスタを各々Ｓ３、Ｓ４とする。またＷ相の上アーム側スイッチングトランジスタ、下アームスイッチングトランジスタも同様にして、各々Ｓ５、Ｓ６とする。Ｖ、Ｗ相の主回路部出力端子を各々Ｔｖ、Ｔｗとする。
【００１０】
Ｕ相に設けられたシャント抵抗Ｒ１は正側端子Ｐと上アームトランジスタＳ１との間に、シャント抵抗Ｒ２は負側端子Ｎと下アームトランジスタＳ２との間に構成される。Ｕ相と同様にして、Ｖ相に設けられたシャント抵抗Ｒ３は正側端子Ｐと上アームトランジスタＳ３との間に、シャント抵抗Ｒ４は負側端子Ｎと下アームトランジスタＳ４との間に構成される。
半導体スイッチＳ１〜Ｓ６はパワーＭＯＳＦＥＴやＩＧＢＴ等が一般に用いられ、三相ブリッジを構成している。シャント抵抗Ｒ１〜Ｒ４は、両端の電位差によってそのノードに流れる電流を検出する。Ｒ５〜Ｒ１２は分圧抵抗である。Ｒ１、Ｒ３の両端の電位は高電圧のＰ、Ｎ間の主回路電圧まで上昇するので、後段の差動増幅器に入力可能な電圧まで分圧する。
【００１１】
今、Ｒ１を流れる電流をｉ１、Ｒ２を流れる電流をｉ２、Ｕ相に流れる負荷電流をｉＵとすると、
ｉＵ＝ｉ１−ｉ２・・・・・・・・・・・・・・・（１）式
となる。
従って、ｉ１とｉ２をそれぞれＲ１とＲ２の両端の電位差から検出すれば、Ｕ相の負荷電流ｉＵを求めることができる。同様に、
ｉＶ＝ｉ３−ｉ４・・・・・・・・・・・・・・・（２）式
となるので、Ｒ３、Ｒ４の両端の電位差からＶ相の負荷電流ｉＶを求めることができる。Ａ１〜Ａ４は差動増幅器である。それぞれシャント抵抗Ｒ１〜Ｒ４の両端の電位差からｉ１〜ｉ４の電流値を検出する。
【００１２】
Ａ１〜Ａ４の差動増幅器のゲインとＲ５〜Ｒ１２の分圧抵抗の分圧比はｉ１〜ｉ４の電流値に対するゲインが等しくなるように適切に設定される。Ａ５、Ａ６は差動増幅器であり、それぞれ（１）式、（２）式に示される演算を行い、ｉＵ、ｉＶに比例した電圧を出力する。Ａ７、Ａ８は誤差増幅器であり、それぞれＵ相電流指令値、Ｖ相電流指令値と対応する相の電流検出値の誤差である偏差を増幅して出力する。Ｂ１はＰＷＭ変調回路である。Ｕ相、Ｖ相の誤差増幅器の出力を受け、誤差を解消するべくパルス幅変調された、主回路スイッチのドライブ信号を生成する。Ｂ２はゲートドライブ回路である。ＰＷＭ変調回路によって生成されたドライブ信号を主回路の各スイッチのゲート（Ｇ１〜Ｇ６）をドライブするのに必要な増幅とレベルシフトを行う。Ｇ１〜Ｇ６のゲートドライブ信号によってオン・オフ制御されたスイッチＳ１〜Ｓ６は出力端の電位をＰの正電位またはＮの基底電位に適切にドライブすることにより、Ｕ相電流指令とＶ相電流指令に相当する負荷電流ｉＵ、ｉＶを発生させる。Ｗ相の負荷電流ｉＷついては、常にｉＷ＝−（ｉＵ＋ｉＶ）の関係があるので、ｉＵ、ｉＶを制御すれば、ｉＷは同時に一意に制御される。
【００１３】
ここで、図２にＵ相負荷電流を検出するＲ１、Ｒ２の両端の電位を示す。Ｒ１の主回路電源のＰ側に接続された端子の電位ｅ１は常に一定の高電位の状態にある。Ｒ１のもう一方の端子の電位ｅ２はｅ１に対して、Ｒ１に流れる電流ｉ１による電圧降下Ｖｄ１の分だけ変移することになるので、ごく僅かな電位変動しか生じない。また、Ｒ２の主回路電源のＮ側に接続された端子の電位ｅ４は常に一定の基底電位の状態にある。Ｒ２のもう一方の端子の電位ｅ３はｅ４に対してＲ２に流れる電流ｉ２による電圧降下Ｖｄ２の分だけ変移することになるので、こちらもまた僅かな電位変動しか生じない。Ａ１の差動増幅器から入力信号であるｅ１’、ｅ２’を見ると一定の直流高電圧に負荷電流による微小な電圧降下が重畳されたものとなる。即ちコモンモード電圧が一定の直流電圧になるので、スイッチング周波数によるＣＭＲＲの悪化の影響が無くなる。Ａ２の差動増幅器についてはさらに高電圧のコモンモード電圧も生ぜず、ＣＭＲＲが悪化する要因は存在しない。以上のことはＶ相についても全く同様である。電流検出精度がスイッチング周波数によって影響を受けないので、結果として精度の高い電流制御特性が得られる。
【００１４】
【発明の効果】
本発明は三相ブリッジによる主回路と負荷電流検出手段と電流制御手段を備えた三相電流制御装置において、前記負荷電流検出手段は、正側端子Ｐと上アームトランジスタＳ１との間に設けられたシャント抵抗Ｒ１と、負側端子Ｎと前記上アームトランジスタＳ１と同相にある下アームトランジスタＳ２との間に設けられたシャント抵抗Ｒ２と、前記トランジスタＳ１、Ｓ２と異なる相の上アームトランジスタＳ３と正側端子Ｐとの間に設けられたシャント抵抗Ｒ３と、前記上アームトランジスタＳ３と同相にある下アームトランジスタＳ４と負側端子Ｎとの間に設けられたシャント抵抗Ｒ４と、前記シャント抵抗Ｒ１〜Ｒ４によって計測された電流値に基づいて負荷電流を演算する手段から構成されているので、検出すべき電圧に含まれるコモンモード電圧が一定の直流電圧になり、スイッチング周波数が電流検出精度に影響を与えないので、高いスイッチング周波数と精度の高い電流制御特性を両立することができる。
【図面の簡単な説明】
【図１】本発明の実施例を示す回路図
【図２】本発明の実施例の電流検出シャント抵抗の端子電位波形図
【図３】従来の三相電流制御装置を示す回路図
【図４】従来の三相電流制御装置の電流検出シャント抵抗の端子電位波形図
【符号の説明】
Ｓ１〜Ｓ６ 半導体スイッチ
Ｒ１〜Ｒ４ シャント抵抗
Ｒ５〜Ｒ１２ 分圧抵抗
Ａ１〜Ａ６ 差動増幅器
Ａ７〜Ａ８ 誤差増幅器
Ｂ１ ＰＷＭ変調回路
Ｂ２ ゲートドライブ回路
Ｇ１〜Ｇ６ Ｓ１〜Ｓ６のゲート
ｉＵ Ｕ相負荷電流
ｉＶ Ｖ相負荷電流
ｉＷ Ｗ相負荷電流
ｉ１ Ｒ１を流れる電流
ｉ２ Ｒ２を流れる電流
ｉ３ Ｒ３を流れる電流
ｉ４ Ｒ４を流れる電流
ｅ１ Ｒ１のＰ側端子電位
ｅ２ Ｒ１のＳ１側端子電位
ｅ３ Ｒ２のＳ２側端子電位
ｅ４ Ｒ２のＮ側端子電位
ｅ１’ 分圧されたＲ１のＰ側端子電位
ｅ２’ 分圧されたＲ１のＳ１側端子電位
ｅ３’ 分圧されたＲ２のＳ２側端子電位
ｅ４’ 分圧されたＲ２のＮ側端子電位
Ｖｄ１ Ｒ１の端子間電位差
Ｖｄ２ Ｒ２の端子間電位差
Ｖｄ Ｒ１の端子間電位差[0001]
BACKGROUND OF THE INVENTION
The present invention relates to current detection of a current control device of a driving device for a three-phase motor.
[0002]
[Prior art]
Conventionally, a three-phase current control device is as shown in FIG. In the figure, S1 to S6 are semiconductor switch elements such as power MOSFETs and IGBTs, and constitute a three-phase bridge. R1 and R2 are shunt resistors, which detect U-phase and V-phase output currents by voltage drops across the shunt resistors, respectively. R3 to R10 are voltage dividing resistors. Since the potential at both ends of R1 and R2 rises to the main circuit voltage between the high voltage P and N, the voltage is divided to a voltage that can be input to the subsequent differential amplifier. A1 and A2 are differential amplifiers. A voltage proportional to the U-phase current iU and the V-phase current iV is output by amplifying the potential difference between both ends of the divided R1 and R2. A3 and A4 are error amplifiers. A3 amplifies and outputs the error between the U-phase current command value and the detected U-phase current value, and A4 amplifies and outputs the error between the V-phase current command value and the detected V-phase current value.
[0003]
B1 is a PWM modulation circuit. The output of the U-phase and V-phase error amplifiers is received, and a drive signal for the main circuit switch that is pulse-width modulated to eliminate the error is generated. B2 is a gate drive circuit. The drive signal generated by the PWM modulation circuit is amplified and level-shifted to drive the gates (G1 to G6) of the switches of the main circuit. The switches S1 to S6, which are on / off controlled by the gate drive signals G1 to G6, appropriately drive the potential of the output terminal to the positive potential of P or the base potential of N, so that the U-phase current command and the V-phase current command Load currents iU and iV are generated. Since the W-phase load current iW always has a relationship of iW = − (iU + iV), if iU and iV are controlled, iW is uniquely controlled at the same time. In addition, there are JP-A-11-75396 and JP-A-10-123184 as techniques for detecting a current flowing in each phase of the motor by inserting a shunt resistor between the inverter output and the motor.
[0004]
In the prior art of FIG. 3, the shunt resistors R1 and R2 for detecting the load current are connected in series between the output end of each phase arm and the load. Therefore, the potential at both ends of the shunt resistor is changed every time the switch is turned on / off. There is an instantaneous transition between the base potential N and the high positive potential P. On the other hand, the resistance value of the shunt resistor is set as small as possible in order to minimize heat generation and power loss. Usually, several mΩ to several tens mΩ is common. Therefore, the potential difference appearing at both ends of the shunt resistor is very small.
[0005]
FIG. 4 shows the potentials at both ends when the shunt resistor R1 is present. e1 is a potential on the U-phase arm side of R1, and is indicated by a solid line. e2 is a potential on the load side of R1, and is indicated by a broken line. Vd is a potential difference between e1 and e2, and corresponds to a voltage drop caused by the load current. As shown in this figure, the potential waveforms of e1 and e2 are obtained by superimposing a small voltage drop due to a load current on a large amplitude rectangular waveform. For example, assuming that the main circuit voltage is 200 V and the load current of 1 A is detected when the resistance value of R1 is 10 mΩ, the voltage drop is 10 mV, which is only 0.005% with respect to the voltage swing of 200 V due to switching. e1 and e2 are appropriately divided by voltage dividing resistors to become e1 ′ and e2 ′, respectively, but this ratio does not change. If the potential difference between e1 ′ and e2 ′ can be accurately amplified by the differential amplifier A1, the load current iU can be detected, but this causes a problem.
[0006]
When e1 ′ and e2 ′ that are input signals from the differential amplifier A1 are viewed, a minute signal voltage to be detected is superimposed on a large-amplitude common mode voltage. In general, the CMRR, that is, the common mode voltage rejection ratio of the differential amplifier has frequency characteristics, and becomes worse as the frequency becomes higher. Therefore, as the switching frequency increases, the error increases and the current detection accuracy decreases. If the current detection accuracy decreases, as a result, the accuracy of the output current with respect to the current command also decreases. In this prior art, the switching frequency is considered to be a practical limit from several kHz to several tens of kHz. In order to reduce the ripple component of the output current or to realize a high-speed response, it is difficult to obtain a high switching frequency and a highly accurate current control characteristic with the conventional technology.
[0007]
[Problems to be solved by the invention]
Therefore, the present invention has been made to solve the above-described problems, and an object thereof is to achieve both high switching frequency and high-precision current detection without affecting the current detection accuracy. .
[0008]
[Means for Solving the Problems]
In order to solve the above problem, the present invention provides a main circuit by a three-phase bridge, a shunt resistor R1 provided between the positive terminal P and the upper arm transistor S1, a negative terminal N and the upper arm transistor S1. A shunt resistor R2 provided between the lower arm transistor S2 in the same phase, a shunt resistor R3 provided between the upper arm transistor S3 and a positive terminal P different from the transistors S1 and S2, and the upper shunt resistor R3. A shunt resistor R4 provided between the lower arm transistor S4 in phase with the arm transistor S3 and the negative terminal N is configured, and a load current is calculated based on a current value measured by the shunt resistors R1 to R4. a load current detecting means, in the three-phase current controller having a current control means,
The load current detecting means is inserted between the positive terminal P side terminal of the shunt resistor R1 and the negative terminal N, and the positive terminal P side terminal and the negative terminal N of the shunt resistor R1 A first voltage dividing means for dividing the voltage between the first and second differential amplifiers to generate a first divided potential that can be input to the differential amplifier of the subsequent stage, and the upper arm transistor S1 side terminal and the negative side terminal N of the shunt resistor R1. Between the upper arm transistor S1 side terminal and the negative side terminal N of the shunt resistor R1, and a second divided potential that can be input to the subsequent differential amplifier. A second voltage dividing means to be made; a differential amplifier A1 for amplifying a potential difference between the first divided potential and the second divided potential with reference to the negative terminal N; and the negative terminal N , The lower arm transistor S2 side end of the shunt resistor R2 The differential amplifier A2 amplifies the potential difference between the potential of the shunt resistor R2 and the potential on the negative terminal N side of the shunt resistor R2, and the output voltage of the differential amplifier A1 and the differential amplifier A2 with reference to the negative terminal N A differential amplifier A5 that amplifies the potential difference between the output voltage and the positive terminal P side of the shunt resistor R3 inserted between the positive terminal P side terminal and the negative terminal N of the shunt resistor R3. A third voltage dividing means for dividing a voltage between the terminal and the negative terminal N to generate a third divided potential that can be input to a differential amplifier at a subsequent stage, and an upper arm transistor S3 of the shunt resistor R3. Inserted between the side terminal and the negative side terminal N, the voltage between the upper arm transistor S3 side terminal of the shunt resistor R3 and the negative side terminal N can be divided and input to the differential amplifier at the subsequent stage. Fourth partial pressure hand that creates a fourth partial voltage potential A differential amplifier A3 that amplifies a potential difference between the third divided potential and the fourth divided potential with respect to the negative terminal N, and the shunt resistor with respect to the negative terminal N as a reference. A differential amplifier A4 that amplifies the potential difference between the potential of the lower arm transistor S4 side terminal of R4 and the potential of the negative side terminal N side of the shunt resistor R4, and the differential amplifier A3 using the negative side terminal N as a reference. And a differential amplifier A6 for amplifying a potential difference between the output voltage and the output voltage of the differential amplifier A4 .
The upper arm transistor and the lower arm transistor are IGBTs.
The upper arm transistor and the lower arm transistor are power MOSFETs.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to FIG. In the figure, M is an electric motor serving as a load of the three-phase current control device, P and N are terminals for supplying a DC voltage to the main circuit section of the three-phase current control device, P on the positive side and N on the negative side. . The three-phase current control device supplies a variable voltage having a variable frequency to an electric motor as a load by performing pulse width modulation on the DC voltage. The main circuit section is composed of two semiconductor elements for each of U, V, and W phases. The upper arm side switching transistor provided between the positive side terminal P of the U-phase DC voltage and the U-phase main circuit part output terminal Tu is provided between S1 and the terminal Tu and the negative side terminal N. The lower arm side switch transistor is S2. Similarly to the U phase, the upper arm side switching transistor and the lower arm side switching transistor of the V phase are denoted by S3 and S4, respectively. Similarly, the upper arm side switching transistor and the lower arm switching transistor of the W phase are denoted by S5 and S6, respectively. The V and W-phase main circuit unit output terminals are denoted by Tv and Tw, respectively.
[0010]
The shunt resistor R1 provided in the U phase is configured between the positive terminal P and the upper arm transistor S1, and the shunt resistor R2 is configured between the negative terminal N and the lower arm transistor S2. Similarly to the U phase, the shunt resistor R3 provided in the V phase is configured between the positive terminal P and the upper arm transistor S3, and the shunt resistor R4 is configured between the negative terminal N and the lower arm transistor S4. The
As the semiconductor switches S1 to S6, power MOSFETs, IGBTs and the like are generally used, and constitute a three-phase bridge. The shunt resistors R1 to R4 detect a current flowing through the node based on a potential difference between both ends. R5 to R12 are voltage dividing resistors. Since the potential at both ends of R1 and R3 rises to the main circuit voltage between the high voltage P and N, the voltage is divided to a voltage that can be input to the subsequent differential amplifier.
[0011]
Assuming that the current flowing through R1 is i1, the current flowing through R2 is i2, and the load current flowing through the U phase is iU,
iU = i1-i2 (1).
Therefore, if i1 and i2 are detected from the potential difference between both ends of R1 and R2, respectively, the U-phase load current iU can be obtained. Similarly,
Since iV = i3-i4 (2), the V-phase load current iV can be obtained from the potential difference between both ends of R3 and R4. A1 to A4 are differential amplifiers. Current values i1 to i4 are detected from potential differences between both ends of the shunt resistors R1 to R4, respectively.
[0012]
The gain of the differential amplifiers A1 to A4 and the voltage dividing ratio of the voltage dividing resistors R5 to R12 are appropriately set so that the gains for the current values i1 to i4 are equal. A5 and A6 are differential amplifiers that perform the calculations shown in equations (1) and (2), respectively, and output voltages proportional to iU and iV. A7 and A8 are error amplifiers, which amplify and output deviations that are errors in the detected current values of the phases corresponding to the U-phase current command value and the V-phase current command value, respectively. B1 is a PWM modulation circuit. The output of the U-phase and V-phase error amplifiers is received, and a drive signal for the main circuit switch that is pulse-width modulated to eliminate the error is generated. B2 is a gate drive circuit. The drive signal generated by the PWM modulation circuit is amplified and level-shifted to drive the gates (G1 to G6) of the switches of the main circuit. The switches S1 to S6, which are on / off controlled by the gate drive signals G1 to G6, appropriately drive the potential of the output terminal to the positive potential of P or the base potential of N, so that the U-phase current command and the V-phase current command Load currents iU and iV are generated. Since the W-phase load current iW always has a relationship of iW = − (iU + iV), if iU and iV are controlled, iW is uniquely controlled at the same time.
[0013]
Here, FIG. 2 shows potentials at both ends of R1 and R2 for detecting the U-phase load current. The potential e1 of the terminal connected to the P side of the main circuit power supply of R1 is always in a constant high potential state. Since the potential e2 of the other terminal of R1 is shifted by e1 by the voltage drop Vd1 due to the current i1 flowing through R1, only a slight potential fluctuation occurs. Further, the potential e4 of the terminal connected to the N side of the main circuit power supply of R2 is always at a constant base potential. Since the potential e3 of the other terminal of R2 is shifted by the amount of the voltage drop Vd2 due to the current i2 flowing through R2 with respect to e4, this also causes a slight potential fluctuation. When the input signals e1 ′ and e2 ′ are viewed from the differential amplifier A1, a small voltage drop due to the load current is superimposed on a constant DC high voltage. That is, since the common mode voltage is a constant DC voltage, the influence of CMRR deterioration due to the switching frequency is eliminated. The A2 differential amplifier does not generate a higher common mode voltage, and there is no cause for CMRR deterioration. The above is also true for the V phase. Since the current detection accuracy is not affected by the switching frequency, a highly accurate current control characteristic can be obtained as a result.
[0014]
【The invention's effect】
The present invention is a three-phase current control device comprising a main circuit by a three-phase bridge, a load current detection means and a current control means, wherein the load current detection means is provided between the positive terminal P and the upper arm transistor S1. A shunt resistor R1, a shunt resistor R2 provided between the negative terminal N and the lower arm transistor S2 in phase with the upper arm transistor S1, and an upper arm transistor S3 having a phase different from that of the transistors S1 and S2. A shunt resistor R3 provided between the positive terminal P, a shunt resistor R4 provided between the lower arm transistor S4 and the negative terminal N in phase with the upper arm transistor S3, and the shunt resistor R1. Since it is composed of means for calculating the load current based on the current value measured by R4, it is included in the voltage to be detected Common mode voltage is a constant DC voltage, the switching frequency does not affect the current detection accuracy, it is possible to achieve both high current control characteristics of high switching frequency and accuracy.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating an embodiment of the present invention. FIG. 2 is a terminal potential waveform diagram of a current detection shunt resistor according to an embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a conventional three-phase current control apparatus. ] Terminal potential waveform diagram of current detection shunt resistor of conventional three-phase current controller [Explanation of symbols]
S1 to S6 Semiconductor switches R1 to R4 Shunt resistors R5 to R12 Voltage dividing resistors A1 to A6 Differential amplifiers A7 to A8 Error amplifier B1 PWM modulation circuit B2 Gate drive circuits G1 to G6 S1 to S6 gates iU U-phase load current iV V Phase load current iW current W2 phase load current i1 current R2 flowing through R1 current i3 flowing through R2 current i4 flowing through R3 current e1 flowing through R4 P1 terminal potential e2 of R1 S1 terminal potential e3 of R1 S2 terminal potential e4 of R2 R2 N-side terminal potential e1 'divided R1 P-side terminal potential e2' divided R1 S1-side terminal potential e3 'divided R2 S2-side terminal potential e4' divided R2 N side terminal potential Vd1 R1 terminal potential difference Vd2 R2 terminal potential difference Vd R1 terminal potential difference
Claims (3)
前記負荷電流検出手段は、前記シャント抵抗Ｒ１の正側端子Ｐ側端子と前記負側端子Ｎとの間に挿入して前記シャント抵抗Ｒ１の前記正側端子Ｐ側端子と前記負側端子Ｎとの間の電圧を分圧して後段の差動増幅器に入力可能な第一の分圧電位を作る第一の分圧手段と、
前記シャント抵抗Ｒ１の上アームトランジスタＳ１側端子と前記負側端子Ｎとの間に挿入して前記シャント抵抗Ｒ１の前記上アームトランジスタＳ１側端子と前記負側端子Ｎとの間の電圧を分圧して後段の差動増幅器に入力可能な第二の分圧電位を作る第二の分圧手段と、
前記負側端子Ｎを基準として、前記第一の分圧電位と前記第二の分圧電位との電位差を増幅する差動増幅器Ａ１と、
前記負側端子Ｎを基準として、前記シャント抵抗Ｒ２の下アームトランジスタＳ２側端子の電位と前記シャント抵抗Ｒ２の負側端子Ｎ側の電位との電位差を増幅する差動増幅器Ａ２と、
前記負側端子Ｎを基準として、前記差動増幅器Ａ１の出力電圧と前記差動増幅器Ａ２の出力電圧との電位差を増幅する差動増幅器Ａ５と、
前記シャント抵抗Ｒ３の正側端子Ｐ側端子と前記負側端子Ｎとの間に挿入して前記シャント抵抗Ｒ３の前記正側端子Ｐ側端子と前記負側端子Ｎとの間の電圧を分圧して後段の差動増幅器に入力可能な第三の分圧電位を作る第三の分圧手段と、
前記シャント抵抗Ｒ３の上アームトランジスタＳ３側端子と前記負側端子Ｎとの間に挿入して前記シャント抵抗Ｒ３の前記上アームトランジスタＳ３側端子と前記負側端子Ｎとの間の電圧を分圧して後段の差動増幅器に入力可能な第四の分圧電位を作る第四の分圧手段と、
前記負側端子Ｎを基準として、前記第三の分圧電位と前記第四の分圧電位との電位差を増幅する差動増幅器Ａ３と、
前記負側端子Ｎを基準として、前記シャント抵抗Ｒ４の下アームトランジスタＳ４側端子の電位と前記シャント抵抗Ｒ４の負側端子Ｎ側の電位との電位差を増幅する差動増幅器Ａ４と、
前記負側端子Ｎを基準として、前記差動増幅器Ａ３の出力電圧と前記差動増幅器Ａ４の出力電圧との電位差を増幅する差動増幅器Ａ６と、を備えたことを特徴とする三相電流制御装置。Between the main circuit of the three-phase bridge, the shunt resistor R1 provided between the positive terminal P and the upper arm transistor S1, the negative terminal N and the lower arm transistor S2 in phase with the upper arm transistor S1. A shunt resistor R2 provided, a shunt resistor R3 provided between the upper arm transistor S3 and the positive terminal P different in phase from the transistors S1 and S2, and a lower arm transistor S4 in phase with the upper arm transistor S3 and provided is constituted by a shunt resistor R4 between the negative terminal N, the load current detection means for calculating the load current on the basis of the current value measured by the shunt resistor R1 to R4, and a current control means In the provided three-phase current control device,
The load current detecting means is inserted between the positive terminal P side terminal of the shunt resistor R1 and the negative terminal N, and the positive terminal P side terminal and the negative terminal N of the shunt resistor R1 A first voltage dividing means that divides the voltage between the first and second voltages to generate a first divided potential that can be input to a differential amplifier at a subsequent stage;
Inserted between the upper arm transistor S1 side terminal and the negative terminal N of the shunt resistor R1, and divides the voltage between the upper arm transistor S1 side terminal and the negative terminal N of the shunt resistor R1. A second voltage dividing means for generating a second divided potential that can be input to the differential amplifier at the subsequent stage;
A differential amplifier A1 that amplifies a potential difference between the first divided potential and the second divided potential with respect to the negative terminal N;
A differential amplifier A2 for amplifying a potential difference between a potential of the lower arm transistor S2 side terminal of the shunt resistor R2 and a potential of the negative side terminal N side of the shunt resistor R2 with respect to the negative side terminal N;
A differential amplifier A5 that amplifies a potential difference between an output voltage of the differential amplifier A1 and an output voltage of the differential amplifier A2 with respect to the negative terminal N;
Inserted between the positive terminal P side terminal and the negative terminal N of the shunt resistor R3 to divide the voltage between the positive terminal P side terminal and the negative terminal N of the shunt resistor R3. A third voltage dividing means for generating a third divided potential that can be input to the differential amplifier at the subsequent stage;
Inserted between the upper arm transistor S3 side terminal and the negative terminal N of the shunt resistor R3, and divides the voltage between the upper arm transistor S3 side terminal and the negative terminal N of the shunt resistor R3. A fourth voltage dividing means for generating a fourth divided potential that can be input to the differential amplifier at the subsequent stage;
A differential amplifier A3 for amplifying a potential difference between the third divided potential and the fourth divided potential with respect to the negative terminal N;
A differential amplifier A4 for amplifying a potential difference between a potential of the lower arm transistor S4 side terminal of the shunt resistor R4 and a potential of the negative side terminal N side of the shunt resistor R4 with respect to the negative side terminal N;
A three-phase current control comprising: a differential amplifier A6 that amplifies a potential difference between an output voltage of the differential amplifier A3 and an output voltage of the differential amplifier A4 with respect to the negative terminal N. apparatus.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| JP2002200683A JP4106704B2 (en) | 2002-07-10 | 2002-07-10 | Three-phase current controller |
| PCT/JP2003/008622 WO2004008620A1 (en) | 2002-07-10 | 2003-07-07 | Three-phase current control device |
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| JP2002200683A JP4106704B2 (en) | 2002-07-10 | 2002-07-10 | Three-phase current controller |
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| JP2007078599A (en) * | 2005-09-16 | 2007-03-29 | Hitachi Ltd | Resistor for current detection and controller |
| JP4607075B2 (en) * | 2006-09-05 | 2011-01-05 | 三菱電機株式会社 | DC motor current detection device and galvano scanner system |
| WO2011003220A1 (en) * | 2009-07-09 | 2011-01-13 | Texas Instruments Incorporated | Inverter current measurement using shunt resistor |
| JP2013172528A (en) * | 2012-02-20 | 2013-09-02 | Toyota Motor Corp | Voltage conversion device |
| JP2016164490A (en) * | 2015-03-06 | 2016-09-08 | キヤノン株式会社 | Current detector, driving device, and industrial machine |
| CN104820124A (en) * | 2015-03-20 | 2015-08-05 | 国家电网公司 | Three-phase harmonic wave current detection method based on synchronization rotation mean value theory |
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