WO2003100759A1 - Dispositif d'affichage d'images ou d'affichage video et procede de regulation d'une frequence de rafraichissement d'ecran - Google Patents

Dispositif d'affichage d'images ou d'affichage video et procede de regulation d'une frequence de rafraichissement d'ecran Download PDF

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Publication number
WO2003100759A1
WO2003100759A1 PCT/GB2003/002294 GB0302294W WO03100759A1 WO 2003100759 A1 WO2003100759 A1 WO 2003100759A1 GB 0302294 W GB0302294 W GB 0302294W WO 03100759 A1 WO03100759 A1 WO 03100759A1
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WIPO (PCT)
Prior art keywords
image
display
refresh
displayed
video
Prior art date
Application number
PCT/GB2003/002294
Other languages
English (en)
Inventor
Philip David Austin
Original Assignee
Sendo International Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0212142.4A external-priority patent/GB0212142D0/en
Application filed by Sendo International Limited filed Critical Sendo International Limited
Priority to AU2003241015A priority Critical patent/AU2003241015A1/en
Priority to JP2004508327A priority patent/JP2005534047A/ja
Publication of WO2003100759A1 publication Critical patent/WO2003100759A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3218—Monitoring of peripheral devices of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3265—Power saving in display device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0613—The adjustment depending on the type of the information to be displayed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/10—Special adaptations of display systems for operation with variable images
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • H04W52/0267—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by controlling user interface components
    • H04W52/027—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by controlling user interface components by controlling a display operation or backlight unit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • This invention relates to a method of reducing power consumption of a display.
  • the invention is applicable to, but not limited to, display devices used in battery powered apparatus, such as personal digital assistants (PDAs) or mobile phones, where battery power to operate and refresh the display is limited.
  • PDAs personal digital assistants
  • mobile phones where battery power to operate and refresh the display is limited.
  • Future generation mobile and fixed communication systems are expected to provide the capability for video and image transmission as well as the more conventional voice and data services.
  • video and image services for communication devices will become more prevalent, and improvements in video/image compression technology are likely to be needed in order to satisfy the anticipated consumer demand within the available communication bandwidt .
  • the image fades with time. Therefore, it is necessary for the image to be refreshed in order for it to remain clear. Therefore, the pixel data is constantly, and cyclically, being retrieved from memory, provided to the LCD and used to refresh the image one pixel at a time.
  • the refresh rate of a display must be set to be sufficiently high for the human eye not to perceive the difference in the image before and after it is refreshed. Otherwise visible flickering of the image occurs .
  • an image or video communication device as claimed in Claim 5.
  • a display driver for controlling a refresh rate of a display device, as Claimed in claim 7.
  • a video or image display device as claimed in Claim 8.
  • a display driver for controlling the refresh rate of a display device, as claimed in Claim 12.
  • the present invention provides a means of varying or halting a clock provided to display refresh circuitry to halt or vary a refresh rate of a display, dependent upon the type of image being displayed. In this manner, when the display does not need to be refreshed based on the image being displayed a reduction in the overall power consumption of the display device can be achieved.
  • FIG. 1 shows a block diagram of a battery-powered wireless subscriber unit adapted to support the inventive concepts of the preferred embodiments of the present invention.
  • FIG. 2 shows a block diagram of a preferred display driver arrangement of the subscriber unit of FIG. 1.
  • FIG. 3 shows a graphical illustration of a display refresh operation.
  • FIG. 4 shows timing diagrams of a subscriber unit used to support the inventive concepts of the preferred embodiments of the present invention.
  • FIG. 5 shows a block diagram of part of a processor system that handles the provision of clock signals, in accordance with an enhanced embodiment of the present invention.
  • FIG. 6 shows a flowchart of a preferred process of- adapting a refresh rate of a display, in accordance with an preferred embodiment of the present invention.
  • the inventor of the present invention has recognised that, at present, no distinction is made as to the refresh rates for different images being displayed.
  • the same refresh rate is used for both static images and moving pictures.
  • a static, i.e. fixed, image does not require as high a refresh rate as, for example, a moving picture such as a video clip or the like. This results in the display being refreshed more than is needed when a static image is being displayed. Such a refresh rate consumes unnecessary power.
  • PDA personal data assistant
  • PC wirelessly networked personal computer
  • FIG. 1 there is shown a block diagram of a cellular subscriber unit 100 adapted to support the inventive concepts of the preferred embodiments of the present invention.
  • the subscriber unit 100 contains an antenna 102 preferably coupled to a duplex filter, antenna switch or circulator 104 that provides isolation between receiver and transmitter chains within the subscriber unit 100.
  • the receiver chain includes scanning receiver front-end circuitry 106 (effectively providing reception, filtering and intermediate or baseband frequency conversion) .
  • the scanning front-end circuit 106 is serially coupled to a signal processing function 108.
  • An output from the signal processing function 108 is provided to a suitable output device 110, such as a screen or flat panel liquid crystal display.
  • the screen or flat panel display 110 includes a display driver circuit 111.
  • each pixel within the display device is typically refreshed.
  • the receiver chain also includes received signal strength indicator (RSSI) circuitry 112, which in turn is coupled to a controller 114 for maintaining overall subscriber unit control.
  • RSSI received signal strength indicator
  • a timer 118 is operably coupled to the controller 114 to control the timing of operations
  • the controller 114 is also coupled to the scanning receiver front-end circuitry 106 and the signal processing function 108 (generally realised by a DSP) for receiving a transmitted video or image signal.
  • the controller 114 may therefore receive bit error rate (BER) or frame error rate (FER) data from recovered information.
  • BER bit error rate
  • FER frame error rate
  • the interaction between the microprocessor 108 and the output device 110 and display driver circuit 111 has been adapted to reduce power consumption of the respective elements.
  • the reduction in power consumption is achieved by the microprocessor 108 determining, or being informed, of the type of image, for example static or video, to be displayed on the display 110.
  • the microprocessor adapts or halts a refresh operation of the display, thereby reducing power consumption of the respective devices used in the refresh operation.
  • determining a type of image to be displayed would be to simply identify the image by the file type (e.g. bitmap being a static image and MPEG being a video clip etc.).
  • a default mode could be set to substantially static images, and only when certain applications are running (i.e. those capable of displaying video clips etc.) does the microprocessor revert to a normal refresh operation.
  • FIG. 2 illustrates a block diagram of a liquid crystal display (LCD) control/driver circuit 200, in accordance with the preferred embodiment of the present invention.
  • a microprocessor for example the microprocessor 108 of FIG. 1, initialises an LCD controller 140 and a DMA controller 220 by way of control registers 132.
  • the microprocessor 108 manages the contents of image memory 210 via an address bus 134 and a data bus 136. In this regard, in accordance with the preferred embodiment of the present invention, the microprocessor determines the type of image to be displayed.
  • the LCD controller 140 is also connected to an LCD panel 110 by way of three timing links 142a, 142b, 142c that provide timing signals vertical (V) -sync, horizontal (H) - sync and pixel clock respectively.
  • the DMA controller 220 drives pixel data bus 144, by way of a data latch
  • the LCD panel 110 includes an LCD display and control circuitry (not shown) .
  • the LCD controller 140 also provides timing control signals to the LCD panel 110, the DMA controller 220 and the data latch 240 to coordinate the retrieval and making available of pixel data.
  • the DMA controller 220 retrieves pixel data for the image to be displayed from the memory device 210 via an address bus and data bus. The pixel data retrieved from the memory is then passed to a data latch 240.
  • the LCD panel 110 receives the timing signals provided by the LCD controller 140 and, in response to the timing signals, retrieves the data for each pixel. The LCD panel 110 then systematically displays the corresponding image one pixel at a time.
  • the microprocessor 108 initiates an adapted image refresh operation.
  • the adapted image refresh operation includes either temporarily halting timing signals being supplied to the aforementioned devices used in the refresh operation, or reducing the rate of timing signals supplied to these devices so that the refresh rate is reduced.
  • LCD control/driver circuit 200 illustrated in FIG. 2 is only an example of a suitable LCD driver circuitry apparatus, and that any other suitable circuitry known may alternatively be adapted to facilitate and perform the inventive concepts described herein.
  • the pixel data is constantly, and cyclically, being retrieved from memory, provided to the LCD panel and used to refresh the image one pixel at a time.
  • each pixel within the display device is refreshed, starting at the top left corner 310 and refreshing each pixel row-by-row 320-360, as illustrated in FIG. 3.
  • An exception to this may be when interleaving is used, whereby odd and even lines of pixels are alternately refreshed.
  • a display refresh operation is preferably controlled in response to a status of particular signal timings 410, as shown in the graph 400 of FIG. 4.
  • the preferred embodiment of the present invention utilises timing of signals that include vertical synchronisation (V-Sync) 420, horizontal synchronisation (H-Sync) 430, data 440 and pixel clock 450, associated with the display in conjunction with the received video or image signal (s).
  • V-Sync vertical synchronisation
  • H-Sync horizontal synchronisation
  • s data 440
  • pixel clock 450 associated with the display in conjunction with the received video or image signal (s).
  • the frequencies of H-Sync 430 and the pixel clock 450 are multiples of the V-Sync 420 frequency.
  • the V-Sync signal 420 is used to inform the display device 110 when to commence incorporating the next whole image or commence refreshing portions of the current image.
  • the V-Sync signal 420 essentially controls when the vertical alignment of the refresh operation returns to the top of the display device, as shown by the top left hand corner 310 of FIG. 3.
  • every low pulse of the V-Synch causes the refresh cycle to start at the top again thereby essentially setting a display refresh rate.
  • the H-Sync signal 430 is used to inform the display device when to begin to refresh the next horizontal line (row) of pixels. Hence, the H-Sync signal 430 controls when the horizontal alignment of the refresh operation returns to the start of a new row, at the left hand side of the screen of the display 110.
  • the Data signal 440 contains the data for each pixel of the display device. This data is divided into blocks, where each block represents a row on the display device. As shown in FIG. 4, these blocks correspond to the H-Sync timing signal 430. Furthermore, it is envisaged that the data contained in a row is further divided into a series of pixels, where each pixel is preferably further partitioned into bits that relate to the primary colours red, green and blue.
  • the microprocessor 108 monitors a timing signal of a refresh operation of the display.
  • the timing signal monitored is preferably one of V-Sync, H- Sync or Pixel Clock.
  • the V-Sync signal is also provided to the microprocessor 108, for example by way of a general purpose input/output port (not shown) of the microprocessor 108, so that the microprocessor 108 is able to monitor the V-Sync signal.
  • the microprocessor 108 is preferably the main processor of the device in which the display and control/driver circuit are provided. However, it is within the contemplation of the present invention for the device to comprise a further processor (not shown) for performing tasks other than controlling the display and display control/driver circuit. Where this is the case, the V-Sync signal may alternatively be monitored by the further processor of the device.
  • the microprocessor 108 determines an opportunity to reduce or halt the refresh rate, based on the type of image to be displayed on the LCD panel 110, the microprocessor 108 interrupts, say, a clock signal (not shown) provided to the control/driver circuit 200 to halt the refresh operation.
  • the clock signal for the driver/control circuit 200 illustrated is provided to the LCD controller 140, which controls the timing and synchronisation of the various elements of the control/driver circuit 200 during a refresh operation.
  • the effect of halting the clock signal provided thereto is that the control/driver circuit 200, with the exception of the microprocessor 108, will in essence be ⁇ frozen' .
  • the halting of the clock signal is preferably achieved by the microprocessor 108, or by a further processor of the device, by way of clock management functionality, which may be an integral part of the microprocessor 108, or further processor of the device.
  • the clock signal control may be provided by a separate clock management unit 570 (of FIG. 5) .
  • the clock management unit 570 controls clock signals provided to various components of the device in which the display 110 and control/driver circuit 200 are provided. Where the clock management unit 570 halts the clock signal for the control/driver circuit 200, this is preferably performed under instruction from the microprocessor 108, as described later.
  • the microprocessor determines when to resume the clock signal to the control/driver circuit 200, to resume the refresh operation.
  • the period of time for which the clock signal is interrupted is selected such that an image being displayed by the display remains substantially unaffected to the human eye.
  • the normal refresh rate of the display 110 can be such that the display is refreshed sufficiently frequently for moving pictures and the like, such as video clips, to be adequately displayed without a user of the device experiencing flickering etc.
  • the refresh rate can be reduced by periodically halting the refresh operation as described above.
  • the clock signal is halted once each refresh cycle, i.e. once for each complete display refresh.
  • This can most easily be achieved by monitoring the V-Sync signal, as described above.
  • the V-Sync signal is, for the illustrated embodiment, set ⁇ high' during the refresh cycle (V-Sync duty cycle) .
  • the V-Sync signal goes low' for a short duration 422 before again going high to signify the start of the next refresh cycle.
  • the microprocessor 108 monitors the V-Sync signal. When a low signal is detected, signifying the short period between refresh cycles, the microprocessor 108 halts, or causes to halt, the clock signal to the control/driver circuit 200 for a required period of time. The effect of this is to extend the period between refresh cycles, effectively reducing the number of refresh cycles per second, and so reducing the refresh rate. Thus, the refresh rate can be variably reduced as required by varying the period of time for which the clock signal to the control/driver circuit 200 is halted.
  • a display device for example a mobile communications device, comprising a display and a display control/driver circuit, and in which the above described method of the present invention is implemented,
  • FIG. 5 illustrates an example of part of a processor system 500 that handles the provision of clock signals to a processor (CPU) , for example the microprocessor 108 of FIG. 2, and peripheral components of the microprocessor 108 within the processor system 500, such as a traffic controller (TC) 520, display driver circuit (LCD), for example the control/driver circuit illustrated in FIG. 2 200, external memory interface (EMIF) 540 etc.
  • TC traffic controller
  • LCD display driver circuit
  • EMIF external memory interface
  • the display driver 200 is a liquid crystal display driver, which is used to drive a liquid crystal display (not shown) such as a thin film transistor (TFT) display, with which the processor system 500 is used.
  • a driver for any other type of display, with which the processor system 500 is used may be substituted for the liquid crystal display driver without affecting the scope of the present invention.
  • an oscillator 550 provides a clock signal to the processor system 500.
  • This clock signal is used as an origin for further clock signals within the processor system 500. It will therefore be referred hereinafter as the seed clock signal.
  • the seed clock signal has a frequency of 12MHz.
  • the processor system 500 comprises a Digital Phased Locked Loop (DPLL) 560, which has as an input the 12MHz seed clock signal from the oscillator 550.
  • the DPLL 560 uses the seed clock signal to generate as an output a reference clock signal (RF_CLK) , by multiplying and/or dividing the seed clock signal.
  • RF_CLK reference clock signal
  • the processor system 500 further comprises a clock management unit 570 for providing clock management functionality of the device, which has as an input the reference clock signal generated by the DPLL 560.
  • the clock management unit 570 multiplies and/or divides the reference clock signal from the DPLL 560 to provide individual clock signals for the microprocessor 108 and its peripheral components.
  • the clock management unit provides a CP ⁇ _CLK clock signal to the microprocessor 108, a TC__CLK clock signal to the traffic controller 520, an LCD_CLK clock signal to the display driver 200 and an EMIF_CLK clock signal to the external memory interface 540, along with any further clock signals required within the processor system 500.
  • the clock rates provided to each of the microprocessor 108 and peripheral components 520, 200, 540 are dependent jointly on the generation of the reference clock signal REF_CLK by the DPLL 560, and individually on the generation of the specific clock signals CPU_CLK, TC_CLK, LCD_CLK and EMIF_CLK by the clock management unit 570.
  • the DPLL 560 and clock management unit 570 are each configurable by the microprocessor 108, such that the microprocessor 108 is able to adjust the clock signals provided by them. In this way, the microprocessor 108 is able to alter the clock signals provided to itself and to the peripheral components, both universally through reconfiguration of the DPLL 560 and/or individually through reconfiguration of the clock management unit 570.
  • the display control/driver 200 controls a refresh operation of the display (not shown) of the device.
  • a clock signal provided to the control/driver circuit is interrupted, for example by the clock management unit 570, to halt the refresh operation. This is preferably initiated by the microprocessor 108, which monitors the timing signal, and when required instructs the clock management unit 570 to halt the clock signal to the display control/driver circuit 200.
  • the clock signal to the control/driver circuit is resumed. For example, the resumption of the clock signal to the control/driver circuit is made in response to a signal from the microprocessor 108 to the clock management unit 570, to resume the refresh operation.
  • the period of time for which the clock signal is interrupted is selected such that an image being displayed by the display remains substantially unaffected to the human eye.
  • the process includes the step of a processor receiving an image to be displayed, in step 610.
  • the processor determines the type of image to be displayed, by any known mechanism, as shown in step 620.
  • the processor (or clock management function) then varies or halts one or more clock signals provided to any circuit or device in the display refresh (control and/or driver) circuitry, for a period of time, to vary the refresh rate of the image being displayed.
  • the refresh rate is varied or halted in response to the type of images being displayed to keep the power consumption of the display device to a minimum without noticeable flickering of the display device to the display viewer/user.
  • Power consumption of a display device is dynamically optimised whilst maintaining a quality of viewed image or video.
  • a portable communication device having a display and a method of reducing the refresh rate of a display, in particular when displaying a static image, have been described that substantially alleviate the problems of known display technology.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Multimedia (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention concerne un dispositif d'affichage vidéo ou d'affichage d'images (100) comprenant un écran (110) sur lequel peut être affichée une image, ainsi qu'un circuit de rafraîchissement d'écran (200) couplé fonctionnellement à l'écran (110), ce circuit servant à rafraîchir une image affichée sur l'écran (110). Un processeur (108), couplé fonctionnellement à l'écran (110) et au circuit de rafraîchissement d'écran (200), traite une image reçue de façon à déterminer le type d'image à afficher. Le processeur (108) modifie ensuite ou bloque un signal d'horloge fourni au circuit de rafraîchissement d'écran en fonction de l'image affichée. De cette manière, la fréquence de rafraîchissement est modifiée ou bloquée d'après le type de l'image affichée, ce qui permet de réduire constamment la consommation d'énergie du dispositif d'affichage sans provoquer de scintillement de l'affichage.
PCT/GB2003/002294 2002-05-27 2003-05-27 Dispositif d'affichage d'images ou d'affichage video et procede de regulation d'une frequence de rafraichissement d'ecran WO2003100759A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2003241015A AU2003241015A1 (en) 2002-05-27 2003-05-27 Image or video display device and method of controlling a refresh rate of a display
JP2004508327A JP2005534047A (ja) 2002-05-27 2003-05-27 ディスプレイのリフレッシュレートを制御するイメージ又はビデオディスプレイ装置及び方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GBGB0212142.4 2002-05-27
GBGB0212142.4A GB0212142D0 (en) 2002-05-27 2002-05-27 Method of controlling a refresh rate of a display
GB0214112A GB2381931B (en) 2002-05-27 2002-06-20 Method of controlling a refresh rate of a display
GBGB0214112.5 2002-06-20

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WO2003100759A1 true WO2003100759A1 (fr) 2003-12-04

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JP (1) JP2005534047A (fr)
KR (1) KR20050060033A (fr)
AU (1) AU2003241015A1 (fr)
WO (1) WO2003100759A1 (fr)

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US8179388B2 (en) 2006-12-15 2012-05-15 Nvidia Corporation System, method and computer program product for adjusting a refresh rate of a display for power savings
US8207977B1 (en) 2007-10-04 2012-06-26 Nvidia Corporation System, method, and computer program product for changing a refresh rate based on an identified hardware aspect of a display system
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EP2652730A1 (fr) * 2010-12-13 2013-10-23 ATI Technologies ULC Procédé et appareil fournissant une indication de trame statique
EP3144773A4 (fr) * 2014-05-14 2017-06-28 ZTE Corporation Procédé et dispositif permettant d'ajuster la fréquence de rafraîchissement matériel d'un terminal
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WO2007072377A3 (fr) * 2005-12-22 2007-10-11 Nokia Corp Ajustement de rafraichissement d'un ecran d'affichage
US7605794B2 (en) 2005-12-22 2009-10-20 Nokia Corporation Adjusting the refresh rate of a display
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EP2293272A1 (fr) * 2006-08-31 2011-03-09 ATI Technologies ULC Réglage de fréquences d'images dynamique
US8451279B2 (en) * 2006-12-13 2013-05-28 Nvidia Corporation System, method and computer program product for adjusting a refresh rate of a display
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US8207977B1 (en) 2007-10-04 2012-06-26 Nvidia Corporation System, method, and computer program product for changing a refresh rate based on an identified hardware aspect of a display system
US8284210B1 (en) 2007-10-04 2012-10-09 Nvidia Corporation Bandwidth-driven system, method, and computer program product for changing a refresh rate
EP2244246A1 (fr) * 2009-04-24 2010-10-27 Sony Ericsson Mobile Communications AB Appareil, procédé et programme d'affichage
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EP2652730A4 (fr) * 2010-12-13 2014-06-18 Ati Technologies Ulc Procédé et appareil fournissant une indication de trame statique
EP2652730A1 (fr) * 2010-12-13 2013-10-23 ATI Technologies ULC Procédé et appareil fournissant une indication de trame statique
CN102968978A (zh) * 2011-08-31 2013-03-13 联想(北京)有限公司 一种显示刷新率的控制方法及装置
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WO2013029493A1 (fr) * 2011-08-31 2013-03-07 联想(北京)有限公司 Procédé et dispositif de commande de fréquence de rafraîchissement d'affichage
WO2013089960A1 (fr) * 2011-12-14 2013-06-20 Qualcomm Incorporated Gestion d'énergie d'une image statique
US10082860B2 (en) 2011-12-14 2018-09-25 Qualcomm Incorporated Static image power management
US10600379B2 (en) 2013-01-14 2020-03-24 Apple Inc. Low power display device with variable refresh rates
EP2943948B1 (fr) * 2013-01-14 2020-07-29 Apple Inc. Dispositif d'affichage de faible puissance ayant une fréquence de rafraîchissement variable
EP3144773A4 (fr) * 2014-05-14 2017-06-28 ZTE Corporation Procédé et dispositif permettant d'ajuster la fréquence de rafraîchissement matériel d'un terminal
US10339987B2 (en) 2014-05-14 2019-07-02 Zte Corporation Method and device for adjusting hardware refresh rate of terminal

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