WO2003075464A1 - Module de commande de ligne a consommation d'electricite reduite - Google Patents

Module de commande de ligne a consommation d'electricite reduite Download PDF

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Publication number
WO2003075464A1
WO2003075464A1 PCT/IB2003/000888 IB0300888W WO03075464A1 WO 2003075464 A1 WO2003075464 A1 WO 2003075464A1 IB 0300888 W IB0300888 W IB 0300888W WO 03075464 A1 WO03075464 A1 WO 03075464A1
Authority
WO
WIPO (PCT)
Prior art keywords
transmitter
taps
transmission line
transistors
transmitted data
Prior art date
Application number
PCT/IB2003/000888
Other languages
English (en)
Inventor
Igor Anatolievich Abrosimov
Alexander Roger Deas
Original Assignee
Igor Anatolievich Abrosimov
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Igor Anatolievich Abrosimov filed Critical Igor Anatolievich Abrosimov
Priority to AU2003207915A priority Critical patent/AU2003207915A1/en
Publication of WO2003075464A1 publication Critical patent/WO2003075464A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

Abstract

L'invention concerne des moyens de réduction de la consommation d'électricité d'un émetteur par l'intermédiaire de la mémorisation de l'historique récent des données transmises à l'aide de chaînes de portes logiques présentant des prises provenant de la chaîne prise en des points déterminés par le retard de propagation de chaque porte et par l'intermédiaire de la commande de transistors en fonction de la comparaison de cet historique avec les données entrées de manière que le signal soit mené dans la ligne de transmission à une force complète ou à un niveau proche du minimum nécessaire pour conserver l'état du récepteur. L'avantage de cette invention tient du fait que la capacité de ligne diminue à travers les résistances ou les transistors de décharge de terminaison de manière que, lorsqu'une modification de l'état suivant se fait sentir, la ligne ait moins d'énergie stockée à décharger.
PCT/IB2003/000888 2002-03-06 2003-03-06 Module de commande de ligne a consommation d'electricite reduite WO2003075464A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003207915A AU2003207915A1 (en) 2002-03-06 2003-03-06 Line driver with reduced power consumption

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US36169002P 2002-03-06 2002-03-06
US60/361,690 2002-03-06

Publications (1)

Publication Number Publication Date
WO2003075464A1 true WO2003075464A1 (fr) 2003-09-12

Family

ID=27789133

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/000888 WO2003075464A1 (fr) 2002-03-06 2003-03-06 Module de commande de ligne a consommation d'electricite reduite

Country Status (2)

Country Link
AU (1) AU2003207915A1 (fr)
WO (1) WO2003075464A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1940028A1 (fr) * 2006-12-29 2008-07-02 STMicroelectronics S.r.l. Système d'interconnexion asynchrone pour une communication entre puces en 3D

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5995730A (ja) * 1982-11-25 1984-06-01 Toshiba Corp 半導体デジタル集積回路
US4728822A (en) * 1983-04-26 1988-03-01 Nec Corporation Data processing system with improved output function
US4758743A (en) * 1986-09-26 1988-07-19 Motorola, Inc. Output buffer with improved di/dt
US5128555A (en) * 1991-03-18 1992-07-07 Motorola, Inc. Pulsed CMOS logic circuit having selectable rise and fall times
US5319260A (en) * 1991-07-23 1994-06-07 Standard Microsystems Corporation Apparatus and method to prevent the disturbance of a quiescent output buffer caused by ground bounce or by power bounce induced by neighboring active output buffers
US5495187A (en) * 1994-03-25 1996-02-27 Philips Electronics North America Corporation CMOS input with Vcc compensated dynamic threshold
US5717343A (en) * 1996-07-23 1998-02-10 Pericom Semiconductor Corp. High-drive CMOS output buffer with noise supression using pulsed drivers and neighbor-sensing

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5995730A (ja) * 1982-11-25 1984-06-01 Toshiba Corp 半導体デジタル集積回路
US4728822A (en) * 1983-04-26 1988-03-01 Nec Corporation Data processing system with improved output function
US4758743A (en) * 1986-09-26 1988-07-19 Motorola, Inc. Output buffer with improved di/dt
US5128555A (en) * 1991-03-18 1992-07-07 Motorola, Inc. Pulsed CMOS logic circuit having selectable rise and fall times
US5319260A (en) * 1991-07-23 1994-06-07 Standard Microsystems Corporation Apparatus and method to prevent the disturbance of a quiescent output buffer caused by ground bounce or by power bounce induced by neighboring active output buffers
US5495187A (en) * 1994-03-25 1996-02-27 Philips Electronics North America Corporation CMOS input with Vcc compensated dynamic threshold
US5717343A (en) * 1996-07-23 1998-02-10 Pericom Semiconductor Corp. High-drive CMOS output buffer with noise supression using pulsed drivers and neighbor-sensing

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 008, no. 209 (E - 268) 22 September 1984 (1984-09-22) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1940028A1 (fr) * 2006-12-29 2008-07-02 STMicroelectronics S.r.l. Système d'interconnexion asynchrone pour une communication entre puces en 3D

Also Published As

Publication number Publication date
AU2003207915A1 (en) 2003-09-16

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