WO2003075337A1 - Assemblage sans flux de paquets a semi-conducteurs de la taille de puce - Google Patents

Assemblage sans flux de paquets a semi-conducteurs de la taille de puce Download PDF

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Publication number
WO2003075337A1
WO2003075337A1 PCT/US2002/006183 US0206183W WO03075337A1 WO 2003075337 A1 WO2003075337 A1 WO 2003075337A1 US 0206183 W US0206183 W US 0206183W WO 03075337 A1 WO03075337 A1 WO 03075337A1
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WIPO (PCT)
Prior art keywords
pad
pads
substrate
forming
die
Prior art date
Application number
PCT/US2002/006183
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English (en)
Other versions
WO2003075337A8 (fr
Inventor
Stanislav A. Garyainov
Alexander S. Gotman
Vladimir V. Novikov
Original Assignee
Agng, Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agng, Llc filed Critical Agng, Llc
Priority to US10/501,431 priority Critical patent/US7098072B2/en
Priority to PCT/US2002/006183 priority patent/WO2003075337A1/fr
Publication of WO2003075337A1 publication Critical patent/WO2003075337A1/fr
Publication of WO2003075337A8 publication Critical patent/WO2003075337A8/fr

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates, in general, to the soldering of one substrate to another with electrically conductive eutectic alloys, and in particular, to the electrical assembly and hermetic sealing of chip size semiconductor packages without the use of fluxes or reducing atmospheres.
  • ICs are formed in the "active" surface of a single die, or “chip,” cut from a semiconductor wafer containing an integral array of identical dies.
  • the dies are relatively small and fragile, are susceptible to harmful environmental elements, particularly moisture, and during operation, can generate a relatively large amount of heat in a relatively small volume. Accordingly, ICs are typically assembled in affordable, yet robust, packages that protect them from the environment, enable them to be reliably mounted to and interconnected with, for ex- ample, a printed circuit board (“PCB”) populated with associated electronic components, and to effectively dissipate to the ambient the heat they generate during operation.
  • PCB printed circuit board
  • the conventional BGA package 100 comprises a semiconductor die 102 soldered to and in electrical connection with an interconnective sub- strate 104, the latter serving both to redistribute the electrical input/output (“I/O") signals to and from the die, and to assist in the hermetic sealing of the die against harmful environmental agents, including moisture.
  • I/O electrical input/output
  • a laminate type of substrate 104 typically comprises one or more dielectric layers 106 on which one or more patterned metal layers 108 are formed.
  • the metal layers 108 are patterned, typically by photo-etching techniques, to include signal connection pads 110 on the upper surface of the dielectric layer 106 and terminal lands 112 on the lower surface thereof.
  • the connection pads 110 are connected to the lands 112 through the thickness of the substrate 102 by plated-through holes 114, called "vias.”
  • the metal layers 108 may also be patterned to include circuit traces 116 on one or both surfaces of the dielectric layer 106 that connect one or both of the connection pads 110 and the lands 112 to each other through the vias 114.
  • balls 118 of a conductive metal are formed on respective ones of the lands 112, which are arranged in the form of a "grid,” or rectangular array, to serve as signal input/output and mounting terminals of the package 100.
  • the terminal balls 118 are omitted, and the lands 112 themselves serve as the package terminals.
  • signal I/O pads 120 on the active surface of the die 102 may be bonded to the signal connection pads 110 on the substrate 104 with fine, conductive wires (not illustrated), or alternatively, as illustrated in Fig. 6, soldered directly to the connection pads 110 using the so-called “flip-chip,” or "C4,” method of die attachment, typically with a flux and a solder comprising lead (Pb) and tin (Sn).
  • the technique involves forming bumps of a conductive metal, e.g., solder, on the signal I/O pads 120 on the active surface of the chip 102, then inverting, or "flipping" the chip upside-down and “reflowing,” or fusing, the solder bumps to the corresponding connection pads 110 on the substrate 104, which is conventionally effected in a conveyor oven using a flux.
  • a conductive metal e.g., solder
  • the package 100 is typically hermetically sealed by molding a dense body 122 of plastic, e.g., a. filled epoxy resin, over the mounted die 102 and at least a portion of the substrate 104, or alternatively, by attaching, e.g., by soldering, a metal lid 124 (shown by dashed outline in Figs. 5 and 6) to the substrate that covers the die.
  • a dense body 122 of plastic e.g., a. filled epoxy resin
  • a metal lid 124 shown by dashed outline in Figs. 5 and 6
  • the underfill layer 126 serves to support the die 102 above the substrate 104 and prevent the plastic of an encapsulating body 122 from penetrating into the space and forming a potentially destructive "thermal wedge" between the die and the substrate at elevated temperatures, or alternatively, to prevent any flux residue remaining in the package from the solder attachment of a lid from corroding the connection pads and the active surface of the die during the life of the package.
  • Another drawback of the conventional package is the need for separate, costly processes and structures for hermetically sealing the active surface of the die and the electrical contacts between the die and the substrate from the ambient. It is therefore desirable to provide a method for hermetically sealing a semiconductor package without the need for these additional processes and materials, and further, to effect such a seal simultaneously with the electrical connection of the die to the substrate.
  • a method is pro- vided for soldering a first substrate, e.g., a semiconductor die, to and in electrical connection with, a second substrate, e.g., an interconnective substrate of a semiconductor package, with low-melting-temperature, electrically conductive eutectic alloys, including lead-free alloys, without using fluxes or reducing atmospheres.
  • a method is provided for hermeti- cally sealing a semiconductor package simultaneously with the electrical connection of the die to the substrate without additional sealing processes and materials. The method of the invention is characterized by forming one or more first electrically conductive pads on a first surface of the first substrate.
  • the first pads may comprise, e.g., the signal input/output pads on the active surface of a semiconductor die. Each of the first pads includes at least an upper portion comprising at least one component of an electrically conductive eutectic alloy. One or more electrically conductive second pads are formed on a first surface of the second substrate.
  • the second pads may comprise, e.g., the signal connection pads on an interconnective substrate of a semiconductor package. Each of the second pads includes at least an upper portion comprising at least one other component of the eutectic alloy and corresponds in number and placement to a respective one of the first pads on the first substrate, thereby defining one or more corresponding pairs of pads on the two substrates.
  • the respective first surfaces of the first and second substrates are urged toward each other such that the respective upper surfaces of the first and second pads in each corresponding pair thereof are brought together in a forceful opposing abutment with each other.
  • the opposing pads are then heated to at least the soldering temperature of the eutectic alloy, and until the one or more sharp peaks on the at least one pad in each corresponding pair thereof penetrate through any oxide films on the respective upper surfaces of the opposing pair of pads and contact the upper surface of the opposing other pad in the pair. This initiates melting and dissolution of the respective upper portions of the opposing pads into each other without the need for a flux or reducing atmosphere.
  • the opposing pads After joining, the opposing pads are cooled to solidify the inter-dissolved, molten eutectic upper portions thereof into an electrically conductive joint between each corresponding pair of pads.
  • Semiconductor packages assembled by the method of the invention may be hermetically sealed by conventional techniques, e.g., by encapsulation with plastic or with a sealing lid, but in one particularly advantageous embodiment of the invention, the first and second pads can further comprise a pair of corresponding frames formed around the respective peripheries of the respective first surfaces of the die and the interconnective substrate.
  • the two frames thereby have the same structure and alloy constituency as respective ones of the first and second signal pads, and are soldered to each other simultaneously with the soldering together of the corresponding pairs of signal pads of the die and the substrate, thereby closing and hermetically sealing the narrow space inside of the joined frames and between the respective first surfaces of the die and the substrate, including the active surface of the die and the electrical contacts between the die and the substrate, from the ambient.
  • Figure 1 is a top plan view of a chip size semiconductor package assembled in accordance with one method of the present invention
  • Fig. 2 is an enlarged cross-sectional elevation view of the package shown in Fig. 1, as revealed by the section taken along the lines II-II therein;
  • Fig. 3 is a bottom plan view of the package shown in Figs. 1 and 2;
  • Fig. 4 A is an enlarged cross-sectional detail view of the encircled portion IN-IV of the package shown in Fig. 2, showing one mode for carrying out the invention;
  • Fig. 4B is a cross-sectional detail view similar to that of Fig. 4A, showing another mode for carrying out the invention
  • Fig. 4C is a cross-sectional detail view similar to that of Fig. 4 A, showing yet another mode for carrying out the invention
  • Fig. 4D is a cross-sectional detail view similar to that of Fig. 4A, showing still yet another mode for carrying out the invention
  • Fig. 5 is a top plan view of a chip size BGA semiconductor package assembled in accordance with the method of the prior art
  • Fig. 6 is an enlarged cross-sectional elevation view of the package shown in Fig. 5, as revealed by the section taken along the lines NI-NI therein; and, Fig. 7 is a bottom plan view of the prior art package shown in Figs. 5 and 6.
  • a chip size semiconductor package 10 assembled in accordance with the method of the present invention is illustrated in the top plan, cross-sectional elevation, and bottom plan views of Figs. 1-3, respectively.
  • the novel package 10 com- prises a first substrate 12, e.g., a semiconductor die, having a first, active surface with one or more electrically conductive first pads 14, e.g., signal I/O pads, formed thereon, soldered to and in electrical connection with one or more corresponding electrically conductive second pads 16, e.g., signal connection pads, formed on a first surface of a second substrate 18, e.g., an interconnective substrate of the pack- age 10, in accordance with the method of the invention.
  • the respective first and second pads 14 and 16 of the die 12 and interconnective substrate 18 may further comprise a pair of corresponding first and second sealing frames 20 and 22, each extending around a periphery of a respective one of the first surfaces of the die and the substrate, which are used to hermetically seal the package 10 in the manner described below.
  • the first substrate 12 may otherwise comprise a conventional semiconductor die that is cut, or "singulated,” from a wafer of semiconductor material, e.g. , silicon or germanium (Ge), containing an integral array of identical dies 14, each of which includes an IC formed in the first, or active, surface thereof by conventional semiconductor fabrication techniques, including conventional photolithography, etching, doping, chemical vapor deposition, plating and vapor deposition processes. Indeed, as dis- cussed below, several of these same conventional techniques can also be used for forming the corresponding pairs of signal pads 14 and 16, and the optional corre- sponding sealing frames 20 and 22, on respective ones of the first and second substrates 12 and 18.
  • semiconductor fabrication techniques including conventional photolithography, etching, doping, chemical vapor deposition, plating and vapor deposition processes.
  • the second, or interconnective, substrate 18 comprises a laminate of a dielectric layer 24 having opposite first and second surfaces, each with a respective one of first and second patterned metal layers 26 and 28 disposed thereon.
  • the metal layer 26 on the first, or upper, surface of the substrate 18 may be patterned to include at least a lower portion of the second, signal connection pads 16 described above, and the metal layer 28 on the second, or lower, surface of the substrate 18 may be patterned to include an array of terminal lands 30.
  • Plated-through metal vias 32 electrically connect the first metal layer 26 to the second metal layer 28 through the thickness of the dielectric layer 24.
  • the through-openings in the substrate 18 created by the vias 32 can be filled, e.g., with a "plug" 34 of solder or an electrically conductive epoxy resin, to ensure that there are no discontinuities in the substrate through which moisture can enter into the narrow space 36 between the two substrates and contaminate the first, or active surface of the die or the electrical connections between the die and the second substrate 18.
  • the metal layers 26 and 28 may additionally be patterned to include circuit traces 38 on one or both surfaces of the dielectric layer 24, for electrically connecting the connection pads 16 through the vias 32 and to the lands 30.
  • Metal bumps 40 e.g., of solder, may be formed on respective ones of the lands 30 to serve, in the case of a BGA type of package 10, as I/O terminals of the package, or in the case of a LGA or LCC type of package, the lands 30 may be left bare to function themselves as package I/O terminals.
  • the interconnective substrate 18 of the invention may comprise one of a variety of possible embodiments.
  • the dielectric layer 24 can comprise a ceramic, e.g., silicon dioxide (SiO 2 ), gallium arsenide ("GAS"), quartz, alumina, aluminum nitride (“A1N”), or a laminate of one or more layers of the foregoing materials
  • the metal layers 26 and 28 can comprise, e.g. , a tungsten-bearing ink that is printed on the ceramic layer in the pattern desired, and then "co-fired" with the ceramic layer to form a hard, rigid structure.
  • the dielectric layer 24 can comprise one or more layers of a resin, such as polyimide, on which the metal layers 26 and 28, e.g., copper or aluminum foil, are laminated or plated, then patterned using conventional photolithography and etching techniques.
  • the dielectric layer 24 may comprise a matrix of fiberglass or polycarbonate fibers impregnated with a resin, e.g., an epichloridehydrin bisphenol-A (epoxy) resin, a bismaleimidetriazine (“BT”) resin, or a polytetra- fluoroethylene (“PTFE”) resin.
  • a resin e.g., an epichloridehydrin bisphenol-A (epoxy) resin, a bismaleimidetriazine (“BT”) resin, or a polytetra- fluoroethylene (“PTFE”) resin.
  • the method of soldering the die 12 in electrical connection with the substrate 18 of the present invention is not limited to the above, “laminate,” types of interconnective substrates 18, but can also be carried out in conjunction with conventional metal lead frame types of substrates (not illustrated), for assembling so-called “Lead-On-Chip” (“LOC”) types of semiconductor packages.
  • laminate types of interconnective substrates 18, but can also be carried out in conjunction with conventional metal lead frame types of substrates (not illustrated), for assembling so-called “Lead-On-Chip” (“LOC”) types of semiconductor packages.
  • LOC Lead-On-Chip
  • the second, interconnective substrate 18 of the invention is, with the exception of the connection pads 16 and optional sealing frame 22 formed thereon, and the method whereby they are soldered to the corresponding pads 14 and frame 20 on the first substrate or die 12, otherwise relatively conventional in its construction.
  • Figs. 4A - 4D are enlarged cross-sectional detail views of the encircled portion IN-IN of the package 10 shown in Fig. 2, each illustrating a different mode for carrying out the invention.
  • the method is characterized by forming the one or more first pads 14, which may include forming the optional sealing frame 20, on the first surface of the first substrate 12, i.e., the active surface of a semiconductor die, and forming the one or more corresponding second pads 16, which may include forming the optional corresponding sealing frame 22, on the first surface of the second, interconnective substrate 18.
  • the first or signal I/O pads 14 are formed to intersect, and thereby electrically connect with, an electrically conductive trace (not illustrated), e.g., a metalli- zation formed on or within the die 12, which in turn, is electrically connected to the IC (not illustrated) contained therein, and to include at least an upper portion comprising at least one component of an electrically conductive eutectic alloy.
  • the second pads 16 are formed to intersect, and thereby electrically connect with, a cir- cuit trace 38 patterned on the second substrate 18, and to include at least an upper portion comprising at least one other component of the eutectic alloy.
  • each of the respective first and second pads 14 and 16 and sealing frames 20 and 22 consists entirely of a respective one of the at least one eutectic alloy components associated with the re- spective substrate.
  • pads 14 and 16 and frames 20 and 22 having respective lower portions 42, 44, 46 and 48 that are of a material that is electrically conductive, e.g., a metal or a semiconductor, but which does not necessarily include any of the eutectic alloy components.
  • the particular eutectic alloy used in forming the respective pads 14 and 16 and frames 20 and 22 may be selected in accordance with the particular properties desired thereof, e.g., its soldering temperature. It should be understood, however, that if more than one component of the alloy is present on either pad or frame in a corresponding pair thereof, then the portion of that pad or land comprising the eutectic components must comprise the full complement of the alloy, and not just a single component thereof, and further, that the components of the alloy must be present in the specific percentages, by weight, necessary to constitute the eutectic alloy.
  • the first pads 14 and frame 20 may consist entirely of silicon, and the second pads 16 and frame 22 may consist entirely of gold, with the amounts of the respective two components of the alloy in the respective sets of pads and frames being relatively unimportant.
  • at least one or both sets of pads and frames in each corresponding pair thereof may comprise both of the components of the eutectic alloy, i.e., 94% Au + 6% Si.
  • at least one of the pads and frames in each corresponding pair thereof must include all three of the components of the eutectic alloy, and in the weight percentages of the individual components thereof indicated above, and optionally, both pads and frames in each corresponding pair thereof may comprise the complete alloy.
  • the method of the present invention further includes forming at least one sharp, upstanding peak 50 on an upper surface of at least one of the pads and frames in each corresponding pair thereof.
  • the sharp peaks 50 are shown formed on respective ones of the second pads 16 and the frame 22, i.e., those of the second, interconnective substrate 18.
  • the peaks 50 may instead be formed on respective ones of the other, first pads 14 and frame 20, or alternatively, on respective ones of both sets of the first and second pads and frames.
  • the sharp peaks 50 serve the primary function of penetrating through any oxide films 52, shown in the figures as a dark line on the outer surfaces of the re- .
  • the sharp peaks 50 are formed on the pads and frames first, and then covered with a coating 56 or 62 of the eutectic alloy or component thereof, thereby forming conforming sharp peaks 58 on the upper surface of the overlying eutectic coating, then the material of the first formed peaks 50 may comprise either the same or a different material than that comprising the upper portion of the respective pad or frame on which they are formed.
  • the pads 14 and 16 and frames 20 and 22 can be formed by either a "positive” process, in which the material is deposited on the target areas defined by openings thorough a suitable mask, or alternatively, in a "negative” process, in which the material is deposited as a single layer over the entire substrate, and the unwanted portions of the layer then removed, e.g., by photo-etching techniques.
  • the sharp upstanding peaks 50 of the pads 14 and 16 and frames 20 and 22 can be formed by similar masking and vacuum deposition techniques, but with the additional requirement that the sidewalls of the peaks taper to a relatively sharp point.
  • the sharp peaks 50 are deposited onto the target surface as macroscopic conical or pyramidal structures using conventional vacuum deposition techniques and a two-layer, metal mask (not illustrated).
  • the upper layer of the mask is very thin and includes a small, circular "pin-hole" aperture through it.
  • the lower metal layer has a greater thickness, viz., slightly greater than the desired height of the peak 50 to be formed, and has a larger circular aper- ture through it, viz.
  • the sharp peaks 50 have height of about 6-7 ⁇ m, and a base diameter of about 30 ⁇ m.
  • the sharp peaks 50 should be distributed uniformly over the surface of the respective pads 14 and 16 and frames 20 and 22, and in such number that they occupy from between about 1 to 10% of the total area of the respective pad or frame on which they are formed.
  • FIG. 4B Another mode for carrying out the invention is illustrated in the enlarged cross sectional view of Fig. 4B.
  • the arrangement in Fig. 4B is similar to that shown in Fig. 4 A, except that the respective pads 14 and 16 and frames 20 and 22 comprise respective lower portions 42, 44, 46 and 48 that, while of a material that is electrically conductive, e.g., a metal or a semiconductor, does not necessarily include any of the eutectic alloy components comprising the upper portion of the pad or frame.
  • a material that is electrically conductive e.g., a metal or a semiconductor
  • the respective lower portions 42, 44, 46 and 48 of the respective first and second pads 14 and 16 and frames 20 and 22 can comprise the same respective materials used in the metallizations of the die 14, typically alumi- num, and the patterned metal layers 26 and 28 of the interconnective substrate 18, respectively, which may include copper, aluminum, tungsten, gold, nickel, silver, or layers thereof.
  • the upper portions of the pads 14 and 16 and frames 20 and 22 that comprise the eutectic alloy component(s) are made by first forming coatings 54 and 56 of the respective alloy components on the respective upper surfaces of the respective lower portions 42, 44, 46 or 48 of the pads and frames, and then forming the sharp peaks 50 on the upper surfaces of the respective coatings. Since the sharp peaks 50 are formed on the upper surfaces of at least one of the respective eutectic coatings 54 or 56, the peaks are formed to consist of the same eutectic alloy component(s) comprising the upper portion of the respective pad or frame on which they are formed.
  • Another mode for carrying out the invention is illustrated in the enlarged cross sectional view of Fig. 4C. The arrangement in Fig.
  • FIG. 4C is similar to that shown in Fig. 4B, except that the sharp peaks 50 are formed first on the respective upper surfaces of the lower portions 42 or 44 and 46 or 48 of the respective pads and frames, then the coatings 54 and 56 of the eutectic alloy components are form- ed over the upper portions of the respective pads and frames, including over the sharp peaks 50 previously formed thereon.
  • the first formed sharp peaks 50 thereby form conforming sharp peaks 58 on the upper surface of the respective eutectic coating 54 and/or 56 overlying them, and accordingly, may, but need not necessarily, consist of the same eutectic alloy component(s) overlying them.
  • the sharp peaks 50 can comprise a material that is insoluble in the eutectic alloy at the soldering temperature thereof, whereby the sharp peaks 50 can act as spacers for controlling the distance between respective corresponding pairs of pads 14 and 16 and frames 20 and 22.
  • Fig. 4D Yet another possible mode for carrying out the invention is illustrated in the enlarged cross sectional view of Fig. 4D, which is similar to the arrangement in Fig. 4C, except that the sharp peaks 50 are sandwiched between a first coating 60 of the eutectic alloy component(s) comprising the upper portion of the respective pad or frame, and a second coating 62 of the same eutectic material, which is formed over the upper surfaces of the first coating 60 and the sharp peaks 50.
  • the sharp peaks 50 may, but need not necessarily, consist of the same eutectic alloy component(s) as the first and second eutectic component coatings 60 and 62.
  • first substrate or die 12 of the package 10 is soldered to and in electrical connection with the second, interconnective substrate 18 thereof, and optionally, whereby the package is simultaneously hermetically sealed, is now described in connection with Figs. 4A - 4D.
  • the respective first surfaces of the first and second substrates 12 and 18 are urged toward each other, i.e., in the directions of the respective arrows shown in Figs. 4 A - 4D, such that the upper surfaces of the respective pads 14 and 16 and frames 20 and 22 in each corresponding pair thereof are brought together in a forceful opposing abutment with each other.
  • the amount of the force required in the opposing abutment of the pads and frames will vary, depending in the materials involved and the areas of the respective features in abutment. However, in one possible mode of carrying out the invention, if the area of the respective pads and frames occupied by the sharp peaks 50 is controlled to be between about 1 to 10% of the total area thereof, then the appropriate pressure applied between the two substrates is between about 0.03 to 0.05 Newtons/mm ("N/mm ), or 4 to 7 pounds/in . ("psi").
  • the opposing pairs of pads and frames are heated to at least the soldering temperature of the particular eutectic al- loy comprising the upper portions thereof, which is typically 5-10° C above the melting temperature of the alloy. Additionally, in those embodiments in which the upper portion of one set of the pads and frames consists of only one component of the eutectic alloy, and the pads and frames in the other set comprise the full complement of eutectic components, the abutting pads and frames should be heated to between about 5-10 °C above the eutectic soldering temperature.
  • the heating is effected with a laser (not illustrated) operating in the microwave range of frequencies, and arranged to irradiate the second, or lower surface of the second substrate 18, which is relatively transparent to the radiation produced thereby, to achieve a very rapid rate of heating of the pads and frames.
  • a laser not illustrated
  • the lands 30 and the vias 32 can be offset laterally from the second pads 16 on the first surface of the interconnective substrate 18 so that they do not obscure the pads from the laser, and are thereby heated more effectively.
  • This forceful, direct contact of the eutectic components at or slightly above the soldering temperature of the eutectic alloy initiates a rapid melting and dissolution of the upper portions of the respective opposing pairs of first and second pads 14 and 16 and frames 20 and 22 into each other, commencing at the respective tips of the sharp peaks 50 or 58.
  • the pads 14 and 16 and frames 20 and 22 are cooled to cause the inter-dissolved, molten eutectic upper portions thereof to solidify into an elec- trically conductive joint between each corresponding pair of first and second pads 14 and 16, and simultaneously, into a continuous, airtight joint between the frames 20 and 22 that closes and hermetically seals the narrow space 36 inside of the frames and between the respective first surfaces of the die 14 and the interconnective substrate 18, including the active surface of the die and the electrical connec- tions between the die and the substrate.
  • MCM Multi-Chip Module

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Wire Bonding (AREA)

Abstract

L'invention porte sur un procédé d'assemblage de paquets à semi-conducteurs (10) consistant à former des paires correspondantes de plaquettes semi-conductrices (14, 16, 20, 22) sur des surfaces respectives d'une matrice (12) et un substrat d'interconnexion (18). Chaque plaquette de chaque paire comprend une portion supérieure comportant au moins un composant d'un alliage eutectique électro-conducteur. Des pics verticaux et tranchants (50, 58) sont formés sur au moins une des plaquettes de chaque paire. La matrice et le substrat sont calés par contrainte et les plaquettes sont chauffées jusqu'à ce que les pics tranchants pénètrent les films d'oxyde (52) sur les plaquettes opposées respectives de chaque paire et viennent en contact avec la surface supérieure de l'autre plaquette, ce qui permet de démarrer la fusion de plaquette. Ces plaquettes sont ensuite refroidies afin de solidifier les parties fondues dans un joint électro-conducteur entre chaque paire correspondante de plaquettes et un joint hermétique autour de la périphérie du paquet.
PCT/US2002/006183 2002-03-01 2002-03-01 Assemblage sans flux de paquets a semi-conducteurs de la taille de puce WO2003075337A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/501,431 US7098072B2 (en) 2002-03-01 2002-03-01 Fluxless assembly of chip size semiconductor packages
PCT/US2002/006183 WO2003075337A1 (fr) 2002-03-01 2002-03-01 Assemblage sans flux de paquets a semi-conducteurs de la taille de puce

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PCT/US2002/006183 WO2003075337A1 (fr) 2002-03-01 2002-03-01 Assemblage sans flux de paquets a semi-conducteurs de la taille de puce

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012120245A1 (fr) * 2011-03-10 2012-09-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Composant de connexion muni d'inserts creux
WO2018099766A1 (fr) * 2016-11-30 2018-06-07 Gottfried Wilhelm Leibniz Universität Hannover Procédé d'assemblage d'un composant semi-conducteur à une contre-partie par soudage laser et dispositif pourvu d'un composant semi-conducteur
US10556292B2 (en) 2010-08-31 2020-02-11 Nissan Motor Co., Ltd. Method for bonding aluminum-based metals

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US5938454A (en) * 1997-05-30 1999-08-17 International Business Machines Corporation Electrical connector assembly for connecting first and second circuitized substrates
US6399896B1 (en) * 2000-03-15 2002-06-04 International Business Machines Corporation Circuit package having low modulus, conformal mounting pads

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US4404453A (en) * 1981-09-10 1983-09-13 Asta, Ltd. Laser bonding of microelectronic circuits
US5900674A (en) * 1996-12-23 1999-05-04 General Electric Company Interface structures for electronic devices
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US6399896B1 (en) * 2000-03-15 2002-06-04 International Business Machines Corporation Circuit package having low modulus, conformal mounting pads

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10556292B2 (en) 2010-08-31 2020-02-11 Nissan Motor Co., Ltd. Method for bonding aluminum-based metals
WO2012120245A1 (fr) * 2011-03-10 2012-09-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Composant de connexion muni d'inserts creux
FR2972569A1 (fr) * 2011-03-10 2012-09-14 Commissariat Energie Atomique Composant de connexion muni d'inserts creux
WO2018099766A1 (fr) * 2016-11-30 2018-06-07 Gottfried Wilhelm Leibniz Universität Hannover Procédé d'assemblage d'un composant semi-conducteur à une contre-partie par soudage laser et dispositif pourvu d'un composant semi-conducteur

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