WO2003055125A1 - Dispositif a circuit de detection de signal synchrone pour systeme de communication ofdm et procede de detection pour detecter le signal synchrone de ce dispositif - Google Patents
Dispositif a circuit de detection de signal synchrone pour systeme de communication ofdm et procede de detection pour detecter le signal synchrone de ce dispositif Download PDFInfo
- Publication number
- WO2003055125A1 WO2003055125A1 PCT/CN2002/000905 CN0200905W WO03055125A1 WO 2003055125 A1 WO2003055125 A1 WO 2003055125A1 CN 0200905 W CN0200905 W CN 0200905W WO 03055125 A1 WO03055125 A1 WO 03055125A1
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- WO
- WIPO (PCT)
- Prior art keywords
- signal
- correlation
- cross
- input
- feature code
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2668—Details of algorithms
- H04L27/2673—Details of algorithms characterised by synchronisation parameters
- H04L27/2675—Pilot or known symbols
Definitions
- the invention relates to a synchronization signal detection circuit device in an OFDM (Orthogonal Frequency Division Multiplexing) communication system and a detection method for the device to detect a synchronization signal.
- OFDM Orthogonal Frequency Division Multiplexing
- Detection of synchronization signals is an important part of wireless communication systems. Performing autocorrelation on the received signal is a traditional synchronous detection method. The main problem of using auto-correlation to detect synchronization signals is the circuit scale and large power consumption. However, to address this issue,
- the problem to be solved by the present invention is to provide a device that can use the characteristic of repeated occurrence of characteristic signals in a synchronization signal and use a cross-correlation operator to detect a characteristic signal in a received signal, and use its cross-correlation operator and correlation peak detection.
- the operation of the output device realizes the detection of the synchronization signal.
- the main technical solution to the problem to be solved by the present invention is to provide a synchronous signal detection circuit device including at least a cross-correlation operator and a correlation peak detector, wherein the cross-correlation operator is an input signal A cross-correlation operator performing cross-correlation operation with a characteristic code signal, and the correlation peak detector receives a cross-correlation signal output from the cross-correlation operator and compares it with a preset gate valve voltage, and For the determination of the time interval, a correlation peak computing unit of the synchronization head is detected, and the signal output terminal of the cross-correlation computing unit is connected to the signal input terminal of the correlation peak computing unit.
- the invention also provides A detection method using the device to detect a synchronization signal, in which several formulas in the method can obtain at least accurate quantized values of short and long feature codes, thereby determining a synchronization head signal.
- the detection of the synchronization signal is achieved by using a device with a simple structure
- the special definitions and algorithms of the input and output signals through the device are used to obtain precision values of universal significance.
- FIG. 1 is a schematic structural diagram of a synchronization signal detection circuit device according to the present invention
- FIG. 2 is an embodiment of a synchronization signal detection circuit device according to the present invention
- FIG. 3 is a schematic diagram of a correlation peak output of a synchronization signal detector
- FIG. 4 is a schematic diagram of the structure of a digital-analog hybrid circuit for the cross-correlation operation of the real part of a short feature code
- FIG. 5 is a schematic diagram of a digital circuit structure for the cross-correlation operation of the real part of the short feature code
- FIG. 1 is the Short Symbol value before the quantization
- Figure 2 is the quantized Short Symbol quantized value
- Figure 3 is the Long Symbol value before quantization
- Figure 4 is the quantized Long Symbol quantized value.
- the present invention relates to a synchronization signal detection circuit device.
- the device includes at least a cross-correlation operator and a correlation peak detector.
- the cross-correlation operator is input by A cross-correlation operator that performs cross-correlation calculations between a sampling signal and a characteristic code signal.
- the correlation peak detector is configured to receive a cross-correlation signal output from the cross-correlation operator and compare it with a preset gate valve voltage to detect a synchronization head.
- Correlation peak operator, and the signal of said cross-correlation operator is The output terminal is connected to the signal input terminal of the correlation peak calculator.
- the cross-correlation operator includes at least one set of feature code real parts and feature code imaginary parts that perform cross-correlation operations with the input real part or input imaginary part, respectively, and an output of the cross-correlation operation circuit.
- the terminals are respectively connected to at least one group of adding circuits, and the input terminals of the adding circuits are connected to a square sum operation circuit, and the square sum operation circuit is connected to an input terminal of a peak detector.
- the cross-correlation operator may be a digital-analog hybrid cross-correlation operator as shown in FIG. 4, and is composed of at least one set of sampling and maintaining circuits and a set of inverting operational amplifiers.
- the cross-correlation operator may be a digital cross-correlation operator as shown in FIG. 5, and includes at least one group of sixteen parallel digital switches SWBankl and a group of sixteen parallel digital switches for controlling the sixteen parallel digital switches.
- Sixteen bit shift register SR a set of complex digital register group RegBank controlled by parallel digital switch SWBankl and connected to the input signal, the group is used to realize the multiplication of the feature code with the value of 0, 1, -1 and the input signal
- Sixteen-stage shift register pair for operation (Cx0, Cxi, x is an integer value from 0 to 15)
- the adder ADDB connected to the switch SWBank2 is configured and used to control the initial state of the sixteen bit shift register SR of the sixteen parallel digital switches SWBankl can be set to 1000000000000000; used to realize the characteristics of values 0, 1, -1
- a detection method for detecting a synchronization signal using the device includes performing a simulation on a cross-correlation operator, a feature code in a correlation peak detector, a feature code and an input sampling signal, an input analog signal, and a sample-and-hold output simulation.
- Signal, correlation peak, and calculation processing steps of the synchronization head, where the calculation formula of the synchronization head signal is: s (t) (1);
- S (t) is a synchronization signal and is composed of M characteristic signals,.
- the characteristic code signal is composed of N symbols and the formula is:
- CW represents a symbol of length T
- the feature code signal is divided into a short feature code signal and a long feature code signal, and a quantization processing formula of a real part and an imaginary part of the complex number of the short feature code signal is:
- the quantization processing formulas of the real part and imaginary part of the complex number of the long feature code signal are:
- the sync head signal is a sync head signal detected by a correlation peak detector that can continuously detect peaks and the interval between adjacent peaks is consistent with the interval length calculated by the formula.
- Figure 1 shows the structural relationship between the cross-correlation calculator and the correlation peak detector. Obviously, how to detect the synchronization signal depends on the front-end output signal of the correlation peak detector. Its working principle can also be shown in Figure 4 or Figure 5 Show it. If it is said that the synchronization signal in the received wireless signal is composed of M characteristic signals, then the values of the synchronization signal and the characteristic signal can be calculated by using equations (1) and (2). In addition, the symbol c in Equation 2 may take a real value or a complex value. When non-integer, In order to simplify the complexity of the circuit, quantization can be performed according to actual needs.
- the cross-correlation operation shown in formula (3) is performed with the symbol of the characteristic signal to obtain an output signal with a correlation peak as shown in FIG. 3.
- the time interval of the correlation peak is N x r.
- the correlation peak detector detects a correlation output signal with a higher voltage through a preset gate valve voltage. Since the correlation output of the synchronization signal includes N correlation peaks with an interval time of adjacent peaks of NT, by determining the interval time and the number of peaks of the adjacent peaks in the correlation output signal, it can be determined whether the received signal is Contains sync header signals.
- the broadband wireless local area network assumes that the synchronization signal consists of 10 short feature signals with a length of 0.8 microseconds (16 samples) and 2 short symbols with a length of 1.6 microseconds (32 samples Value).
- the formula (4) , (5) to quantify the real and imaginary parts of the fixed-point small digital element in Figure 1. The quantified results are shown in Figure 2.
- the formulas (6) and (7) are shown in Figure 3, that is, the real and imaginary parts of the fixed-point small digital elements of each long feature signal are quantized.
- the quantized values are shown in Figure 4.
- the complex cross-correlation operation shown in formula (3) is composed of four real-number cross-correlation operation circuits with similar structures. Therefore, when explaining the design method of the cross-correlation operation circuit, the cross-correlation operation of the real part of the short characteristic signal and the real part of the input signal can be used as an example to reveal the relationship between them.
- Equation (8) can be implemented using the circuit shown in FIG. 4 or FIG. 5.
- Figure 4 shows the cross-correlation operation digital-analog hybrid circuit structure.
- SH1 to SH14 in the figure represent fourteen sample-and-hold circuits
- NAMP1 and NAMP2 represent two inverting operational amplifiers
- the capacity of the capacitor is taken as a proportion in the figure.
- cross-correlation operator may be a digital cross-correlation operator as shown in FIG.
- a group of sixteen parallel digital switches SWBankl a group of sixteen bit shift registers SR for controlling sixteen parallel digital switches, a group of complex digital register groups RegBank controlled by the parallel digital switch SWBankl and connected to the input signal, a A set of sixteen-stage shift register pairs (CxO, Cxi, where x is an integer value from 0 to 15) for multiplying the feature code with the value 0, 1, -1 and the input signal, and one set with the adder
- the connected switches SWBank2, which are controlled by the shift register pair (CxO, Cxi), are a group of adders ADDB connected to the control switch SWBank2, and are used to control the sixteen shift register SR of sixteen parallel digital switches SWBank1.
- the initial state can be set to 1000000000000000; the initial state of the sixteen-stage 2-bit shift register (CxO, Cxi) for multiplying the feature code with the input signal of 0, 1, -1 can be set to (0 , 0) (1,0) (0,0) (0,0) (0,0) (1,0) (0,0) (0,0) (1,0) (0,0) (0 , 1) (0, 1) (0, 1) (0,0) (1,0) (0,0).
- the shift operation of the shift register SR and the shift register pair is controlled by a clock signal having the same frequency as the input signal.
- the above process only introduces the circuit implementation method of the cross-correlation operation between the short signature and the input signal.
- the cross-correlation operation between the long signature and the input signal only the above-mentioned integer can be used to implement the similar circuit structure.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002354167A AU2002354167A1 (en) | 2001-12-20 | 2002-12-20 | A synchronous signal detect circuit device of ofdm communication system and a detection method to detect synchronous signal of the device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN01144557.2 | 2001-12-20 | ||
CNB011445572A CN100461656C (zh) | 2001-12-20 | 2001-12-20 | 同步信号检测电路装置及其该装置检测同步信号的检测方法 |
Publications (1)
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WO2003055125A1 true WO2003055125A1 (fr) | 2003-07-03 |
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PCT/CN2002/000905 WO2003055125A1 (fr) | 2001-12-20 | 2002-12-20 | Dispositif a circuit de detection de signal synchrone pour systeme de communication ofdm et procede de detection pour detecter le signal synchrone de ce dispositif |
Country Status (3)
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CN (1) | CN100461656C (zh) |
AU (1) | AU2002354167A1 (zh) |
WO (1) | WO2003055125A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102571136A (zh) * | 2012-01-29 | 2012-07-11 | 北京航空航天大学 | 一种双路伪码捕获系统的相关峰检测方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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CN100361423C (zh) * | 2004-05-12 | 2008-01-09 | 北京信威通信技术股份有限公司 | 使用智能天线的码分多址系统中下行业务码道的同步方法 |
CN101039293B (zh) * | 2006-03-15 | 2010-06-23 | 华为技术有限公司 | 通信系统中用于初始定时同步的装置、方法及接收机 |
CN101304402B (zh) * | 2008-06-30 | 2011-08-31 | 北京海尔集成电路设计有限公司 | 一种相关峰值处理中锁定方法及其系统 |
CN101304403B (zh) * | 2008-06-30 | 2012-04-11 | 北京海尔集成电路设计有限公司 | 一种帧同步方法及系统 |
CN101345576B (zh) * | 2008-08-29 | 2012-02-29 | 芯通科技(成都)有限公司 | 一种减小td-scdma直放站开关抖动的方法及系统 |
CN103226169B (zh) * | 2012-06-12 | 2015-07-08 | 殷明 | 一种用于无线唤醒电路的方波检测器 |
CN103414676B (zh) * | 2013-07-25 | 2016-08-24 | 桂林电子科技大学 | 一种自适应自同步的tcm-mppm编码调制解调通信方法 |
Citations (3)
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WO2000077961A1 (en) * | 1999-06-15 | 2000-12-21 | Samsung Electronics Co., Ltd. | Apparatus and method for achieving symbol timing and frequency synchronization to orthogonal frequency division multiplexing signal |
EP1089510A2 (en) * | 1999-09-30 | 2001-04-04 | Hitachi Denshi Kabushiki Kaisha | Data transmission method and apparatus utilising an OFDM system |
CN1309484A (zh) * | 2000-02-16 | 2001-08-22 | 汤姆森特许公司 | 正交频分多路复用系统中取样偏移校正 |
Family Cites Families (2)
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US6226336B1 (en) * | 1998-02-20 | 2001-05-01 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and apparatus for detecting a frequency synchronization signal |
JP3606761B2 (ja) * | 1998-11-26 | 2005-01-05 | 松下電器産業株式会社 | Ofdm受信装置 |
-
2001
- 2001-12-20 CN CNB011445572A patent/CN100461656C/zh not_active Expired - Fee Related
-
2002
- 2002-12-20 WO PCT/CN2002/000905 patent/WO2003055125A1/zh not_active Application Discontinuation
- 2002-12-20 AU AU2002354167A patent/AU2002354167A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000077961A1 (en) * | 1999-06-15 | 2000-12-21 | Samsung Electronics Co., Ltd. | Apparatus and method for achieving symbol timing and frequency synchronization to orthogonal frequency division multiplexing signal |
EP1089510A2 (en) * | 1999-09-30 | 2001-04-04 | Hitachi Denshi Kabushiki Kaisha | Data transmission method and apparatus utilising an OFDM system |
CN1309484A (zh) * | 2000-02-16 | 2001-08-22 | 汤姆森特许公司 | 正交频分多路复用系统中取样偏移校正 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102571136A (zh) * | 2012-01-29 | 2012-07-11 | 北京航空航天大学 | 一种双路伪码捕获系统的相关峰检测方法 |
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AU2002354167A1 (en) | 2003-07-09 |
CN100461656C (zh) | 2009-02-11 |
CN1427564A (zh) | 2003-07-02 |
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