WO2003046977A3 - Tranchee d'isolation destinee a un circuit integre et procede de fabrication de cette tranchee - Google Patents

Tranchee d'isolation destinee a un circuit integre et procede de fabrication de cette tranchee Download PDF

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Publication number
WO2003046977A3
WO2003046977A3 PCT/EP2002/012838 EP0212838W WO03046977A3 WO 2003046977 A3 WO2003046977 A3 WO 2003046977A3 EP 0212838 W EP0212838 W EP 0212838W WO 03046977 A3 WO03046977 A3 WO 03046977A3
Authority
WO
WIPO (PCT)
Prior art keywords
insulation trench
production
integrated circuit
insulation
trench
Prior art date
Application number
PCT/EP2002/012838
Other languages
German (de)
English (en)
Other versions
WO2003046977A2 (fr
Inventor
Martin Schrems
Original Assignee
Austriamicrosystems Ag
Martin Schrems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Austriamicrosystems Ag, Martin Schrems filed Critical Austriamicrosystems Ag
Priority to EP02799043A priority Critical patent/EP1449246A2/fr
Priority to AU2002364274A priority patent/AU2002364274A1/en
Publication of WO2003046977A2 publication Critical patent/WO2003046977A2/fr
Publication of WO2003046977A3 publication Critical patent/WO2003046977A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

L'invention concerne une tranchée d'isolation (1) destinée à un circuit intégré, formée dans un substrat (2) et remplie d'un milieu d'isolation (7) présentant une constante diélectrique relative faible. Sur le côté supérieur, la tranchée d'isolation (1) est fermé au moyen d'un capot (12) de manière que le milieu d'isolation (7) soit entièrement encapsulé. L'invention concerne également une tranchée d'isolation en forme de bouteille, ainsi qu'un procédé de fabrication d'une tranchée d'isolation.
PCT/EP2002/012838 2001-11-27 2002-11-15 Tranchee d'isolation destinee a un circuit integre et procede de fabrication de cette tranchee WO2003046977A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP02799043A EP1449246A2 (fr) 2001-11-27 2002-11-15 Tranchee d'isolation destinee a un circuit integre et procede de fabrication de cette tranchee
AU2002364274A AU2002364274A1 (en) 2001-11-27 2002-11-15 Insulation trench for an integrated circuit and method for production thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2001157785 DE10157785A1 (de) 2001-11-27 2001-11-27 Isolationsgraben für eine intergrierte Schaltung und Verfahren zu dessen Herstellung
DE10157785.0 2001-11-27

Publications (2)

Publication Number Publication Date
WO2003046977A2 WO2003046977A2 (fr) 2003-06-05
WO2003046977A3 true WO2003046977A3 (fr) 2004-02-12

Family

ID=7706915

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/012838 WO2003046977A2 (fr) 2001-11-27 2002-11-15 Tranchee d'isolation destinee a un circuit integre et procede de fabrication de cette tranchee

Country Status (4)

Country Link
EP (1) EP1449246A2 (fr)
AU (1) AU2002364274A1 (fr)
DE (1) DE10157785A1 (fr)
WO (1) WO2003046977A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10345345A1 (de) 2003-09-19 2005-04-14 Atmel Germany Gmbh Verfahren zur Herstellung von Halbleiterbauelementen in einem Halbleitersubstrat
DE10345346B4 (de) 2003-09-19 2010-09-16 Atmel Automotive Gmbh Verfahren zur Herstellung eines Halbleiterbauelements mit aktiven Bereichen, die durch Isolationsstrukturen voneinander getrennt sind
DE10348021A1 (de) * 2003-10-15 2005-05-25 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterstruktur mit einer Einkapselung einer Füllung, welche zum Anfüllen von Gräben verwendet wird
US7935602B2 (en) * 2005-06-28 2011-05-03 Micron Technology, Inc. Semiconductor processing methods
US7422960B2 (en) 2006-05-17 2008-09-09 Micron Technology, Inc. Method of forming gate arrays on a partial SOI substrate
US7537994B2 (en) 2006-08-28 2009-05-26 Micron Technology, Inc. Methods of forming semiconductor devices, assemblies and constructions
US7939403B2 (en) 2006-11-17 2011-05-10 Micron Technology, Inc. Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells
US9263455B2 (en) 2013-07-23 2016-02-16 Micron Technology, Inc. Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0540262A2 (fr) * 1991-10-31 1993-05-05 STMicroelectronics, Inc. Isolation à ramure
DE19856805A1 (de) * 1997-12-13 1999-06-24 Lg Semicon Co Ltd Grabenisolierstruktur und Verfahren zu ihrer Herstellung
US5972758A (en) * 1997-12-04 1999-10-26 Intel Corporation Pedestal isolated junction structure and method of manufacture
EP1043769A1 (fr) * 1999-04-07 2000-10-11 STMicroelectronics S.r.l. Procédé pour la production d'une plaquette en matériau semi-conducteur comportant des régions monocristallines séparées par des régions de materiau isolant, notamment pour la fabrication de dispositifs de puissance intégrés, et plaquette ainsi obtenue
US6140691A (en) * 1997-12-19 2000-10-31 Advanced Micro Devices, Inc. Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate
US6150212A (en) * 1999-07-22 2000-11-21 International Business Machines Corporation Shallow trench isolation method utilizing combination of spacer and fill
US6214696B1 (en) * 1998-04-22 2001-04-10 Texas Instruments - Acer Incorporated Method of fabricating deep-shallow trench isolation

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4106050A (en) * 1976-09-02 1978-08-08 International Business Machines Corporation Integrated circuit structure with fully enclosed air isolation
US5098856A (en) * 1991-06-18 1992-03-24 International Business Machines Corporation Air-filled isolation trench with chemically vapor deposited silicon dioxide cap
JPH05299498A (ja) * 1991-06-22 1993-11-12 Takehide Shirato 半導体装置
KR100242466B1 (ko) * 1996-06-27 2000-02-01 김영환 채널스탑이온주입에 따른 좁은폭효과 방지를 위한 소자분리 구조를 갖는 반도체장치 및 그 제조방법
KR100234408B1 (ko) * 1997-02-17 1999-12-15 윤종용 반도체장치의 소자분리방법
US5915192A (en) * 1997-09-12 1999-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming shallow trench isolation
KR100252866B1 (ko) * 1997-12-13 2000-04-15 김영환 반도체소자 및 이의 제조방법
US6251734B1 (en) * 1998-07-01 2001-06-26 Motorola, Inc. Method for fabricating trench isolation and trench substrate contact
US6268637B1 (en) * 1998-10-22 2001-07-31 Advanced Micro Devices, Inc. Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication
US6144086A (en) * 1999-04-30 2000-11-07 International Business Machines Corporation Structure for improved latch-up using dual depth STI with impurity implant
US6833079B1 (en) * 2000-02-17 2004-12-21 Applied Materials Inc. Method of etching a shaped cavity

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0540262A2 (fr) * 1991-10-31 1993-05-05 STMicroelectronics, Inc. Isolation à ramure
US5972758A (en) * 1997-12-04 1999-10-26 Intel Corporation Pedestal isolated junction structure and method of manufacture
DE19856805A1 (de) * 1997-12-13 1999-06-24 Lg Semicon Co Ltd Grabenisolierstruktur und Verfahren zu ihrer Herstellung
US6140691A (en) * 1997-12-19 2000-10-31 Advanced Micro Devices, Inc. Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate
US6214696B1 (en) * 1998-04-22 2001-04-10 Texas Instruments - Acer Incorporated Method of fabricating deep-shallow trench isolation
EP1043769A1 (fr) * 1999-04-07 2000-10-11 STMicroelectronics S.r.l. Procédé pour la production d'une plaquette en matériau semi-conducteur comportant des régions monocristallines séparées par des régions de materiau isolant, notamment pour la fabrication de dispositifs de puissance intégrés, et plaquette ainsi obtenue
US6150212A (en) * 1999-07-22 2000-11-21 International Business Machines Corporation Shallow trench isolation method utilizing combination of spacer and fill

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1449246A2 *

Also Published As

Publication number Publication date
AU2002364274A1 (en) 2003-06-10
WO2003046977A2 (fr) 2003-06-05
AU2002364274A8 (en) 2003-06-10
EP1449246A2 (fr) 2004-08-25
DE10157785A1 (de) 2003-06-12

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