WO2003043088A1 - Dispositif de memoire - Google Patents

Dispositif de memoire Download PDF

Info

Publication number
WO2003043088A1
WO2003043088A1 PCT/JP2002/011804 JP0211804W WO03043088A1 WO 2003043088 A1 WO2003043088 A1 WO 2003043088A1 JP 0211804 W JP0211804 W JP 0211804W WO 03043088 A1 WO03043088 A1 WO 03043088A1
Authority
WO
WIPO (PCT)
Prior art keywords
mosfet
memory
potential
memory device
gate electrode
Prior art date
Application number
PCT/JP2002/011804
Other languages
English (en)
French (fr)
Inventor
Tetsuya Uemura
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to US10/495,000 priority Critical patent/US20040262656A1/en
Priority to EP02788611A priority patent/EP1453095A1/en
Publication of WO2003043088A1 publication Critical patent/WO2003043088A1/ja

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/JP2002/011804 2001-11-12 2002-11-12 Dispositif de memoire WO2003043088A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/495,000 US20040262656A1 (en) 2001-11-12 2002-11-12 Memory device
EP02788611A EP1453095A1 (en) 2001-11-12 2002-11-12 Memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-345551 2001-11-12
JP2001345551A JP4336758B2 (ja) 2001-11-12 2001-11-12 メモリ装置

Publications (1)

Publication Number Publication Date
WO2003043088A1 true WO2003043088A1 (fr) 2003-05-22

Family

ID=19158869

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/011804 WO2003043088A1 (fr) 2001-11-12 2002-11-12 Dispositif de memoire

Country Status (6)

Country Link
US (1) US20040262656A1 (ja)
EP (1) EP1453095A1 (ja)
JP (1) JP4336758B2 (ja)
KR (1) KR20050044397A (ja)
CN (1) CN1586007A (ja)
WO (1) WO2003043088A1 (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7633162B2 (en) * 2004-06-21 2009-12-15 Sang-Yun Lee Electronic circuit with embedded memory
US7548455B2 (en) 2006-05-05 2009-06-16 Rochester Institute Of Technology Multi-valued logic/memory cells and methods thereof
KR101162729B1 (ko) * 2007-07-30 2012-07-05 삼성전자주식회사 전기장센서의 센싱감도향상방법, 전기장 센서를 채용한저장장치, 및 그 정보재생방법
US8054673B2 (en) * 2009-04-16 2011-11-08 Seagate Technology Llc Three dimensionally stacked non volatile memory units
US9230641B2 (en) 2013-03-15 2016-01-05 Rambus Inc. Fast read speed memory device
US11984163B2 (en) 2013-03-15 2024-05-14 Hefei Reliance Memory Limited Processing unit with fast read speed memory device
CN106847750B (zh) * 2017-01-19 2020-04-03 上海宝芯源功率半导体有限公司 一种用于锂电保护的开关器件及其制作方法
CN109979843B (zh) * 2019-04-09 2021-04-13 德淮半导体有限公司 用于校验版图中的图案偏移的装置和方法
CN113629013B (zh) * 2021-07-01 2024-03-15 芯盟科技有限公司 一种存储器件的制造方法及存储器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02116162A (ja) * 1988-10-25 1990-04-27 Nec Corp 半導体記憶装置
US5536674A (en) * 1992-12-11 1996-07-16 Motorola, Inc. Process for forming a static-random-access memory cell
US5543652A (en) * 1992-08-10 1996-08-06 Hitachi, Ltd. Semiconductor device having a two-channel MISFET arrangement defined by I-V characteristic having a negative resistance curve and SRAM cells employing the same
US5917247A (en) * 1995-03-31 1999-06-29 Nec Corporation Static type memory cell structure with parasitic capacitor
JP2001068632A (ja) * 1999-08-25 2001-03-16 Mitsubishi Electric Corp 半導体記憶装置および製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5535156A (en) * 1994-05-05 1996-07-09 California Institute Of Technology Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same
US5883829A (en) * 1997-06-27 1999-03-16 Texas Instruments Incorporated Memory cell having negative differential resistance devices
US6104631A (en) * 1997-12-17 2000-08-15 National Scientific Corp. Static memory cell with load circuit using a tunnel diode

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02116162A (ja) * 1988-10-25 1990-04-27 Nec Corp 半導体記憶装置
US5543652A (en) * 1992-08-10 1996-08-06 Hitachi, Ltd. Semiconductor device having a two-channel MISFET arrangement defined by I-V characteristic having a negative resistance curve and SRAM cells employing the same
US5536674A (en) * 1992-12-11 1996-07-16 Motorola, Inc. Process for forming a static-random-access memory cell
US5917247A (en) * 1995-03-31 1999-06-29 Nec Corporation Static type memory cell structure with parasitic capacitor
JP2001068632A (ja) * 1999-08-25 2001-03-16 Mitsubishi Electric Corp 半導体記憶装置および製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
VAN DER WAGT J.P.A. ET AL.: "RTD/HFET low standby power SRAM gain cell", IEEE ELECTRON DEVICE LETTERS, vol. 19, no. 1, 1998, pages 7 - 9, XP002961099 *

Also Published As

Publication number Publication date
US20040262656A1 (en) 2004-12-30
JP2003152109A (ja) 2003-05-23
KR20050044397A (ko) 2005-05-12
CN1586007A (zh) 2005-02-23
JP4336758B2 (ja) 2009-09-30
EP1453095A1 (en) 2004-09-01

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