WO2003032701A1 - Procede de fabrication d'une plaquette de circuit multicouche et plaquette de circuit multicouche obtenue par ce procede - Google Patents

Procede de fabrication d'une plaquette de circuit multicouche et plaquette de circuit multicouche obtenue par ce procede Download PDF

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Publication number
WO2003032701A1
WO2003032701A1 PCT/JP2001/008610 JP0108610W WO03032701A1 WO 2003032701 A1 WO2003032701 A1 WO 2003032701A1 JP 0108610 W JP0108610 W JP 0108610W WO 03032701 A1 WO03032701 A1 WO 03032701A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
resin
metal adhesion
wiring board
insulating layer
Prior art date
Application number
PCT/JP2001/008610
Other languages
English (en)
Japanese (ja)
Inventor
Motoaki Tani
Nobuyuki Hayashi
Tomoyuki Abe
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2001/008610 priority Critical patent/WO2003032701A1/fr
Priority to JP2003535517A priority patent/JPWO2003032701A1/ja
Publication of WO2003032701A1 publication Critical patent/WO2003032701A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0264—Peeling insulating layer, e.g. foil, or separating mask
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor

Definitions

  • the present invention relates to a method for manufacturing a multilayer wiring board used in a circuit system of an electric / electronic device, and a multilayer wiring board manufactured by the method.
  • a wiring layer is buried between a plurality of insulating layers, and each wiring layer is electrically connected to a via hole formed in the insulating layer.
  • a method of forming a via hole a method of forming a hole in the insulating layer by photolithography using a photosensitive resin, a method of forming a hole by irradiating a laser, and the like are employed.
  • a conductive material is formed on the insulating layer by electroless plating or electroplating, and this is etched to form a wiring pattern.
  • a series of steps from the formation of the insulating layer to the formation of the wiring pattern are repeated a predetermined number of times, whereby the circuit can be multilayered, and the degree of integration of the circuit is increased. Can be.
  • the surface of the insulating layer is roughened and wiring is performed on the insulating layer with some unevenness.
  • the layers were formed in layers. More specifically, the surface of the outermost insulating resin layer is immersed sequentially in a swelling liquid, a roughening liquid, and a neutralizing liquid to form irregularities of about 5 ⁇ . Electroless copper plating and electrolytic copper plating were sequentially performed to form a copper wiring layer. By doing so, the distance between the luster layer and the copper wiring layer is increased. In the above, adhesion was obtained by a physical anchor effect.
  • Japanese Patent Application Laid-Open Nos. Hei 55-11-198, Hei 10-245 559, Hei 11-6380 also disclose an insulating layer as an insulating layer. For this purpose, there is disclosed a technique aiming at good lamination formation.
  • the surface of the insulating layer is roughened to a certain degree, and the adhesion is improved by a physical anchor effect at the joint surface between the insulating layer and the wiring layer.
  • the surface is roughened to a conventional average roughness of about 5 ⁇ , the wiring with a smaller contact area tends to have lower adhesion to the insulating layer, which hinders finer wiring. In some cases. Therefore, regarding the adhesion of the wiring layer to the insulating layer in a multilayer wiring board having a build-up wiring structure, the 90-degree peel test described above was performed while suppressing the roughening of the insulating layer to such an extent as not to hinder the finer wiring. It is required to achieve a peel strength of 1 kg / cm or more. Disclosure of the invention
  • the present invention has been conceived under such circumstances, and has a method for manufacturing a multilayer substrate in which an insulating layer and a wiring layer are provided with a high level of adhesion and adhesion. It is an object to provide a multilayer wiring board manufactured by this.
  • a method for manufacturing a multilayer wiring board having a laminated structure including an insulating layer and a wiring layer comprises the steps of attaching a support film provided with a metal adhesion layer to an insulating layer via the metal adhesion layer, and removing the support film while transferring the metal adhesion layer to the insulation layer. Forming a resist pattern on the metal adhesion layer, forming a wiring layer by providing a plating film in a non-mask region of the resist pattern, and removing the resist pattern so that the wiring pattern is not covered with the wiring pattern. And removing the metal adhesion layer. According to such a configuration, the adhesion of the wiring layer to the insulating layer can be increased.
  • a wiring layer is formed on an insulating layer via a metal adhesion layer made of a metal material having a relatively high adhesion to an insulating layer made of a resin material and a wiring layer made of a metal material.
  • the metal adhesion layer is laminated on the insulating layer by laminating a support film provided with the metal adhesion layer to the insulating layer via the metal adhesion layer. This bonding step can be performed under a condition in which the insulating layer is pressurized by, for example, a vacuum press or a vacuum laminate.
  • the metal adhesion layer can be formed in a stronger bonding state with the insulating layer than when the metal adhesion layer is formed by a plating technique or the like.
  • the adhesion of the wiring layer to the insulating layer is also improved via the metal adhesion layer.
  • sufficient adhesion can be obtained while suppressing the degree of surface roughening to such an extent that wiring fineness is not hindered. As a result, an excellent fine wiring structure can be formed on the multilayer wiring board.
  • a second aspect of the present invention there is provided another method for manufacturing a multilayer wiring board having a laminated structure including an insulating layer and a wiring layer.
  • This method comprises the steps of: bonding a support film provided with a metal adhesion layer to an insulating layer via the metal adhesion layer; removing the support film while transferring the metal adhesion layer to the insulation layer; Forming a via hole in the insulating layer and the metal adhesion layer laminated thereon; forming a resist pattern on the metal adhesion layer; and providing a plating film in a non-mask region of the resist pattern to form a metal.
  • the method includes a step of forming a wiring layer on the adhesion layer and forming a via in the via hole, and a step of removing the resist pattern and removing a metal adhesion layer not covered by the wiring layer.
  • the same effect as described above with respect to the first aspect of the present invention is exerted on the adhesion of the wiring layer to the insulating layer.
  • the metal adhesion layer is not formed in the via hole, even when a material having low conductivity is used for the metal adhesion layer, the electric connection between the wiring layers is appropriately performed. Can be achieved.
  • the support film is pressed against the insulating layer.
  • the step of laminating the support film is performed under heating. Do. With such a configuration, the step of attaching the support film to the insulating layer can be performed more favorably.
  • the insulating layer contains a thermosetting resin
  • the insulating layer in the step of bonding the support film is in a state before being completely cured, and further includes a step of curing the insulating layer after bonding the support film.
  • the method further includes a step of forming an electroless plating film on the metal adhesion layer using a metal selected from the group consisting of copper, nickel, and cobalt.
  • a step of providing a plating film, which is performed later, can be performed by the electroplating technique on the electroless plating.
  • a multilayer wiring board having a laminated structure including an insulating layer and a wiring layer and a via for electrically connecting the wiring layers.
  • the wiring layer is formed by a metal film laminated on an insulating layer via a metal adhesion layer, and the metal film enters a via hole formed in the insulating layer to form a via, and The adhesion layer does not enter the via hole.
  • the metal adhesion layer includes a metal selected from the group consisting of chromium, titanium, nickel, cobalt, and zinc. These metals can improve the adhesion of the conductor material forming the wiring layer to the resin material forming the insulating layer.
  • the metal adhesion layer is provided at a coverage of 10 to 100% with respect to the insulating layer.
  • the metal adhesion layer has a thickness of 0.01 to 1. ⁇ . As a result, the thinning of the wiring structure or the multilayer wiring board is ensured.
  • the insulating layer comprises a polyimide resin, an epoxy resin, a maleimide resin, a bismaleimide resin, a cyanate resin, a polyphenylene ether resin, a polyphenylene oxide resin, an olefin resin, and a fluorine-containing resin. Including resin selected from the group.
  • the support film has an average surface roughness of 5 m or less. In a conventional multilayer wiring board, the average surface roughness of the insulating layer in contact with the wiring layer is relatively high from the viewpoint of improving the adhesion between the insulating layer and the wiring layer. Had been around.
  • the adhesion of the wiring layer to the insulating layer was ensured by such high surface roughness, that is, the anchor effect based on the unevenness of the surface.
  • the metal adhesion formed on the insulating layer by the bonding of the support fills is performed. With the interposition of the layer, the adhesion of the wiring layer to the insulating layer can be improved.
  • FIG. 1 is a sectional view of a multilayer wiring board according to the present invention.
  • FIG. 3 a to FIG. 3 d show steps subsequent to FIG. 2 d.
  • FIG. 1 is a partial cross-sectional view of a multilayer wiring board 1 according to the present invention.
  • the multilayer wiring board 1 includes a core board 10, insulating resin layers 20 and 30 laminated thereon, and a wiring layer 40 embedded between the insulating resin layer 20 and the insulating resin layer 30. And a metal adhesion layer 50 interposed between the wiring layer 40 and the insulating resin layer 20.
  • the core substrate 10 is made of a glass cloth impregnated with a resin, and a plurality of pre-predaders in which the resin is in a B-stage state are used. On the surface, an inner wiring pattern 11 is formed by copper. ing.
  • the wiring layer 40 is formed by patterning on the insulating resin layer 20 and includes an electroless copper plating layer 41 and an electric copper plating layer 42.
  • the metal adhesion layer 50 has a thickness of 0.01 to 1.0 ⁇ and is interposed between the insulating layer 20 and the wiring layer 40 so that the wiring layer 40 adheres to the insulating layer 20. It contributes to improved performance.
  • Examples of a material for forming the metal adhesion layer 50 include, for example, Chromium, titanium, nickel, cobalt, and zinc can be used.
  • the wiring layer 40 and the inner wiring pattern 11 are electrically connected via the via 40a formed in the via hole 20a. No metal adhesion layer 50 is formed in the via hole 20a.
  • FIG. 2A to 4D show steps for manufacturing the multilayer wiring board 1 shown in FIG.
  • a metal adhesion layer 50 is formed on the surface of the support film 60.
  • a support film 60 having an average surface unevenness of 5 ⁇ m or less is prepared, and a wet process such as a chromate treatment or a plating process or a dry process such as a sputtering method or a vacuum deposition method is applied to the surface.
  • a metal adhesion layer 50 is formed with a thickness of 0.01 to 1.0 ⁇ .
  • a metal film such as a copper foil and an aluminum foil, or a film composed of an alkali-soluble resin may be used.
  • the alkali-soluble resin include an acrylic resin often used for a dry film resist and the like, preferably an acrylic resin having a hydroxyl group.
  • an uncured insulating resin film serving as an insulating layer 20 of the multilayer wiring board 1 is placed on the core board 10 on which the inner wiring pattern 11 has already been formed. Then, the support film 60 on which the metal adhesion layer 50 is formed is overlaid and bonded so that the metal adhesion layer 50 is in contact with the insulating resin film 20. At this time, depending on the properties of the resin material constituting the insulating resin film 20, the bonding step may be performed under heating, or the support film 60 may be pressed against the insulating resin film 20. . When the bonding step is performed under heating, the insulating resin film 20 may be solidified or cured by the heating to form the insulating resin layer 20 together.
  • a heating step for solidifying or curing the insulating resin film 20 is performed to form the insulating resin layer 20.
  • Materials for forming the insulating resin layer 20 include, for example, polyimide resin, epoxy resin, maleimide, luster, bismaleide, cyanate, polyphenylene ether resin, and polyphenylene ether resin.
  • a phenylene oxide resin, an olefin resin, a fluorine-containing resin, or the like can be used.
  • FIG. 2D only the support film 60 is removed by etching or the like while leaving the metal adhesion layer 50. Thereby, the metal adhesion layer 50 is uniformly transferred to the insulating resin layer 20.
  • the covering ratio of the metal adhesion layer 50 to the insulating resin layer 20 is 10 to 100%.
  • a via hole 20a is formed in a predetermined portion of the insulating resin layer 20.
  • a carbon dioxide gas laser, an excimer laser, or a UV-YAG laser can be employed as a means for forming the via hole 20a.
  • an electroless copper plating layer 41 having a thickness of 0.3 Aim is formed by performing an electroless copper plating process from above the metal adhesion layer 50.
  • the metal adhesion layer 50 does not cover the entire surface of the insulating resin layer 20! / Even if this is the case, the electroless copper plating layer 41 formed by this electroless copper plating process is insulated.
  • the entire surface of the resin layer 20 is covered, and functions as a current-carrying layer in an electric plating process in a later step.
  • the metal adhesion layer 50 can function as a conductive layer.
  • a resist pattern 70 is formed on the electroless copper plating layer 41.
  • a photoresist is laminated on the electroless copper plating layer 41, and the photoresist is patterned by exposure and a phenomenon corresponding to a desired wiring pattern.
  • the photoresist for example, NIT-240 (produced by Nichigo Morton), RY-340 (produced by Hitachi Chemical), or the like can be used.
  • an electrolytic copper plating process is performed using the electroless copper plating film 41 as a current-carrying layer.
  • an electrolytic copper plating layer 42 having a thickness of 10 ⁇ is deposited and grown on the non-mask region of the resist pattern 70.
  • the resist pattern 70 is peeled off.
  • a sodium hydroxide aqueous solution or an organic amine-based aqueous solution can be used as the stripping solution.
  • the electroless copper plating film 41 not covered with the electrolytic copper plating layer 42 and the metal adhesion layer 50 thereunder are removed.
  • the electroless copper plating film 41 is removed by etching using, for example, a mixed aqueous solution of hydrogen peroxide and sulfuric acid or an aqueous cupric chloride solution. Etching is removed using a cerium nitrate ammonium aqueous solution or the like.
  • the wiring layer 40 including the metal layer 41 and the copper electroplating layer 42 is formed on the insulating resin layer 20 via the metal adhesion layer 50.
  • an insulating resin layer 30 is formed on the insulating resin layer 20 from above the wiring layer 40. As a result, the multilayer wiring board 1 shown in FIG. 1 is formed.
  • FIG. 4D shows a multilayer wiring board in which the above-described series of steps from the transfer of the metal adhesion layer 50 to the insulating resin layer 20 to the formation of the wiring layer 40 are repeated. In this way, a desired number of layers can be achieved by repeating the series of steps a predetermined number of times.
  • examples of the present invention will be described together with comparative examples.
  • the surface of copper foil (thickness: 18 / m, average surface roughness: 1 / m) as a support film was subjected to chromate treatment to form a chromium adhesion layer as a metal adhesion layer.
  • a thermoplastic polyimide film film thickness: 35 / m, trade name: ESPANEX, Nippon Steel Chemical Co., Ltd.
  • the above-mentioned copper foil with a chromium adhesion layer is overlaid so that the chromium adhesion layer and polyimide are in contact with each other.
  • the peel strength of the copper plating film on the sample substrate obtained as described above was measured.
  • the copper plating film in this example exhibited a peel strength of 1.2 kgf Zcm with respect to the thermoplastic polyimide.
  • the average surface roughness was 1; ⁇ .
  • a sample substrate was produced in the same manner as in Example 1 except that a copper foil having an average surface roughness of 5 ⁇ was used instead of a copper foil having an average surface roughness of 1; / m as a supporting film.
  • the peel strength of the copper plating film on this sample substrate was measured in the same manner as in Example 1.
  • the copper-plated film in this example exhibited a peel strength of 1.2 kgf Zcm, which was equivalent to that in Example 1.
  • Example 1 was repeated except that only the thermoplastic polyimide film was cured by vacuum pressing without forming a chromium adhesion layer as a metal adhesion layer, and electroless copper plating and electrolytic copper plating were applied thereon. In the same manner, the production of a sample substrate was attempted. Then, the copper plating film was peeled off from the polyimide surface during electrolytic copper plating. Therefore, it was not possible to measure the peel strength.
  • a 0.2 / m-thick titanium layer is formed by sputtering, and a metal adhesion layer is formed.
  • a titanium adhesion layer is formed on the surface of an aluminum foil (thickness: 25 // ⁇ , average surface roughness: 2 ⁇ m) as a support film.
  • a semi-cured thermosetting epoxy resin sheet (thickness: 50 ⁇ m, trade name: SH-9, made by Ajinomoto Co.)
  • the tan adhesion layer and the epoxy resin sheet were stacked so as to be in contact with each other, and were laminated by vacuum lamination at a temperature of 130 ° C. and a pressure of IMP a for 3 minutes. Thereafter, the insulating resin layer was taken out of the vacuum laminate and heated at 170 ° C. for 1 hour under atmospheric pressure to cure the insulating resin layer.
  • the aluminum foil was removed by etching with hydrochloric acid, leaving only the titanium adhesion layer on the surface of the insulating resin layer.
  • an electroless copper plating film (thickness: 0.3 ⁇ ) is formed on the entire surface of the titanium adhesion layer, and an electrolytic copper plating film (thickness: 30 / zm) is formed thereon.
  • a copper-plated film as a wiring layer was formed.
  • the copper plating film was cut into 1 cm width. Thus, a sample substrate was manufactured.
  • the peel strength of the copper-plated film on the sampnole substrate obtained as described above was measured.
  • the copper plating film in this example exhibited a peel strength of 1.0 kgf / cm with respect to the thermosetting epoxy resin.
  • Examination of the surface roughness of the peeled surface of the copper plating film peeled due to excessive load revealed that the average surface roughness was 2 ⁇ .
  • the surface of a copper foil (thickness: 18 ⁇ , average surface roughness: ⁇ ) as a support film was subjected to a chromate treatment to form a chromium adhesion layer as a metal adhesion layer.
  • a copper-clad resin substrate 100 x 100 x 1.6 mm, manufactured by Mitsubishi Gas Chemical
  • a thermoplastic polyimide film film thickness: 25 m, as an insulating resin layer
  • PIXIO manufactured by Kanegabuchi Chemical Industry Co., Ltd.
  • Lamination was performed under a pressure of 0.5 MPa for 3 minutes. Then, it was removed from the vacuum laminate and heated at 210 ° C. for 30 minutes under atmospheric pressure to cure the insulating resin layer. Next, the copper foil was removed by etching with an aqueous cupric chloride solution, leaving only the chromium adhesion layer on the surface of the insulating resin layer. Next, a via hole of ⁇ 80 ⁇ m was formed in the insulating resin layer using a carbon dioxide gas laser. Then Electroless copper plating was performed on the chromium adhesion layer to form a current-carrying layer.
  • a photoresist (trade name: NIT-250, manufactured by Nichigo Morton) was formed on the current-carrying layer, and the film was patterned to form a resist pattern.
  • An electrolytic copper plating layer having a thickness of 30 jam was deposited and grown on the non-mask region of the resist pattern, and then the resist pattern was peeled off.
  • the current-carrying layer not covered with the electrolytic copper plating layer is removed by etching with a mixed solution of hydrogen peroxide and sulfuric acid. Subsequently, the chromium adhesion layer, which is also exposed, is removed with a ceric ammonium nitrate aqueous solution.
  • a wiring layer was formed on the insulating resin layer via the chromium adhesion layer. As a result, a fine wiring structure having a wiring width of 30 / m with high adhesion to the insulating resin layer could be formed.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

plaquette de circuit multicouche (1) comportant une structure stratifiée avec couches isolantes (20, 30) et couche de câblage (40). Le procédé de fabrication du substrat de câblage multicouche (1) consiste à : coller sur la couche isolante (20) un film support par l'intermédiaire de la couche de contact métallique (50) de ce film ; retirer le film support tout en transférant la couche de contact métallique (50) sur la couche isolante (20) ; former la couche de câblage (40) en créant un motif de réserve sur la couche de contact métallique (50) ; former un film de plaquage sur une région non masquée du motif de réserve ; et retirer le motif de réserve et la couche de contact métallique (50) qui n'est pas recouverte par la couche de câblage.
PCT/JP2001/008610 2001-09-28 2001-09-28 Procede de fabrication d'une plaquette de circuit multicouche et plaquette de circuit multicouche obtenue par ce procede WO2003032701A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2001/008610 WO2003032701A1 (fr) 2001-09-28 2001-09-28 Procede de fabrication d'une plaquette de circuit multicouche et plaquette de circuit multicouche obtenue par ce procede
JP2003535517A JPWO2003032701A1 (ja) 2001-09-28 2001-09-28 多層配線基板の製造方法およびこれにより製造される多層配線基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2001/008610 WO2003032701A1 (fr) 2001-09-28 2001-09-28 Procede de fabrication d'une plaquette de circuit multicouche et plaquette de circuit multicouche obtenue par ce procede

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Publication Number Publication Date
WO2003032701A1 true WO2003032701A1 (fr) 2003-04-17

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005150211A (ja) * 2003-11-12 2005-06-09 Hitachi Chem Co Ltd 多層配線板およびその製造方法
JP2009182118A (ja) * 2008-01-30 2009-08-13 Shinko Electric Ind Co Ltd 配線基板の製造方法
WO2018153760A1 (fr) 2017-02-22 2018-08-30 CHT Germany GmbH Formulation aqueuse pour améliorer la résistance à l'abrasion
CN113348733A (zh) * 2019-01-11 2021-09-03 斯天克有限公司 多层基板及其制造方法
US20220128865A1 (en) * 2020-10-26 2022-04-28 Lg Display Co., Ltd. Printed Circuit, Backlight Unit and Display Device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273458A (ja) * 1994-03-31 1995-10-20 Hitachi Chem Co Ltd 多層配線板の製造法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273458A (ja) * 1994-03-31 1995-10-20 Hitachi Chem Co Ltd 多層配線板の製造法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005150211A (ja) * 2003-11-12 2005-06-09 Hitachi Chem Co Ltd 多層配線板およびその製造方法
JP2009182118A (ja) * 2008-01-30 2009-08-13 Shinko Electric Ind Co Ltd 配線基板の製造方法
WO2018153760A1 (fr) 2017-02-22 2018-08-30 CHT Germany GmbH Formulation aqueuse pour améliorer la résistance à l'abrasion
CN113348733A (zh) * 2019-01-11 2021-09-03 斯天克有限公司 多层基板及其制造方法
JP2022517011A (ja) * 2019-01-11 2022-03-03 ステムコ カンパニー リミテッド 多層基板およびその製造方法
US20220128865A1 (en) * 2020-10-26 2022-04-28 Lg Display Co., Ltd. Printed Circuit, Backlight Unit and Display Device
CN114488613A (zh) * 2020-10-26 2022-05-13 乐金显示有限公司 印刷电路、背光单元和显示装置
US11762238B2 (en) * 2020-10-26 2023-09-19 Lg Display Co., Ltd. Printed circuit, backlight unit and display device
CN114488613B (zh) * 2020-10-26 2024-01-26 乐金显示有限公司 印刷电路、背光单元和显示装置

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