WO2003028118A1 - Iii group nitride quantum dot and production method therefor - Google Patents

Iii group nitride quantum dot and production method therefor Download PDF

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Publication number
WO2003028118A1
WO2003028118A1 PCT/JP2002/009786 JP0209786W WO03028118A1 WO 2003028118 A1 WO2003028118 A1 WO 2003028118A1 JP 0209786 W JP0209786 W JP 0209786W WO 03028118 A1 WO03028118 A1 WO 03028118A1
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iii nitride
group iii
etching
quantum dot
semiconductor layer
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PCT/JP2002/009786
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French (fr)
Japanese (ja)
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Kazumasa Hiramatsu
Hideto Miyake
Harumasa Yoshida
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Nagoya Industrial Science Research Institute
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00Nanooptics, e.g. quantum optics or photonic crystals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier

Definitions

  • the present invention relates to a method for producing a group III nitride quantum dot and the like.
  • the quantum structure is a one-dimensional quantum wire or a zero-dimensional quantum dot
  • the size of the active layer structure is about the effective Bohr radius of the exciton
  • the electron and hole wave functions overlap due to the quantum confinement effect and Coulomb interaction. Is increased, the binding energy of the exciton increases, and the oscillator strength of the exciton and the exciton molecule also increases. And this effect is thought to be stronger as the dimension of the quantum structure decreases.
  • the 111-V group semiconductors InGaAs and InGasZGaAs systems use the Stranski-Krastanov growth mode on a lattice-mismatched substrate. It is reported that quantum dots are formed spontaneously [Appl. Phys. Lett. 63, 3203 (1993); Nature 369, 131 (1994); Appl. Phys. Lett. 65, 1421 (1994)]. . It has also been reported that nanoscale GaN dots of various sizes are formed directly on 6H-SiC substrates [V. Dmitriev, K. Irvine, A. Zubrilov, D. Tsvetkov, V. Nikolaev, M. Jakobson, D. Nelson and A. Sitnikova, to be published in "Gallium Nitride and Related Materials” (Mater. Res. Soc. Symp. Proc.)].
  • quantum dots When applying quantum dots to electronic devices, it is necessary to form the quantum dots in a state where they are confined in another semiconductor layer.
  • GaN quantum dots In order to use GaN quantum dots for electronic devices, it is necessary to form GaN quantum dots in a state where they are confined within, for example, an A1 GaN layer with a larger band gap than GaN. is there.
  • GaN is grown on the A 1 GaN layer by ordinary metal-organic chemical vapor deposition (MOVP E) or molecular beam epitaxy (MBE), GaN / A 1 GaN
  • MOVP E metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • GaN / A 1 GaN Depending on the energy balance conditions of the system and the degree of lattice distortion, GaN grows in a film direction in a two-dimensionally spread state on the A 1 GaN layer as a film on the A 1 GaN layer.
  • GaN quantum dots cannot be formed at the same time.
  • quantum dots cannot be formed in a semiconductor layer as a device structure,
  • quantum dots there were circumstances in which it was not possible to contribute to higher performance of electronic devices.
  • the present invention has been made in view of such a situation, and is based on a material system that cannot form a quantum dot due to the surface energy balance condition and the degree of lattice distortion in a normal production method using MOVPE-MBE.
  • a method capable of forming quantum dots and to provide a quantum dot (group III nitride quantum dot) applicable to an electronic device manufactured by the method, and to provide such a quantum dot. It is to provide a method which can be manufactured easily. Disclosure of the invention
  • the present inventors have intensively studied a method of manufacturing a quantum dot using a group II nitride semiconductor such as a gallium nitride-based compound semiconductor, and have found a nanometer-order columnar structure (a nanopillar) made of a group II nitride semiconductor. ), And found that the initial objective can be achieved by manufacturing quantum dots using the nanopillars, and basically completed the present invention.
  • a group II nitride semiconductor such as a gallium nitride-based compound semiconductor
  • the first invention includes the following steps: (1) a lamination method in which at least three layers of a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are laminated to form a group III nitride semiconductor film; (2) a nanopillar manufacturing step of manufacturing a nano-pillar by dry-etching the group III nitride semiconductor film, and (3) a filling step of growing a new semiconductor in a gap between the nano-pillars and growing a filling layer.
  • This is a method for producing an in-group nitride quantum dot.
  • an etching slow substance having an etching rate smaller than that of the group II nitride semiconductor film is present on the surface of the group II nitride semiconductor film.
  • the III nitride semiconductor film is dry-etched. Note that the etching slow-moving substance is placed as a solid in the etching chamber, and may be exposed to an etching gas at the time of dry etching.
  • the band gap energy of the second semiconductor layer is the band gap energy of the first semiconductor layer and the band gap energy of the third semiconductor layer. It is characterized by being smaller than
  • the fourth invention is characterized in that, in the first invention to the third invention, a multilayer quantum dot is produced by repeating the above-mentioned (1) laminating step, (2) the above-mentioned nobular manufacturing step, and (3) the filling step. .
  • a fifth invention is a group III nitride device, characterized in that the quantum dots have a distribution density of 10 6 / c ⁇ 2 to 10 12 Z cm 2 .
  • the group III nitride quantum dot having such characteristics can be manufactured by the method according to any one of the first to fourth inventions. Next, the present invention will be described in more detail.
  • the material constituting the group III nitride quantum dots (having a plurality of group III nitride semiconductors and having a predetermined number of dots inside) manufactured by the present invention ie, the first semiconductor layer to the third Is a group III-V semiconductor containing nitrogen and a group III element (for example, gallium) such as GaN, GaAlN, and InGAN.
  • a group III element for example, gallium
  • X G a y I ri — y N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, and O ⁇ x + y ⁇ l).
  • These group III nitride semiconductors may be pure or doped with impurities, and the impurities may be either p-type or n-type.
  • the second semiconductor layer eventually becomes a quantum dot (sometimes referred to as an active layer or a light emitting layer).
  • the size of the quantum dot is about 1 ⁇ ! ⁇ 100 nm, height of about 1 nm to about 100 nm.
  • the second semiconductor layer has a sandwich-like structure sandwiched between the first semiconductor layer and the third semiconductor layer.
  • the band gap energy of the second semiconductor layer is determined by the band gap energy of the first semiconductor layer and the third band gap energy. It is preferable to make a selection so that the material becomes smaller than the band gap energy of the semiconductor layer.
  • the second semiconductor layer is not limited to a single semiconductor layer, and includes a multi-quantum structure in which the semiconductor layers having different heights of the hand gap energy from about 1 nm to about 100 nm are stacked.
  • a group III nitride quantum dot having a multilayer structure such as a double hetero structure.
  • the quantum dots are almost perpendicular and the height is uniform, so that the quantum dots excite each other, enabling highly efficient light emission.
  • the plurality of layers constituting the group III nitride quantum dots include a case where at least one of all the layers is formed of a group III nitride semiconductor.
  • the group III nitride semiconductor may be formed on a substrate such as sapphire.
  • Examples of dry etching methods that can be used in the “nanopillar fabrication process” include: 1) dry etching in the presence of an etching slow substance having a lower etching rate than group III nitride semiconductors, and 2) electron beam exposure. Without forming a mask using lithography technology such as And a method of performing dry etching using a tray.
  • the technical scope of the present invention is not limited to these methods, and may be any method that can produce nanopillars.
  • “Etching slow material” refers to a material that has a lower etching rate than the intrinsic target material of a group III nitride semiconductor when dry-etched. If such an etching slow substance is present on the surface of the group III nitride semiconductor, the dry etching speed will not be uniform on the target surface. For this reason, the portion where the etching slow substance is present will be etched more slowly than the portion where it is not, and irregularities (nanopillars) will be formed on the target surface (details will be described later).
  • Specific examples of the etching slow substance include quartz (Sio 2 ), sapphire, nickel, and an organic resist.
  • “Dry etching” is an etching method that uses gas discharge, unlike chemical wet etching. For example, reactive ion etching (RIE), electron cyclotron resonance etching (ECR), and electromagnetically coupled plasma There are methods such as etching (ICP).
  • RIE reactive ion etching
  • ECR electron cyclotron resonance etching
  • ICP electromagnetically coupled plasma
  • Present state means a state in which an etching slow substance is present on the surface of the group III nitride semiconductor film in the order of nanometer (range smaller than 1 / im).
  • etching is performed while a solid etching slow substance is placed in a chamber where dry etching is performed, so that the etching slow substance is etched by a sputtering effect.
  • a method of depositing it on the surface of a group III nitride semiconductor film (ii) a method of flowing an etching slow material into an etching chamber, and (iii) a method of previously depositing a nanometer-order etching slow material in a group III nitride. There is a method of appropriately sprinkling it on the surface of the semiconductor film.
  • Nanopillar means a structure in which multiple small pillars with a cross section of nanometer order are protruded.
  • Quartz for example quartz (S i 0 2), it is preferably produced by sapphire.
  • a small number of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer At least three layers are laminated to produce a group III nitride semiconductor film (lamination step).
  • nanopillars are manufactured by dry-etching the group III nitride semiconductor film (nanopillar manufacturing step).
  • a group III nitride quantum dot can be manufactured by growing a new semiconductor in the gap between the nanopillars and growing the filling layer (filling step).
  • any one of the materials constituting the first semiconductor layer and the material constituting the third semiconductor layer can be selected and used.
  • a group III nitride semiconductor different from any of the semiconductor layer to the third semiconductor layer is selected.
  • a buffer layer such as A 1 N is formed on a substrate such as sapphire (for example, it can be manufactured by MOVPE method), and the first semiconductor layer is formed on the buffer layer by, for example, MOVPE method.
  • the layer, the second semiconductor layer, and the third semiconductor layer are sequentially laminated to form a group III nitride semiconductor film (lamination step).
  • nanopillars are manufactured by etching the metal nitride semiconductor film by dry etching.
  • 1 0- 4 P a orders placed vacuum etch chamber a pair of positive and negative electrodes (e.g., the parallel plate electrodes) Place II I-nitride semiconductor film on one of the upper surface of quartz etching chamber (S i O 2 ) or sapphire is used as a tray for the negative electrode.
  • a gas containing chlorine of 1 Pa to 5 O Pa high frequency power is applied to the electrodes to generate plasma from a plasma generating gas, and the plasma is used to etch the group III nitride semiconductor film. Make nano villas.
  • the dimensions of the fabricated nanopillars are mostly less than about 100 nm, and the spacing between adjacent nanopillars (gap) is on average from several tens of nm to about 100 nm. It can be. For this reason, it is possible to form the nano pillar and the gap repeatedly at a distance of about several tens nm to about 100 nm. If you that, will be approximately 1 X 1 0 6 about nanopillars in 1 cm is configured, during 1 cm 2, it is possible to configure to about 1 X 1 0 11 about the quantum dots. Furthermore, when a laminated layer is used as the second semiconductor layer, a structure of about 1 ⁇ 10 12 or more quantum dots is formed. It becomes possible.
  • a new group III nitride semiconductor is grown in the gap between the nano-villagers made of the group III nitride semiconductor thus formed (filling step). At this time, it is preferable to perform etching with plasma such as CF 4 so as to completely remove the slow-etching substance from the surface of the nanopillar and contribute to the formation of a smooth filling layer.
  • the filling method may be, for example, metal organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE). (molecular beam epitaxy)).
  • (1) lamination process, (2) nanopillar fabrication process, and (3) filling process are made into one set, and the process of (1) to (3) is repeated sequentially to produce quantum dots formed in multiple layers in the height direction. be able to.
  • nanopillars fine needle-like structures
  • quantum dots can be manufactured by filling the gaps between the nanopillars with a new group III nitride semiconductor. .
  • the density of the dots this time 1 0 6 /.
  • Group III nitride quantum dots of m 2 to l 0 12 / cm 2 can be provided.
  • nanopillars can be easily formed on the surface of a group III nitride semiconductor film, and the gaps between the nanopillars are filled with a new group III nitride semiconductor, so that the group III nitride quantum can be efficiently produced. Dots can be manufactured.
  • FIG. 1 is a sectional view showing an outline of an etching apparatus that can be used for carrying out the present invention.
  • FIG. 2 is a view showing a process of manufacturing a group III nitride quantum dot.
  • FIG. 1A is a cross-sectional view of a substrate before stacking a group III nitride semiconductor
  • FIG. 1B is a cross-sectional view when a group II nitride semiconductor is stacked.
  • FIG. 3 is a diagram showing a process of manufacturing a group III nitride quantum dot.
  • FIG. (C) is a cross-sectional view when nano-vias are formed by dry etching
  • FIG. (D) is a cross-sectional view when a new group III nitride semiconductor is filled in the gaps between the nanopillars.
  • FIG. 4 is a cross-sectional view when a nanopillar is formed by applying a mask to a predetermined location.
  • FIG. 5 is a view showing an electron micrograph showing the structure of the etching surface after the group III nitride semiconductor film is etched according to Example 1.
  • FIG. 6 is a cross-sectional view when a group of positive and negative electrodes is provided on the group III nitride quantum dot.
  • FIG. 7 is a cross-sectional view of the multilayer quantum dot after the process of manufacturing the quantum dot is repeated a plurality of times.
  • nanopillar 50 nanopillar 50, sapphire 51, buffer layer 52, n-G a ⁇ (first semiconductor layer) 53, and InG a N (second semiconductor layer, Light-emitting layer) 54, p-InGaN (third semiconductor layer) 55, semiconductor structure having quantum dots 56, GAN (filled layer) 58, p-GaN (semiconductor) Layer) 59, group III nitride semiconductor film 60, electrodes 61, 62, multilayer quantum dots 70, group III nitride semiconductor 101, quartz substrate 102.
  • FIG. 1 is a schematic diagram showing an example of a dry etching apparatus that can be used to carry out the present invention.
  • This equipment includes an etching chamber 1, a high-frequency power supply 2, an exhaust device, and a plasma generating gas introduction device.
  • a pair of positive and negative parallel plate type electrodes 11 and 12 are installed in an etching chamber 1 made of stainless steel so as to face each other. Both electrodes are generally The high frequency power is applied to the cathode 12 while the anode 11 is kept at the ground potential. The cathode 12 is hit hard by the plasma gas and the temperature rises. For this reason, in order to cool the cathode 12, a hollow structure is provided so that cooling water can flow on the back side.
  • the cathode 12 is connected to a high frequency power supply 2 of 13.56 MHz via a matching box 22 to control the plasma.
  • An exhaust pipe 3 is provided in the etching chamber 1.
  • the exhaust pipe 3 is connected to an exhaust device (not shown) in which a dry pump, a turbo pump, and the like are combined.
  • the internal space of the etching chamber 1 can be evacuated to, for example, 10 to 4 Pa or less.
  • the pressure in the etching chamber 1 is adjusted by, for example, a pressure adjusting valve 33 provided in the middle of the exhaust pipe 3, and is always kept at a certain degree of vacuum.
  • the etching chamber 1 is further provided with gas introduction pipes 4a and 4b for introducing each plasma generating gas into the etching chamber 1 ⁇ .
  • the other end sides of these gas introduction pipes 4a and 4b are connected to an external plasma generating gas source (not shown).
  • the etching chamber 1 has a first gas introduction pipe 4a for introducing an etching gas (for example, chlorine gas) and another gas (a first gas when necessary).
  • a second gas introducing pipe 4b for introducing a gas for performing dry etching by mixing with a gas.
  • the flow rate of each gas is controlled by mass flow controllers 44a and 44b provided in the gas introduction pipes 4a and 4b, respectively.
  • n-GaN, InGaN, and pGaN are exemplified as semiconductors constituting the first to third semiconductor layers, respectively.
  • the scope is not limited to this, and use a nitride semiconductor represented by the formula A 1 X G a y I n ⁇ N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l and 0 ⁇ x + y ⁇ l) Can be.
  • the group III nitride semiconductor film is provided on the upper surface of a buffer layer 52 provided on the upper surface of a sapphire substrate 51, for example.
  • a first semiconductor layer 53 for example, For example, n-GaN can be used.
  • the second semiconductor layer 54 for example, InGaN can be used
  • the third semiconductor layer 55 for example, undoped Gn.
  • a N or InG aN, p-type G aN or InG aN, or A 1 InG aN can be used.
  • Are formed Fig. 2 (b)).
  • the thickness of the first semiconductor layer 53 is about several hundreds to several thousand nm
  • the thickness of the second semiconductor layer 54 (which eventually becomes a quantum dot and forms a light emitting layer) is about several nm.
  • the thickness of the third semiconductor layer 55 is about several nm to about 100 nm.
  • the band energy gap of the second semiconductor layer 54 is selected to be smaller than the band energy gap of the first semiconductor layer 53 and the third semiconductor layer 55. Further, the second semiconductor layer 54 and the third semiconductor layer 55 can be stacked.
  • each cathode 1 A quartz substrate 102 as a solid is placed on the upper surface side of 2, and a sample 101 in the form of a wafer, for example, is placed on or around the upper surface thereof.
  • the cross-sectional shape of the quartz substrate 102 should be larger than the cross-sectional shape of the sample 101, and the quartz substrate 102 is used as an etching gas. Keep exposed.
  • the exhaust device evacuated to the interior of the etching chamber 1 a 1 0- 4 P a order pressure of.
  • the chlorine gas is introduced from the gas inlet pipe 4a into the internal space of the etching chamber 1 while being controlled by the mass flow controller 44a to have a predetermined flow rate.
  • the inside of the etching chamber 1 is exhausted by the exhaust device, and the pressure adjusting valve 33 is adjusted to adjust The internal pressure of the chucking chamber 1 is controlled to a predetermined pressure.
  • the chlorine gas plasma sputters and etches the group III nitride semiconductor film 60 of the sample 101 while etching the quartz substrate 102 (nanofabric one manufacturing step).
  • nanopillars 50 are formed on the surface of the group III nitride semiconductor film 60, as shown in FIG. 3 (c).
  • the diameter of the nanopillars 50 ranges from about 10 nm to about 200 nm.
  • the spacing between adjacent nanopillars 50 is about 100 nm on average.
  • the diameter and the interval of the nanopillars 50 can be appropriately changed depending on the conditions at the time of etching.
  • a gap between the nanopillars 50 is filled with a new group III nitride semiconductor to form a filling layer 58 (filling step).
  • the filling method the MO VPE method, the HVP E method, the MBE method and the like are mentioned as described above.
  • the MO VPE method, the HVP E method, the MBE method and the like are mentioned as described above.
  • a quantum dot (group III nitride quantum dot) 56 made of a group III nitride semiconductor can be manufactured.
  • a light emitting device can be manufactured by providing a pair of positive and negative electrodes 61 and 62 above and below a quantum dot 56.
  • a semiconductor layer 59 (for example, p-GaN can be used) is further laminated on the upper surface side of the filling layer 58, and the electrode 61 is formed on the upper surface of the semiconductor layer 59. Is preferably provided.
  • a group III nitride semiconductor (eg, n—GaN, InGaN, and!) — GaN) composed of three new layers is provided.
  • a group III nitride semiconductor eg, n—GaN, InGaN, and! — GaN
  • n-GaN53 corresponding to the first semiconductor layer in the present invention
  • InGaN54 A group III nitride semiconductor film 60 on which p-GaN 55 (which is harmful to the third semiconductor layer in the present invention) is grown.
  • n-GaN53 corresponding to the first semiconductor layer in the present invention
  • InGaN54 A group III nitride semiconductor film 60 on which p-GaN 55 (which is harmful to the third semiconductor layer in the present invention) is grown.
  • p-GaN 55 which is harmful to the third semiconductor layer in the present invention
  • the thickness of n-Gan53 and p-gan55 was about 300 nm, and the thickness of InGa54 was about 20 nm.
  • the thickness of n-Gan53 and p-gan55 was about 300 nm, and the thickness of InGa54 was about 20 nm.
  • On the upper surface of the sample 10 for example, by RF sputtering, depositing a S i 0 2 at a thickness of about 300 nm, by conventional photolithography graphic techniques, ⁇ 1 1 00> direction of 5 mu m line and A space pattern was prepared and used as an etching sample 101.
  • a quartz substrate 102 was set on the stage of the etching chamber 1.
  • An etching sample 101 was placed around or on the upper surface of the quartz substrate 102.
  • etching chamber 1 was then evacuated etching chamber 1 to 5 X 1 0- 4 P a vacuum pump. After the degree of vacuum in the etching chamber 1 was stabilized, chlorine gas was introduced into the etching chamber 1 from the gas introduction pipe 4a at a flow rate of 30 ml / in while being controlled by the mass flow controller 44a. At the same time, the inside of the etching chamber 1 was evacuated by a vacuum pump, and the pressure regulating valve 33 was adjusted to control the pressure inside the etching chamber 1 to 6 Pa.
  • a voltage was applied from the high-frequency power source 2 to generate plasma between the electrodes 11 and 12 and 100 W (the area was 1 Dry etching was performed for about 4 minutes under the condition of 77 cm 2 ).
  • FIG. 5 shows a photograph showing the structure of the etched surface of the group III nitride semiconductor film observed by SEM.
  • the manufacturing process of nanopillars according to this embodiment can be considered as follows, for example. Wear. That is, chlorine ions in the plasma collide with the quartz substrate in the vicinity of GaN, and S i 0 2 jumps out into the plasma due to the sputtering effect. Some of the SiO 2 is likely to be ionized and redeposited on the negatively biased GaN film.
  • S i 0 2 is compared to G a N, since one degree and low 20 minutes 10 minutes Etsuchin Great to chlorine gas plasma, since acting as minute masks, Sample 1 0 1 A minute uneven structure is formed on the surface.
  • the nanopillar structure has a thickness of + nn!
  • the height was about 100 nm, and the height was about 500 nanometers.
  • the density of the nanopillars was on the order of 10 6 to ⁇ "!!! 2. It was found that the height of the nanopillars was greatly dependent on the etching time.
  • the gap between the nanopillar structures fabricated in this way was filled with a new group III nitride semiconductor (G a N) by, for example, MOV PE method to form a filling layer 58 (Fig. 3 (d) reference).
  • the conditions at this time trimethyl gallium (TMG) flowed at 48 i mol / min, the NH 3 11 / min, 1 000 ° C, was 300 Torr.
  • TMG trimethyl gallium
  • n-GaN, InGaN, and pGaN are newly laminated on the upper surface side, and the laminated semiconductor film is
  • the multilayer quantum dot 70 shown in FIG. 7 can also be manufactured by repeating the operation of fabricating the nano-village by the dry etching operation and filling the gap between the nano-pillars.
  • nano-pillars 56 can be easily formed on the surface of the group III nitride semiconductor film 60, and the gaps between the nanopillars 56 are filled with the new group III nitride semiconductor. This makes it possible to efficiently manufacture the group III nitride quantum dots 56. Also, by utilizing such a group III nitride quantum dot 56, It is also possible to manufacture large-area light-emitting diode displays and large-area fluorescent displays using field emission cold cathodes.
  • a group III nitride quantum dot having a multilayer structure is used as the second semiconductor layer.
  • the quantum dots are almost vertical on the sides and are uniform in height, so that the quantum dots excite each other, enabling efficient light emission Becomes

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Abstract

A quantum dot (III group nitride dot) consisting of a III group nitride semiconductor, and a method of satisfactorily producing such a quantum dot. As shown in Fig. 3, etching is conducted during a dry etching with a quartz substrate and a III group nitride semiconductor placed on the upper surface of an electrode below to thereby form a nano-pillar structure (50) on the top surface of a III group nitride semiconductor (101). The gaps in this nano-pillar structure (50) are filled with a new III group nitride semiconductor to form a filling layer (58), thereby producing a III group nitride quantum dot (56).

Description

明 細 書  Specification
III族窒化物量子ドットおよびその製造方法 技術分野  Group III nitride quantum dots and method for producing the same
本発明は、 III族窒化物量子ドッ トの製造方法等に関するものである。 背景技術  The present invention relates to a method for producing a group III nitride quantum dot and the like. Background art
近年、 量子井戸、 量子細線、 量子箱 (量子ドット) 等の半導体量子構造に閉じ 込められた電子やエキシトンを利用した電子デバイス、 例えばレーザーや各種の 非線形光学素子、 記憶素子についての研究が進められている。 例えば、 窒化ガリ ゥム及びその他の III族窒化物は、 高品質短波長発光ダイォード及びレーザーダ ィオードを実現できる素子として注目されており、 Jpn. J. Appl. Phys. 35, L74 (1996)、 Appl. Phys. Lett. 68, 2105 (1996)には、 I n G a N多層量子井戸か らのレーザー発振が報告されている。  In recent years, research has been conducted on electronic devices using electrons and excitons confined in semiconductor quantum structures such as quantum wells, quantum wires, and quantum boxes (quantum dots), such as lasers, various nonlinear optical elements, and storage elements. ing. For example, gallium nitride and other group III nitrides have been attracting attention as devices capable of realizing high-quality short-wavelength light-emitting diodes and laser diodes. Jpn. J. Appl. Phys. 35, L74 (1996), Appl. Phys. Lett. 68, 2105 (1996) reports laser oscillations from InGaN multilayer quantum wells.
このような半導体量子構造を利用した電子デバイスの実用化にあたっては解決 すべき多くの問題がある。 例えば、 短波長レーザーダイオードへの応用を考える とき、 前記 I n G a N多層量子井戸のレーザー発振の閾値電流は 8 . 7 kA/cm2と 報告されており、 G a A s系の III一 V族レーザーダイォードゃ Z n S e系の II 一 VI族レーザーダイォードの閾値電流である 1 0 0〜2 0 0 A/cm2程度と比較し て著しく高いことから、 閾値電流を低下させることが必要である。 レーザー発振 の閾値電流は、 活性層構造のサイズを小さくすることによって改善できると考え られる。 すなわち、 量子構造を 1次元の量子細線又は 0次元の量子ドットとして 活性層構造のサイズをエキシトンの実効ボーァ半径程度とすると、 量子閉じ込め 効果により電子とホールの波動関数の重なり合いが增しクーロン相互作用が高め られるため、 エキシトンの結合エネルギーが増大し、 エキシトン及びエキシトン 分子の振動子強度も増大する。 そして、 この効果は量子構造の次元が下がるにつ れ、 より強くなると考えられるからである。 There are many problems that need to be solved in putting electronic devices using such semiconductor quantum structures into practical use. For example, when considering the application to short-wavelength laser diode, wherein I n G a N multilayer threshold current of the laser oscillation of the quantum wells 8. 7 kA / cm 2 is reported to, G a A s based III one since significantly higher as compared with 1 0 0~2 0 0 a / cm 2 about a group V laser die O over de Ya Z n S e system II one group VI laser die O over de threshold current, lowering the threshold current It is necessary. It is thought that the threshold current of laser oscillation can be improved by reducing the size of the active layer structure. In other words, if the quantum structure is a one-dimensional quantum wire or a zero-dimensional quantum dot, and the size of the active layer structure is about the effective Bohr radius of the exciton, the electron and hole wave functions overlap due to the quantum confinement effect and Coulomb interaction. Is increased, the binding energy of the exciton increases, and the oscillator strength of the exciton and the exciton molecule also increases. And this effect is thought to be stronger as the dimension of the quantum structure decreases.
0次元の量子ドットに関し、111一 V族半導体である I n G a A s及び I n A s ZG a A s系では、 格子不整合基板上に Stranski- Krastanov 成長モードによつ て量子ドッ トが自然形成されることが報告されている [Appl.Phys. Lett. 63, 3203(1993); Nature 369, 131 (1994); Appl. Phys. Lett.65, 1421(1994)〕。 また、 種々のサイズのナノスケール G a Nドットが 6H— S i C基板上に直接形成され ることが報告されている 〔V. Dmitriev, K. Irvine, A. Zubrilov, D. Tsvetkov, V. Nikolaev, M. Jakobson, D. Nelson andA. Sitnikova, to be published in "Gallium Nitride and Related Materials" (Mater. Res. Soc. Symp. Proc. )〕。 Regarding the zero-dimensional quantum dot, the 111-V group semiconductors InGaAs and InGasZGaAs systems use the Stranski-Krastanov growth mode on a lattice-mismatched substrate. It is reported that quantum dots are formed spontaneously [Appl. Phys. Lett. 63, 3203 (1993); Nature 369, 131 (1994); Appl. Phys. Lett. 65, 1421 (1994)]. . It has also been reported that nanoscale GaN dots of various sizes are formed directly on 6H-SiC substrates [V. Dmitriev, K. Irvine, A. Zubrilov, D. Tsvetkov, V. Nikolaev, M. Jakobson, D. Nelson and A. Sitnikova, to be published in "Gallium Nitride and Related Materials" (Mater. Res. Soc. Symp. Proc.)].
量子ドットの電子デバイスへの応用に当たっては、 量子ドットを他の半導体層 の中に閉じ込めた状態で形成することが必要である。 例えば、 G a N量子ドット を電子デバイスに利用するには、 G a N量子ドットを G a Nよりバンドギャップ の大きな例えば A 1 G a N層の中に閉じ込めた状態で形成することが必要である。  When applying quantum dots to electronic devices, it is necessary to form the quantum dots in a state where they are confined in another semiconductor layer. For example, in order to use GaN quantum dots for electronic devices, it is necessary to form GaN quantum dots in a state where they are confined within, for example, an A1 GaN layer with a larger band gap than GaN. is there.
しかし、 通常の有機金属化学気相堆積法 (MOVP E) や分子線エピタキシー 法 (MBE) によって A 1 G a N層上に G a Nの成長を行うと、 G a N/A 1 G a N系のエネルギー平衡条件及び格子歪みの程度によって、 G a Nは A 1 G a N 層の上に膜として 2次元的に広がった状態で膜厚方向に成長するため、 A 1 G a N層上に G a N量子ドットを形成することができない。 これは、 G a N/A 1 G a N系のみでなく、 電子デバイスへの半導体量子構造の適用が有望視されている 他の化合物半導体系、 例えば G a A s /G a A 1 A s系、 Z n C d S e/Z n S S e系においても同じ状況にある。  However, when GaN is grown on the A 1 GaN layer by ordinary metal-organic chemical vapor deposition (MOVP E) or molecular beam epitaxy (MBE), GaN / A 1 GaN Depending on the energy balance conditions of the system and the degree of lattice distortion, GaN grows in a film direction in a two-dimensionally spread state on the A 1 GaN layer as a film on the A 1 GaN layer. GaN quantum dots cannot be formed at the same time. This is not limited to the G a N / A 1 G a N system, but also for other compound semiconductor systems for which the application of semiconductor quantum structures to electronic devices is promising, such as G a A s / G a A 1 A s The same situation exists in the system, ZnCdSe / ZnSSe system.
このように電子デバイスの高性能化、 高機能化のために量子ドットを利用する ことが有利であっても、 現実にはデバイス構造として半導体層の中に量子ドット を形成することができないために、 電子デバイスの高性能化に寄与することがで きない事情があった。  Thus, although it is advantageous to use quantum dots for higher performance and higher functionality of electronic devices, in reality, quantum dots cannot be formed in a semiconductor layer as a device structure, However, there were circumstances in which it was not possible to contribute to higher performance of electronic devices.
本発明は、 このような状況に鑑みてなされたもので、 MOVPEゃMBEにょ る通常の製法では表面のエネルギー平衡条件及び格子歪みの程度のために量子ド ットを形成することができない材料系においても量子ドットの形成を可能とする 方法を提供すること、 及びその方法によって作製された電子デバイスへの適用が 可能な量子ドット (III族窒化物量子ドット)、 およびそのような量子ドットを良 好に製造可能な方法を提供することである。 発明の開示 The present invention has been made in view of such a situation, and is based on a material system that cannot form a quantum dot due to the surface energy balance condition and the degree of lattice distortion in a normal production method using MOVPE-MBE. To provide a method capable of forming quantum dots, and to provide a quantum dot (group III nitride quantum dot) applicable to an electronic device manufactured by the method, and to provide such a quantum dot. It is to provide a method which can be manufactured easily. Disclosure of the invention
本発明者らは、 例えば窒化ガリウム系化合物半導体などの I II族窒化物半導体 を用いた量子ドットを製造する方法に関して鋭意検討し、 II I 族窒化物半導体か らなるナノメータオーダーの柱状構造 (ナノピラー) を形成し、 そのナノピラー を利用して量子ドットを製造することにより当初の目的を達成できることを見い 出し、 基本的には本発明を完成するに至った。  The present inventors have intensively studied a method of manufacturing a quantum dot using a group II nitride semiconductor such as a gallium nitride-based compound semiconductor, and have found a nanometer-order columnar structure (a nanopillar) made of a group II nitride semiconductor. ), And found that the initial objective can be achieved by manufacturing quantum dots using the nanopillars, and basically completed the present invention.
第 1の発明は、 以下の各工程、 ①第 1の半導体層と第 2の半導体層と第 3の半 導体層との少なくとも三層を積層させて I I I族窒化物半導体膜を作製する積層ェ 程、 ②前記 I I I族窒化物半導体膜をドライエッチングすることにより、 ナノビラ 一を作製するナノピラー作製工程、 ③前記ナノビラ一の隙間に新たな半導体を成 長させて充填層を成長させる充填工程を含むことを特徴とする in族窒化物量子 ドットの製造方法である。  The first invention includes the following steps: (1) a lamination method in which at least three layers of a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are laminated to form a group III nitride semiconductor film; (2) a nanopillar manufacturing step of manufacturing a nano-pillar by dry-etching the group III nitride semiconductor film, and (3) a filling step of growing a new semiconductor in a gap between the nano-pillars and growing a filling layer. This is a method for producing an in-group nitride quantum dot.
第 2の発明は、 第 1の発明において、 上記②のナノピラー作製工程は、 II I 族 窒化物半導体膜の表面に、 その ΠΙ族窒化物半導体膜に比べてエッチングレート が小さいエッチング遅速物質を存在させた状態で、 前記 II I族窒化物半導体膜を ドライエッチングすることを特徴とする。 なお、 前記エッチング遅速物質は、 固 体としてエッチング室内に載置されており、 ドライエッチングの際にエッチング ガスに曝されるようにしてもよレ、。  According to a second aspect, in the first aspect, in the nanopillar manufacturing step (1), an etching slow substance having an etching rate smaller than that of the group II nitride semiconductor film is present on the surface of the group II nitride semiconductor film. In this state, the III nitride semiconductor film is dry-etched. Note that the etching slow-moving substance is placed as a solid in the etching chamber, and may be exposed to an etching gas at the time of dry etching.
第 3の発明は、 第 1の発明または第 2の発明において、 前記第 2の半導体層の バンドギャップエネルギーは、 前記第 1の半導体層のバンドギャップエネルギー 及び前記第 3の半導体層のバンドギヤップエネルギーよりも小さいことを特徴と する。  In a third aspect based on the first or second aspect, the band gap energy of the second semiconductor layer is the band gap energy of the first semiconductor layer and the band gap energy of the third semiconductor layer. It is characterized by being smaller than
第 4の発明は、 第 1の発明〜第 3の発明において、 前記①積層工程、 前記②ナ ノビラー作製工程、 及び前記③充填工程を繰り返すことにより、 多層量子ドット を作製することを特徴とする。  The fourth invention is characterized in that, in the first invention to the third invention, a multilayer quantum dot is produced by repeating the above-mentioned (1) laminating step, (2) the above-mentioned nobular manufacturing step, and (3) the filling step. .
第 5の発明は、 量子ドットの分布密度が 1 0 6個/ c πι2〜 1 0 12個 Z c m2であ ることを特徴とする I I I族窒化物素子である。 このような特徴を備えた II I族窒 化物量子ドットは、 上記第 1の発明〜第 4の発明のいずれかに記載の方法によつ て製造することができる。 次に本発明をさらに詳しく説明する。 A fifth invention is a group III nitride device, characterized in that the quantum dots have a distribution density of 10 6 / c πι 2 to 10 12 Z cm 2 . The group III nitride quantum dot having such characteristics can be manufactured by the method according to any one of the first to fourth inventions. Next, the present invention will be described in more detail.
本発明により製造される III族窒化物量子ドット (III族窒化物半導体を複数 に積層させた内部に、 所定数のドットを備えたもの) を構成する材料、 すなわち 第 1の半導体層〜第 3の半導体層としては、 G a N、 G a A l N、 I n G a N等 の III族元素 (例えば、 ガリウム) と窒素とを含む III一 V族半導体であり、 一 般に式 A 1 XG a y I ri — yN (0≤x≤l , 0≤y^ lかつ、 O ^ x+y^ l) で表わすこと ができる。 これら III族窒化物半導体は、 純粋なもの、 或いは不純物がドープさ れたものでもよく、 また不純物としては、 p型、 n型のいずれでもよい。 The material constituting the group III nitride quantum dots (having a plurality of group III nitride semiconductors and having a predetermined number of dots inside) manufactured by the present invention, ie, the first semiconductor layer to the third Is a group III-V semiconductor containing nitrogen and a group III element (for example, gallium) such as GaN, GaAlN, and InGAN. X G a y I ri — y N (0≤x≤l, 0≤y ^ l, and O ^ x + y ^ l). These group III nitride semiconductors may be pure or doped with impurities, and the impurities may be either p-type or n-type.
第 2の半導体層は、 最終的に量子ドット (活性層または発光層と言うことがあ る。) となる。 本明細書中において、 その量子ドットの大きさは、 幅が約 1 η π!〜 約 1 0 0 n m、 高さが約 1 n m〜約 1 0 0 n mのものを意味する。  The second semiconductor layer eventually becomes a quantum dot (sometimes referred to as an active layer or a light emitting layer). In this specification, the size of the quantum dot is about 1 ηπ!約 100 nm, height of about 1 nm to about 100 nm.
また、 第 2の半導体層は、 第 1の半導体層と第 3の半導体層とによって挟まれ たサンドィツチ様の構造となる。 この量子ドットを備えた I II属窒化物量子ドッ トがレーザとして良好な作用を示すために、 第 2の半導体層のバンドギャップェ ネルギ一は、 第 1の半導体層のバンドギャップエネルギー及び第 3の半導体層の バンドギヤップエネルギーよりも小さい物質となるような選択を行うことが好ま しい。 さらに、 第 2の半導体層は、 単一の半導体層に限らず、 ハンドギャップェ ネノレギ一の異なる高さが約 1 n m〜約 1 0 0 n mの半導体層を積層した多重量子 構造を含む。 この場合、 例えばダブルへテロ構造のような多層構造の ΠΙ族窒化 物量子ドットの製造にも、 良好に用いることができる。 そのような多層量子ドッ トでは、 側面がほぼ垂直で高さの揃った量子ドットとなるので、 互いの量子ドッ トが励起しあって、 高効率な発光が可能となる。  In addition, the second semiconductor layer has a sandwich-like structure sandwiched between the first semiconductor layer and the third semiconductor layer. In order for the group II nitride quantum dot provided with this quantum dot to exhibit a good function as a laser, the band gap energy of the second semiconductor layer is determined by the band gap energy of the first semiconductor layer and the third band gap energy. It is preferable to make a selection so that the material becomes smaller than the band gap energy of the semiconductor layer. Further, the second semiconductor layer is not limited to a single semiconductor layer, and includes a multi-quantum structure in which the semiconductor layers having different heights of the hand gap energy from about 1 nm to about 100 nm are stacked. In this case, for example, it can be favorably used for the production of a group III nitride quantum dot having a multilayer structure such as a double hetero structure. In such a multi-layer quantum dot, the quantum dots are almost perpendicular and the height is uniform, so that the quantum dots excite each other, enabling highly efficient light emission.
また、 ΙΠ 族窒化物量子ドットを構成する複数層は、 全ての層のうち少なくと も 1層が III族窒化物半導体で形成された場合を含む。 また、 III族窒化物半導 体は、 例えばサファイア等の基板上に形成されていてもよい。  Further, the plurality of layers constituting the group III nitride quantum dots include a case where at least one of all the layers is formed of a group III nitride semiconductor. Further, the group III nitride semiconductor may be formed on a substrate such as sapphire.
「ナノピラー作製工程」 において使用可能なドライエッチング方法としては、 例えば、 ① III 族窒化物半導体に比べてエッチングレートが小さいエッチング遅 速物質を存在させた状態でドライエッチングを行う方法、 ②電子ビーム露光など のリソグラフィ技術を用いてマスクを形成することなく、 適切なエッチングガス と トレーを使用してドライエッチングを行う方法などがあるが、 本発明の技術的 範囲はこれらの方法には限られず、 ナノピラーを作製可能な方法であればよい。 Examples of dry etching methods that can be used in the “nanopillar fabrication process” include: 1) dry etching in the presence of an etching slow substance having a lower etching rate than group III nitride semiconductors, and 2) electron beam exposure. Without forming a mask using lithography technology such as And a method of performing dry etching using a tray. However, the technical scope of the present invention is not limited to these methods, and may be any method that can produce nanopillars.
「エッチング遅速物質」 とは、 ドライエッチングするときに、 本質的なターゲ ット物質である III族窒化物半導体のエッチングレートよりも小さいエッチング レートを備えた物質のことである。 そのようなエッチング遅速物質が III族窒化 物半導体の表面に存在すると、 ドライエッチングのスピードがターゲット表面に おいて均一ではなくなつてしまう。 このため、 エッチング遅速物質が存在する部 分は、 そうでない部分よりもエッチングが遅く行われることになり、 ターゲット 表面に凹凸 (ナノピラー) が形成されることになる (詳細については後述する)。 具体的なエッチング遅速物質としては、石英(S i o 2)、サファイア、 ニッケル、 有機レジス トなどが例示される。 “Etching slow material” refers to a material that has a lower etching rate than the intrinsic target material of a group III nitride semiconductor when dry-etched. If such an etching slow substance is present on the surface of the group III nitride semiconductor, the dry etching speed will not be uniform on the target surface. For this reason, the portion where the etching slow substance is present will be etched more slowly than the portion where it is not, and irregularities (nanopillars) will be formed on the target surface (details will be described later). Specific examples of the etching slow substance include quartz (Sio 2 ), sapphire, nickel, and an organic resist.
「ドライエッチング」 とは、 化学的な湿式エッチングとは異なり、 気体の放電 を利用したエツチング方法のことであり、 例えば反応性イオンエッチング ( R I E )、 電子サイクロ トロン共鳴エッチング (E C R )、 電磁結合プラズマエツチン グ (I C P ) などの方法がある。  “Dry etching” is an etching method that uses gas discharge, unlike chemical wet etching. For example, reactive ion etching (RIE), electron cyclotron resonance etching (ECR), and electromagnetically coupled plasma There are methods such as etching (ICP).
「存在させた状態」 とは、 III 族窒化物半導体膜の表面にエッチング遅速物質 がナノメータオーダ一 ( 1 /i mよりも小さい範囲) として存在する状態のことを 意味している。 そのような状態を達成する方法としては、 例えば、 (i)ドライエツ チングを行う室内に、 固体としてのエッチング遅速物質を載置した状態でエッチ ングすることにより、 スパッタリング効果でエッチング遅速物質をエッチング室 内に発生させ、 それを III族窒化物半導体膜の表面に付着させる方法、 (ii)エツ チング遅速物質をエッチング室内に流入させる方法、(iii)ナノメータオーダーの ェツチング遅速物質を予め III族窒化物半導体膜の表面に適当に振り掛けておく 方法などが挙げられる。  “Present state” means a state in which an etching slow substance is present on the surface of the group III nitride semiconductor film in the order of nanometer (range smaller than 1 / im). As a method for achieving such a state, for example, (i) etching is performed while a solid etching slow substance is placed in a chamber where dry etching is performed, so that the etching slow substance is etched by a sputtering effect. A method of depositing it on the surface of a group III nitride semiconductor film, (ii) a method of flowing an etching slow material into an etching chamber, and (iii) a method of previously depositing a nanometer-order etching slow material in a group III nitride. There is a method of appropriately sprinkling it on the surface of the semiconductor film.
「ナノピラー」 とは、 ナノメータオーダーの大きさからなる断面を備えた小柱 が複数にわたって突設された構造のことを意味している。  “Nanopillar” means a structure in which multiple small pillars with a cross section of nanometer order are protruded.
「トレー」 は、 例えば石英 (S i 02)、 サファイアなどにより作製することが 好ましい。 "Tray", for example quartz (S i 0 2), it is preferably produced by sapphire.
第 1の発明では、 第 1の半導体層と第 2の半導体層と第 3の半導体層との少な くとも三層を積層させて III族窒化物半導体膜を作製する (積層工程)。 次に、 こ の ΠΙ族窒化物半導体膜をドライエッチングすることにより、 ナノピラーを作製 する (ナノピラー作製工程)。 最後に、ナノピラーの隙間に新たな半導体を成長さ せて充填層を成長させる (充填工程) ことにより、 III 族窒化物量子ドットを製 造することができる。 In the first invention, a small number of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer At least three layers are laminated to produce a group III nitride semiconductor film (lamination step). Next, nanopillars are manufactured by dry-etching the group III nitride semiconductor film (nanopillar manufacturing step). Finally, a group III nitride quantum dot can be manufactured by growing a new semiconductor in the gap between the nanopillars and growing the filling layer (filling step).
「充填層」 を構成する材料としては、 第 1の半導体層または第 3の半導体層を 構成する材料のうちいずれか一方の材料を選択して使用することもできるが、 好 ましくは第 1の半導体層〜第 3の半導体層のいずれとも異なる III族窒化物半導 体を選択する。 なお充填層として、 第 2の半導体層を構成する材料よりも導電性 の低い半導体を選択することが好ましい。 そのようにすれば、 所定の位置に設け られた量子ドットに対して、選択的に電圧をかけることが可能となるからである。 より具体的には、 例えばサファイアなどの基板上に A 1 Nなどのバッファ層を 形成し (例えば、 M O V P E法により作製できる。)、 そのバッファ層上に、 例え ば M O V P E法により、 第 1の半導体層、 第 2の半導体層及び第 3の半導体層を 順次積層させて III族窒化物半導体膜を作製する (積層工程)。  As the material constituting the “filled layer”, any one of the materials constituting the first semiconductor layer and the material constituting the third semiconductor layer can be selected and used. A group III nitride semiconductor different from any of the semiconductor layer to the third semiconductor layer is selected. Note that it is preferable to select, as the filling layer, a semiconductor having lower conductivity than the material of the second semiconductor layer. By doing so, it is possible to selectively apply a voltage to the quantum dots provided at predetermined positions. More specifically, a buffer layer such as A 1 N is formed on a substrate such as sapphire (for example, it can be manufactured by MOVPE method), and the first semiconductor layer is formed on the buffer layer by, for example, MOVPE method. The layer, the second semiconductor layer, and the third semiconductor layer are sequentially laminated to form a group III nitride semiconductor film (lamination step).
次いで、 ドライエッチングによって、 Π Ι 属窒化物半導体膜をエッチング処理 することでナノピラーを作製する。 例えば、 1 0— 4 P aのオーダーに減圧された エッチング室内に設置された正負一対の電極 (例えば、 平行平板電極) の一方の 上面に II I族窒化物半導体膜を置き、 エッチング室内に石英 (S i O2) または、 サファイアを負電極のトレーとして用いる。 l Pa〜 5 O Paの塩素を含むガスを導 入した後、 前記電極に高周波電力を印加してブラズマ発生ガスからブラズマを発 生させ、 そのプラズマにより I I I族窒化物半導体膜をエッチングして、 ナノビラ 一を作製する。 作製されたナノピラーの寸法は、 約 1 0 0 n m以下のものが大部 分となることに加え、 隣接するナノピラーの間隔寸法 (間隙) は、 平均的に数十 n m〜約 1 0 0 n m程度とすることができる。 このため、 数十 n m〜約 1 0 0 n m程度の距離でナノピラーと間隙とを繰り返して構成することが可能となる。 す ると、 1 c m中に約 1 X 1 0 6程度のナノピラーが構成されることとなり、 1 c m 2中には、 約 1 X 1 0 11程度の量子ドットの構成が可能となる。 さらに、 第 2の半 導体層として積層した層を用いた場合、 約 1 X 1 0 12以上の量子ドットの構成が 可能となる。 Next, nanopillars are manufactured by etching the metal nitride semiconductor film by dry etching. For example, 1 0- 4 P a orders placed vacuum etch chamber a pair of positive and negative electrodes (e.g., the parallel plate electrodes) Place II I-nitride semiconductor film on one of the upper surface of quartz etching chamber (S i O 2 ) or sapphire is used as a tray for the negative electrode. After introducing a gas containing chlorine of 1 Pa to 5 O Pa, high frequency power is applied to the electrodes to generate plasma from a plasma generating gas, and the plasma is used to etch the group III nitride semiconductor film. Make nano villas. The dimensions of the fabricated nanopillars are mostly less than about 100 nm, and the spacing between adjacent nanopillars (gap) is on average from several tens of nm to about 100 nm. It can be. For this reason, it is possible to form the nano pillar and the gap repeatedly at a distance of about several tens nm to about 100 nm. If you that, will be approximately 1 X 1 0 6 about nanopillars in 1 cm is configured, during 1 cm 2, it is possible to configure to about 1 X 1 0 11 about the quantum dots. Furthermore, when a laminated layer is used as the second semiconductor layer, a structure of about 1 × 10 12 or more quantum dots is formed. It becomes possible.
こうして形成された III 族窒化物半導体からなるナノビラ一の隙間に新たな III族窒化物半導体を成長させる (充填工程)。 なおこのときには、 ナノピラー表 面のェツチング遅速物質を完全に取り去って、 円滑な充填層の形成に寄与できる ように、 C F 4などのプラズマによりエッチングを行うことが好ましい。 充填さ せる方法としては、 例えば、 有機金属化合物気相成長法 (M O V P E (metal organic vaper phase epitaxy) )、ノヽィ卜フィド V P E法 (H V P E (hydride vaper phase epitaxy) または分子線ェピタキシャル成長法 (M B E (molecular beam epitaxy) ) などの方法が例示される。 A new group III nitride semiconductor is grown in the gap between the nano-villagers made of the group III nitride semiconductor thus formed (filling step). At this time, it is preferable to perform etching with plasma such as CF 4 so as to completely remove the slow-etching substance from the surface of the nanopillar and contribute to the formation of a smooth filling layer. The filling method may be, for example, metal organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE). (molecular beam epitaxy)).
また、 ①積層工程、 ②ナノピラー作製工程、 及ぴ③充填工程を一つのセットと して、 ①〜③の工程を順次繰り返すことにより、 高さ方向に多層に形成された量 子ドットを作製することができる。  In addition, (1) lamination process, (2) nanopillar fabrication process, and (3) filling process are made into one set, and the process of (1) to (3) is repeated sequentially to produce quantum dots formed in multiple layers in the height direction. be able to.
本発明によれば、微細な針状構造(ナノピラー)を容易に作成することができ、 そのナノピラーの隙間を新たな III族窒化物半導体で充填することによって、 量 子ドットを製造することができる。 また、 このときドットの密度が、 1 0 6個/。 m2〜 l 0 12個 / c m2の III族窒化物量子ドットを提供することができる。 According to the present invention, fine needle-like structures (nanopillars) can be easily formed, and quantum dots can be manufactured by filling the gaps between the nanopillars with a new group III nitride semiconductor. . The density of the dots this time, 1 0 6 /. Group III nitride quantum dots of m 2 to l 0 12 / cm 2 can be provided.
本発明によれば、 III 族窒化物半導体膜の表面にナノピラーを容易に形成する ことができ、 そのナノピラーの隙間を新たな III族窒化物半導体で充填すること により、 効率よく III族窒化物量子ドットを製造することができる。  According to the present invention, nanopillars can be easily formed on the surface of a group III nitride semiconductor film, and the gaps between the nanopillars are filled with a new group III nitride semiconductor, so that the group III nitride quantum can be efficiently produced. Dots can be manufactured.
また、 上記のような III族窒化物量子ドットを利用して、 大面積を備えた発光 ダイォードディスプレイや、 電界放出型冷陰極による大面積の蛍光ディスプレイ を製造することも可能となる。 図面の簡単な説明  Further, it is possible to manufacture a large-area light-emitting diode display or a large-area fluorescent display using a field emission cold cathode using the above-described group III nitride quantum dots. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 本発明の実施に使用することができるエッチング装置の概要を示す 断面図である。  FIG. 1 is a sectional view showing an outline of an etching apparatus that can be used for carrying out the present invention.
第 2図は、 III 族窒化物量子ドットを製造する工程を示す図である。 図 (a ) は、 III 族窒化物半導体を積層する前の基板の断面図であり、 図 (b ) は、 I II 族窒化物半導体を積層したときの断面図である。 第 3図は、 III 族窒化物量子ドットを製造する工程を示す図である。 図 (c ) は、ドライエッチングによってナノビラ一を形成したときの断面図であり、図( d ) は、 ナノピラーの隙間に新たな III族窒化物半導体を充填したときの断面図であ る。 FIG. 2 is a view showing a process of manufacturing a group III nitride quantum dot. FIG. 1A is a cross-sectional view of a substrate before stacking a group III nitride semiconductor, and FIG. 1B is a cross-sectional view when a group II nitride semiconductor is stacked. FIG. 3 is a diagram showing a process of manufacturing a group III nitride quantum dot. FIG. (C) is a cross-sectional view when nano-vias are formed by dry etching, and FIG. (D) is a cross-sectional view when a new group III nitride semiconductor is filled in the gaps between the nanopillars.
第 4図は、 所定の場所にマスクを施してナノピラーを形成したときの断面図で ある。  FIG. 4 is a cross-sectional view when a nanopillar is formed by applying a mask to a predetermined location.
第 5図は、 実施例 1により III族窒化物半導体膜をエッチングした後のエッチ ング面の構造を示す電子顕微鏡写真を示す図である。  FIG. 5 is a view showing an electron micrograph showing the structure of the etching surface after the group III nitride semiconductor film is etched according to Example 1.
第 6図は、 ΙίΙ 族窒化物量子ドットに正負一対の電極を設けたときの断面図で ある。  FIG. 6 is a cross-sectional view when a group of positive and negative electrodes is provided on the group III nitride quantum dot.
第 7図は、 量子ドットを製造する工程を複数回に渡って繰り返した後の多層量 子ドットの断面図である。  FIG. 7 is a cross-sectional view of the multilayer quantum dot after the process of manufacturing the quantum dot is repeated a plurality of times.
なお、 図中の符号は、 それぞれ、 ナノピラー 5 0、 サファイア 5 1、 バッファ 層 5 2、 n - G a Ν (第 1の半導体層) 5 3、 I n G a N (第 2の半導体層、 発 光層) 5 4、 p - I n G a N (第 3の半導体層) 5 5、 量子ドット 5 6を有する 半導体構造、 G a N (充填層) 5 8、 p - G a N (半導体層) 5 9、 III 族窒化 物半導体膜 6 0、 電極 6 1, 6 2、 多層量子ドット 7 0、 III 族窒化物半導体 1 0 1、 石英基板 1 0 2である。 発明を実施するための最良の形態  The symbols in the figure are nanopillar 50, sapphire 51, buffer layer 52, n-G a Ν (first semiconductor layer) 53, and InG a N (second semiconductor layer, Light-emitting layer) 54, p-InGaN (third semiconductor layer) 55, semiconductor structure having quantum dots 56, GAN (filled layer) 58, p-GaN (semiconductor) Layer) 59, group III nitride semiconductor film 60, electrodes 61, 62, multilayer quantum dots 70, group III nitride semiconductor 101, quartz substrate 102. BEST MODE FOR CARRYING OUT THE INVENTION
次に本発明の実施の形態について、 図面を参照しつつ詳細に説明する。 なお、 本発明は、 下記の実施形態または実施例によって限定されるものではなく、 発明 め要旨を変更することなく様々な態様で実施することができる。 さらに、 本発明 の技術的範囲は、 均等の範囲にまで及ぶものである。  Next, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited by the following embodiments or examples, and can be implemented in various modes without changing the gist of the invention. Further, the technical scope of the present invention extends to an equivalent range.
図 1は、 本発明の発明を実施するために使用可能なドライエッチング装置の一 例を示す概略図である。 この装置には、 エッチング室 1、 高周波電源 2、 排気装 置、 プラズマ発生ガス導入装置が含まれている。  FIG. 1 is a schematic diagram showing an example of a dry etching apparatus that can be used to carry out the present invention. This equipment includes an etching chamber 1, a high-frequency power supply 2, an exhaust device, and a plasma generating gas introduction device.
より具体的には、 例えばステンレス製のエッチング室 1の内部には、 正負一対 の平行平板型電極 1 1, 1 2が対向して設置されている。 両電極は、 一般には、 陽極 1 1がアース電位に保たれる一方、 陰極 1 2には高周波電力が印加される。 陰極 1 2はプラズマガスにより激しくたたかれ、 温度が上昇する。 このため、 陰 極 1 2を冷却するために、 裏面側に冷却水が流通できるように中空構造とされて いる。 陰極 1 2には、 1 3 . 5 6 MH zの高周波電源 2がマッチングボックス 2 2を介して接続されており、 プラズマが制御される。 More specifically, for example, a pair of positive and negative parallel plate type electrodes 11 and 12 are installed in an etching chamber 1 made of stainless steel so as to face each other. Both electrodes are generally The high frequency power is applied to the cathode 12 while the anode 11 is kept at the ground potential. The cathode 12 is hit hard by the plasma gas and the temperature rises. For this reason, in order to cool the cathode 12, a hollow structure is provided so that cooling water can flow on the back side. The cathode 12 is connected to a high frequency power supply 2 of 13.56 MHz via a matching box 22 to control the plasma.
エッチング室 1には、 排気管 3が設けられている。 排気管 3には、 ドライボン プ、 ターボポンプ等が組み合わされた排気装置 (図示せず) が接続さている。 こ の排気装置の駆動により、 エッチング室 1の内部空間は、 例えば 1 0— 4 P a以下 の真空にすることができる。 このエッチング室 1内の圧力は、 排気管 3の中途に 配設された例えば圧力調整バルブ 3 3により調整され、 常に一定範囲の真空度に 保たれる。 An exhaust pipe 3 is provided in the etching chamber 1. The exhaust pipe 3 is connected to an exhaust device (not shown) in which a dry pump, a turbo pump, and the like are combined. By driving the exhaust device, the internal space of the etching chamber 1 can be evacuated to, for example, 10 to 4 Pa or less. The pressure in the etching chamber 1 is adjusted by, for example, a pressure adjusting valve 33 provided in the middle of the exhaust pipe 3, and is always kept at a certain degree of vacuum.
エッチング室 1には、 さらに各プラズマ発生ガスをエッチング室 1內に導入す るためのガス導入管 4 a, 4 bが設けられている。 これらのガス導入管 4 a, 4 bの他端側は、 外部のプラズマ発生ガス源 (図示せず) に接続されている。 より 具体的には、 エッチング室 1には、 エッチング用ガス (例えば、 塩素ガス) を導 入するための第 1のガス導入管 4 aと、 その他のガス (必要な場合に、 第 1のガ スと混合させてドライエッチングを行うためのガス) を導入するための第 2のガ ス導入管 4 bとが設けられている。 各ガスの流量はガス導入管 4 a , 4 bにそれ ぞれ配設されたマスフローコントローラー 4 4 a, 4 4 bにより制御される。 な お、 第 1のガスのみをプラズマ発生ガスとしてエッチング室 1內に導入する場合 には、 ガス導入管 4 4 bを省略、 または閉鎖しておく。  The etching chamber 1 is further provided with gas introduction pipes 4a and 4b for introducing each plasma generating gas into the etching chamber 1 室. The other end sides of these gas introduction pipes 4a and 4b are connected to an external plasma generating gas source (not shown). More specifically, the etching chamber 1 has a first gas introduction pipe 4a for introducing an etching gas (for example, chlorine gas) and another gas (a first gas when necessary). And a second gas introducing pipe 4b for introducing a gas for performing dry etching by mixing with a gas. The flow rate of each gas is controlled by mass flow controllers 44a and 44b provided in the gas introduction pipes 4a and 4b, respectively. When only the first gas is introduced into the etching chamber 1 內 as a plasma generating gas, the gas introduction pipe 44b is omitted or closed.
次に、 上記のドライエッチング装置を用いて、 III 族窒化物半導体膜をエッチ ングしてナノピラーを形成する操作について説明する。 なお以下の例では、 第 1 の半導体層〜第 3の半導体層を構成する半導体として、 それぞれ n— G a N、 I n G a N、 p— G a Nを例示したが、 本発明の技術的範囲はこれに止まらず、 式 A 1 XG a y I n ^N (0≤x≤l , 0≤y^ l かつ、 0≤x+y≤l) で表わされる窒化物 半導体を用いることができる。 なおそのときには、 第 2の半導体層のバンドギヤ ッブエネルギーが、 第 1及び第 3の半導体層のバンドギャップエネルギーよりも 小さい組合せを選択することが好ましい。 まず、 III 族窒化物半導体膜の構造について、 図 2を例として、 説明する。 こ の III族窒化物半導体膜は、 図 2 (a) に示すように、 例えばサファイア基板 5 1の上面に設けられたバッファ層 5 2の上面側に設けられている。 そのバッファ 層 5 2 (例えば、約 20 nm程度の厚さの A 1 Nを用いることができる。) の上面 には、 例えば MOVP E法によって、 下層から順に、 第 1の半導体層 5 3 (例え ば、 n— G a Nを用いることができる。)、 第 2の半導体層 54 (例えば、 I nG a Nを用いることができる。)、 及び第 3の半導体層 5 5 (例えば、 ノンドープの G a Nまたは I nG a N、 p型の G a Nまたは I nG a N、 または A 1 I n G a Nを用いることができる。)からなる少なく とも三層の ΙΠ族窒化物半導体膜 6 0 が形成されている (図 2 (b))。 Next, an operation of forming a nanopillar by etching the group III nitride semiconductor film using the above dry etching apparatus will be described. In the following examples, n-GaN, InGaN, and pGaN are exemplified as semiconductors constituting the first to third semiconductor layers, respectively. The scope is not limited to this, and use a nitride semiconductor represented by the formula A 1 X G a y I n ^ N (0≤x≤l, 0≤y ^ l and 0≤x + y≤l) Can be. At that time, it is preferable to select a combination in which the bandgap energy of the second semiconductor layer is smaller than the bandgap energy of the first and third semiconductor layers. First, the structure of the group III nitride semiconductor film will be described with reference to FIG. As shown in FIG. 2A, the group III nitride semiconductor film is provided on the upper surface of a buffer layer 52 provided on the upper surface of a sapphire substrate 51, for example. On the upper surface of the buffer layer 52 (for example, A 1 N having a thickness of about 20 nm can be used), a first semiconductor layer 53 (for example, For example, n-GaN can be used.), The second semiconductor layer 54 (for example, InGaN can be used), and the third semiconductor layer 55 (for example, undoped Gn). a N or InG aN, p-type G aN or InG aN, or A 1 InG aN can be used.) Are formed (Fig. 2 (b)).
ここで、 第 1の半導体層 5 3の厚さは約数百〜数千 nm、 第 2の半導体層 54 (最終的に量子ドットとなり、発光層を形成する。) の厚さは約数 nm〜約 6 O n m、 第 3の半導体層 5 5の厚さは約数 nm〜百 nm程度であることが好ましい。 また、 第 2の半導体層 54のバンドエネルギーギャップは、 第 1の半導体層 5 3 及び第 3の半導体層 5 5のバンドエネルギーギヤップよりも小さいものを選択す ることが好ましい。 さらに、 第 2の半導体層 54と第 3の半導体層 5 5を積層す ることも可能である。  Here, the thickness of the first semiconductor layer 53 is about several hundreds to several thousand nm, and the thickness of the second semiconductor layer 54 (which eventually becomes a quantum dot and forms a light emitting layer) is about several nm. It is preferable that the thickness of the third semiconductor layer 55 is about several nm to about 100 nm. In addition, it is preferable that the band energy gap of the second semiconductor layer 54 is selected to be smaller than the band energy gap of the first semiconductor layer 53 and the third semiconductor layer 55. Further, the second semiconductor layer 54 and the third semiconductor layer 55 can be stacked.
このような III族窒化物半導体膜 6 0を備えたサンプル 1 0 1 (III族窒化物 半導体膜 6 0と基板 5 1とを含む全体の構造物を示す) をエッチングするには、 各陰極 1 2の上面側に、 固体としての石英基板 1 02を載置し、 その上面または 周辺に、 例えばウェハの形態にあるサンプル 1 0 1を載置する。 なお、 サンプル 1 01を石英基板 1 02の上面に載置する場合には、 石英基板 1 02の断面形状 はサンプル 1 0 1の断面形状よりも大きく しておき、 石英基板 1 02がエツチン グガスに曝されるようにしておく。  To etch the sample 101 (showing the entire structure including the group III nitride semiconductor film 60 and the substrate 51) provided with such a group III nitride semiconductor film 60, each cathode 1 A quartz substrate 102 as a solid is placed on the upper surface side of 2, and a sample 101 in the form of a wafer, for example, is placed on or around the upper surface thereof. When the sample 101 is placed on the upper surface of the quartz substrate 102, the cross-sectional shape of the quartz substrate 102 should be larger than the cross-sectional shape of the sample 101, and the quartz substrate 102 is used as an etching gas. Keep exposed.
ついで、 排気装置を駆動してエッチング室 1の内部を 1 0—4P aのオーダーの 圧力となるまで排気する。 エッチング室 1の内部の真空度が安定した後、 ガス導 入管 4 aから塩素ガスを所定の流量となるようにマスフローコントローラー 44 aで制御しつつ、 エッチング室 1の内部空間に導入する。 このとき同時に、 排気 装置によりエッチング室 1の内部を排気し、 圧力調整バルブ 3 3を調整してエツ チング室 1の内部圧力を所定の圧力に制御する。 エッチング室 1の内部圧力が安 定した後、高周波電源 2からマッチングボックス 22を介して電圧を印加すると、 両電極 1 1, 1 2間に塩素ガスプラズマが発生する。 Then, by driving the exhaust device evacuated to the interior of the etching chamber 1 a 1 0- 4 P a order pressure of. After the degree of vacuum inside the etching chamber 1 is stabilized, the chlorine gas is introduced from the gas inlet pipe 4a into the internal space of the etching chamber 1 while being controlled by the mass flow controller 44a to have a predetermined flow rate. At the same time, the inside of the etching chamber 1 is exhausted by the exhaust device, and the pressure adjusting valve 33 is adjusted to adjust The internal pressure of the chucking chamber 1 is controlled to a predetermined pressure. When a voltage is applied from the high-frequency power supply 2 via the matching box 22 after the internal pressure of the etching chamber 1 is stabilized, chlorine gas plasma is generated between the electrodes 11 and 12.
この塩素ガスプラズマは、 石英基板 1 0 2をエッチングしつつ、 サンプル 1 0 1の III族窒化物半導体膜 6 0をスパッタリング及びエッチングする (ナノビラ 一作製工程)。 こうしてエッチング操作により、 III族窒化物半導体膜 60の表面 には、 図 3 (c ) に示すように、 ナノピラー 50が形成される。 このナノピラー 5 0の直径は約 1 0 nm〜約 200 nmとなる。 また、 隣り合うナノピラー 50 同士の間隔は、 平均して約 1 00 nm程度となる。 なお、 ナノピラー 50の直径 および間隔は、 エッチング時の条件によって、 適当に変更することもできる。 次いで、 図 3 (d) に示すように、 ナノピラー 50の隙間に新たな III族窒化 物半導体を充填させて充填層 5 8を形成する(充填工程)。その充填方法としては、 既述のように MO V P E法、 HVP E法、 または MB E法などが挙げられる。 なお、 ナノピラー 50を III族窒化物半導体膜 60の全面に設ける必要がない 場合には、 図 4に示すように、 予めエッチングする必要のない場所にマスク 57 (例えば、 S i 02からなるマスク) を施した状態で、 ドライエッチングを行うこ とにより、 所望の位置にのみナノピラー 50を形成することができる。 The chlorine gas plasma sputters and etches the group III nitride semiconductor film 60 of the sample 101 while etching the quartz substrate 102 (nanofabric one manufacturing step). By the etching operation, nanopillars 50 are formed on the surface of the group III nitride semiconductor film 60, as shown in FIG. 3 (c). The diameter of the nanopillars 50 ranges from about 10 nm to about 200 nm. Also, the spacing between adjacent nanopillars 50 is about 100 nm on average. In addition, the diameter and the interval of the nanopillars 50 can be appropriately changed depending on the conditions at the time of etching. Next, as shown in FIG. 3D, a gap between the nanopillars 50 is filled with a new group III nitride semiconductor to form a filling layer 58 (filling step). As the filling method, the MO VPE method, the HVP E method, the MBE method and the like are mentioned as described above. When there is no need to provide the nano-pillars 50 on the entire surface of the group III nitride semiconductor layer 60, as shown in FIG. 4, consists of a mask 57 (e.g., S i 0 2 requires no place to advance the etching mask By performing the dry etching in the state where the process is performed, the nano pillars 50 can be formed only at desired positions.
こうして、 III族窒化物半導体からなる量子ドット (ΠΙ族窒化物量子ドット) 5 6を製造することができる。 なお、 図 6に示すように、 量子ドット 5 6の上下 に正負一対の電極 6 1、 6 2を設けることにより、 発光デバイスを製造すること ができる。 また、その際には、充填層 5 8の上面側に更に半導体層 5 9 (例えば、 p— G a Nを用いることができる。) を積層し、その半導体層 5 9の上面に電極 6 1を設けることが好ましい。  Thus, a quantum dot (group III nitride quantum dot) 56 made of a group III nitride semiconductor can be manufactured. As shown in FIG. 6, a light emitting device can be manufactured by providing a pair of positive and negative electrodes 61 and 62 above and below a quantum dot 56. In this case, a semiconductor layer 59 (for example, p-GaN can be used) is further laminated on the upper surface side of the filling layer 58, and the electrode 61 is formed on the upper surface of the semiconductor layer 59. Is preferably provided.
また、 図 3 (d) に示す状態から、 その上面側に、 新たに三層からなる III族 窒化物半導体 (例えば、 n— G a N、 I nG a N、 及び!)— G a N) を積層して III 族窒化物半導体膜を形成し、 その半導体膜に対して、 ナノピラー作製工程お よび充填工程を上記と同様にして操り返すことにより、 図 7に示すように、 多層 量子ドット 70を容易に製造することができる。 実施例 In addition, from the state shown in FIG. 3 (d), on the upper surface side, a group III nitride semiconductor (eg, n—GaN, InGaN, and!) — GaN) composed of three new layers is provided. Are stacked to form a group III nitride semiconductor film, and the nanopillar fabrication process and the filling process are repeated for the semiconductor film in the same manner as described above. Can be easily manufactured. Example
次に、 本発明を実施例により説明する。 なお以下の各実施例において、 前述の エッチング装置 (図 1) を使用した。  Next, the present invention will be described with reference to examples. In each of the following examples, the above-described etching apparatus (FIG. 1) was used.
実施例 1  Example 1
サファイアく 000 1〉基板上に、 バッファ層 52を介して、 例えば MOVP E法により n— G a N5 3 (本発明における第 1の半導体層に該当する。)、 I n G a N 54 (本発明における第 2の半導体層に該当する。)、 及び p— G a N 5 5 (本発明における第 3の半導体層に害とする。)を成長させた ΠΙ族窒化物半導体 膜 60を有するものをエッチング用のサンプル 1 0 1として用いた。  On the sapphire 000 1> substrate, via a buffer layer 52, for example, n-GaN53 (corresponding to the first semiconductor layer in the present invention), InGaN54 ( A group III nitride semiconductor film 60 on which p-GaN 55 (which is harmful to the third semiconductor layer in the present invention) is grown. Was used as a sample 101 for etching.
ここで、 n— G a N 5 3及び p— G a N 5 5の厚さは約 300 nm、 I nG a N 54の厚さは約 20 nmとした。 このサンプル 10 1の上面には、 例えば R F スパッタ法により、 S i 02を約 300 nmの厚さで堆積させ、通常のフォトリソ グラフィ技術により、 < 1 1 00 >方向に 5 μ mのライン及びスペースパターン を作製して、 エッチング用サンプル 1 0 1とした。 Here, the thickness of n-Gan53 and p-gan55 was about 300 nm, and the thickness of InGa54 was about 20 nm. On the upper surface of the sample 10 1, for example, by RF sputtering, depositing a S i 0 2 at a thickness of about 300 nm, by conventional photolithography graphic techniques, <1 1 00> direction of 5 mu m line and A space pattern was prepared and used as an etching sample 101.
エッチング室 1のステージ上に、 石英基板 1 02を設置した。 この石英基板 1 02の周辺または上面に、 エッチング用サンプル 1 0 1を載置した。  A quartz substrate 102 was set on the stage of the etching chamber 1. An etching sample 101 was placed around or on the upper surface of the quartz substrate 102.
その後、 真空ポンプでエッチング室 1を 5 X 1 0— 4 P aまで排気した。 エッチ ング室 1内部の真空度が安定した後、 エッチング室 1の内部にガス導入管 4 aか ら塩素ガスをマスフローコントローラー 44 aで制御しながら、 30m l / i nの流量で導入した。 これと同時に、 真空ポンプによりエッチング室 1の内部を 排気し、 圧力調整バルブ 33を調整して、 エッチング室 1内を 6 P aの減圧に制 御した。 Was then evacuated etching chamber 1 to 5 X 1 0- 4 P a vacuum pump. After the degree of vacuum in the etching chamber 1 was stabilized, chlorine gas was introduced into the etching chamber 1 from the gas introduction pipe 4a at a flow rate of 30 ml / in while being controlled by the mass flow controller 44a. At the same time, the inside of the etching chamber 1 was evacuated by a vacuum pump, and the pressure regulating valve 33 was adjusted to control the pressure inside the etching chamber 1 to 6 Pa.
エッチング室 1内の真空度が安定したことを確認してから、 高周波電源 2によ り電圧を加え、 両電極 1 1, 1 2間にプラズマを発生させ、 1 00W (なお、 面 積は 1 77 cm2) の条件で約 4分間のドライエッチングを行った。 After confirming that the degree of vacuum in the etching chamber 1 was stable, a voltage was applied from the high-frequency power source 2 to generate plasma between the electrodes 11 and 12 and 100 W (the area was 1 Dry etching was performed for about 4 minutes under the condition of 77 cm 2 ).
ドライエッチング後、 サンプノレ 1 0 1をエッチング室 1から取り出し、 エッチ ング面を走查型電子顕微鏡 (S EM) で観察した。 図 5には、 III 族窒化物半導 体膜のエッチング面の構造を S EMにより観察した写真を示す図を示した。 本実 施例によるナノピラーの製造過程については、 例えば次のように考えることがで きる。 すなわち、 プラズマ中の塩素イオンが G a N周辺の石英基板に衝突し、 ス パッタリング効果により S i 02がプラズマ中に飛び出す。そのうち一部の S i O 2はイオン化されて、負にバイアスしている G a N膜上に再付着するものと考えら れる。 ここで、 S i 02は G a Nに比べると、 塩素ガスプラズマに対するエツチン グレートが 10分の 1〜20分の 1程度と低いために、微小なマスクとして働くこと から、 サンプル 1 0 1の表面に微小な凹凸構造が形成される。 After the dry etching, the sample No. 101 was taken out of the etching chamber 1, and the etched surface was observed with a scanning electron microscope (SEM). FIG. 5 shows a photograph showing the structure of the etched surface of the group III nitride semiconductor film observed by SEM. The manufacturing process of nanopillars according to this embodiment can be considered as follows, for example. Wear. That is, chlorine ions in the plasma collide with the quartz substrate in the vicinity of GaN, and S i 0 2 jumps out into the plasma due to the sputtering effect. Some of the SiO 2 is likely to be ionized and redeposited on the negatively biased GaN film. Here, when S i 0 2 is compared to G a N, since one degree and low 20 minutes 10 minutes Etsuchin Great to chlorine gas plasma, since acting as minute masks, Sample 1 0 1 A minute uneven structure is formed on the surface.
S i o2が付着してわずかに凸となった箇所は凹部に比べると、電界が高くなる ため引き続いて S i o2が付着する確率が高くなると考えられる。このようにして S i o2の再付着と塩素ガスプラズマによるエッチングが繰り返し並行して進ん だ結果、 ナノピラー構造が得られたものと考えられる。 しかしながら、 XP S分 析の結果では、 サファイア上では Siが検出されたが、 G a N上では Siが検出さ れなかった。 このため現在のところ、 本実施例の方法では、 必ずしもナノピラー の製造過程については明確ではない。 When locations S io 2 becomes slightly convex adhere than the recess, considered as the probability of S io 2 Subsequently the electric field becomes high adheres increases. It is thought that the nanopillar structure was obtained as a result of the re-deposition of Sio 2 and the etching with chlorine gas plasma repeatedly proceeding in parallel. However, the results of the XPS analysis showed that Si was detected on sapphire, but not on GaN. Therefore, at present, in the method of the present embodiment, the manufacturing process of the nanopillars is not always clear.
また、 ナノピラー構造は、 その太さが数 +nn!〜 1 00 nmの程度であり、 そ の高さが約 500ナノメータであった。 また、 ナノピラーの密度は、 およそ 106 〜^" !!!2のオーダーであった。 なお、 ナノピラーの高さは、 エッチング時間に 大きく依存することが判明した。 The nanopillar structure has a thickness of + nn! The height was about 100 nm, and the height was about 500 nanometers. In addition, the density of the nanopillars was on the order of 10 6 to ^ "!!! 2. It was found that the height of the nanopillars was greatly dependent on the etching time.
こうして作製されたナノピラー構造の隙間に、 例えば MOV P E法によって、 新たな III族窒化物半導体 (G a N) を充填して充填層 5 8を形成することがで きた (図 3 (d) を参照)。 その際の条件としては、 トリメチルガリウム (TMG) を 48 i mol/min、 NH3を 11/minで流し、 1 000°C、 300Torrとした。 また、 図 3 ( d) に示す状態から、 その上面側に新たに n— G a N、 I n G a N、 及び p— G a Nを積層し、 その積層された半導体膜に対して、 ドライエッチ ング操作によるナノビラ一作製および、 ナノピラーの隙間を充填する操作を繰り 返すことにより、 図 7に示す多層量子ドッ ト 70を製造することもできる。 The gap between the nanopillar structures fabricated in this way was filled with a new group III nitride semiconductor (G a N) by, for example, MOV PE method to form a filling layer 58 (Fig. 3 (d) reference). The conditions at this time, trimethyl gallium (TMG) flowed at 48 i mol / min, the NH 3 11 / min, 1 000 ° C, was 300 Torr. In addition, from the state shown in FIG. 3D, n-GaN, InGaN, and pGaN are newly laminated on the upper surface side, and the laminated semiconductor film is The multilayer quantum dot 70 shown in FIG. 7 can also be manufactured by repeating the operation of fabricating the nano-village by the dry etching operation and filling the gap between the nano-pillars.
このように、 本実施例によれば、 III 族窒化物半導体膜 60の表面にナノビラ 一 5 6を容易に形成することができ、 そのナノピラー 56の隙間を新たな III族 窒化物半導体で充填することにより、 効率よく ΙΠ族窒化物量子ドット 56を製 造することができる。また、このような ΙΠ族窒化物量子ドット 56を利用して、 大面積を備えた発光ダイォードディスプレイや、 電界放出型冷陰極による大面積 の蛍光ディスプレイを製造することも可能となる。 As described above, according to the present embodiment, nano-pillars 56 can be easily formed on the surface of the group III nitride semiconductor film 60, and the gaps between the nanopillars 56 are filled with the new group III nitride semiconductor. This makes it possible to efficiently manufacture the group III nitride quantum dots 56. Also, by utilizing such a group III nitride quantum dot 56, It is also possible to manufacture large-area light-emitting diode displays and large-area fluorescent displays using field emission cold cathodes.
また特に、 第 2の半導体層として、 ハンドギャップエネルギーの異なる高さが 約 1 n m〜約 1 0 0 n mの半導体層を積層した多重量子構造を用いた場合、 多層 構造の I I I族窒化物量子ドッ トの製造が可能となり、 そのような多層量子ドッ ト では、 側面がほぼ垂直で高さの揃った量子ドッ トとなるので、 互いの量子ドッ ト が励起しあって、 高効率な発光が可能となる。  In particular, when a multi-quantum structure in which semiconductor layers having different hand gap energies and having a height of about 1 nm to about 100 nm are stacked is used as the second semiconductor layer, a group III nitride quantum dot having a multilayer structure is used. In such a multi-layer quantum dot, the quantum dots are almost vertical on the sides and are uniform in height, so that the quantum dots excite each other, enabling efficient light emission Becomes

Claims

請 求 の 範 囲 The scope of the claims
1. 以下の各工程、 ①第 1の半導体層と第 2の半導体層と第 3の半導体層との 少なく とも三層を積層させて III族窒化物半導体膜を作製する積層工程、 ②前記 III 族窒化物半導体膜をドライエッチングすることにより、 ナノピラーを作製す るナノビラ一作製工程、 ③前記ナノビラ一の隙間に新たな半導体を成長させて充 填層を成長させる充填工程を含むことを特徴とする III族窒化物量子ドッ トの製 造方法。  1. Each of the following steps: (1) a laminating step of laminating at least three layers of a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer to produce a group III nitride semiconductor film; A nano-pillar manufacturing process for manufacturing nanopillars by dry-etching the group-III nitride semiconductor film; and ③ a filling process for growing a new semiconductor in a gap between the nano-pillars and growing a filling layer. Manufacturing method of group III nitride quantum dots.
2. 上記②のナノピラー作製工程は、 III族窒化物半導体膜の表面に、 その III 族窒化物半導体膜に比べてェッチングレートが小さぃェツチング遅速物質を存在 させた状態で、 前記 ΙΠ族窒化物半導体膜をドライエッチングすることを特徴と する請求項 1に記載の III族窒化物量子ドットの製造方法。  2. The nanopillar manufacturing step of the above (1) is performed in a state where a slow-etching material having a smaller etching rate than that of the group III nitride semiconductor film is present on the surface of the group III nitride semiconductor film. 2. The method for producing a group III nitride quantum dot according to claim 1, wherein the nitride semiconductor film is dry-etched.
3. 前記第 2の半導体層のバンドギャップエネルギーは、 前記第 1の半導体層 のバンドギヤップエネルギー及び前記第 3の半導体層のバンドギヤップエネルギ —よりも小さいことを特徴とする請求項 1または請求項 2のいずれかに記載の III族窒化物量子ドッ トの製造方法。  3. The bandgap energy of the second semiconductor layer is smaller than the bandgap energy of the first semiconductor layer and the bandgap energy of the third semiconductor layer. 3. The method for producing a group III nitride quantum dot according to any one of 2.
4. 前記①積層工程、 前記②ナノピラー作製工程、 及び前記③充填工程を繰り 返すことにより、 多層量子ドッ トを作製することを特徴とする請求項 1〜請求項 3のいずれかに記載の ΠΙ族窒化物量子ドットの製造方法。  4. The multilayer quantum dot according to any one of claims 1 to 3, wherein the multilayer quantum dot is manufactured by repeating the above (1) lamination step, (2) nanopillar manufacturing step, and (3) filling step. Method for producing group III nitride quantum dots.
5. 量子ドッ トの分布密度が 1 06個ノ0: 1112〜 1 012個 Zc m2であることを特 徴とする III族窒化物素子。 5. quantum dot distribution density of 1 0 6 Bruno 0: 1 11 2 to 1 0 12 Zc III nitride device according to feature that m is 2.
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