WO2003007374A1 - Module hybride - Google Patents

Module hybride Download PDF

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Publication number
WO2003007374A1
WO2003007374A1 PCT/JP2002/007090 JP0207090W WO03007374A1 WO 2003007374 A1 WO2003007374 A1 WO 2003007374A1 JP 0207090 W JP0207090 W JP 0207090W WO 03007374 A1 WO03007374 A1 WO 03007374A1
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
heat
circuit board
hybrid module
circuit
Prior art date
Application number
PCT/JP2002/007090
Other languages
English (en)
Japanese (ja)
Inventor
Takao Miwa
Toshiya Satoh
Masahiko Ogino
Toshihide Nabatame
Shigehisa Motowaki
Seiji Watahiki
Hideshi Fukumoto
Yoko Furukawa
Hitoshi Akamine
Tsuneo Endo
Masaharu Kubo
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001211537A external-priority patent/JP2003031757A/ja
Priority claimed from JP2001211534A external-priority patent/JP2003031756A/ja
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO2003007374A1 publication Critical patent/WO2003007374A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate

Definitions

  • the present invention relates to a module on which a circuit pattern is formed, and more particularly to a hybrid module on which an integrated circuit having heat generation and an integrated passive element are mounted.
  • a conventional high-power module with a heat-generating integrated circuit such as a field-effect transistor or a power semiconductor mounted on a circuit board has a heat-dissipating structure that connects a heat-dissipating fin to the heat-generating integrated circuit.
  • a common method is to mount an integrated circuit having heat on a circuit board face-up and radiate heat from the entire back surface of the integrated circuit to the circuit board.
  • Japanese Patent Application Laid-Open No. H10-509926 discloses that a heat-generating circuit component is mounted on a surface of the circuit board opposite to the parent circuit board, and the heat generated by the circuit component is applied to the parent circuit board.
  • a hybrid module in which the heat is transmitted directly or via a film-like heat conductive member. The heat generated by the heat-generating integrated circuit is transferred to the parent circuit board and dissipated.
  • the heat dissipation method using the heat dissipation fins of the prior art had a problem that the installation of the heat dissipation fins increased the volume of the hybrid module and was not suitable for miniaturization. Also, when mounting on a circuit board face up, it is necessary to provide a bonding area on the circuit board side by wire bonding connection, which is not suitable for miniaturization. Also, wire bonding There is a problem with high inductance. The method of mounting the heat-generating integrated circuit and the circuit components on the opposing surfaces of the circuit board has a problem that the height cannot be reduced due to the height of the circuit components.
  • An object of the present invention is to provide a heat dissipating element which is excellent in heat dissipation and is suitable for miniaturization and reduction in height, in view of the problem of a conventional hybrid module mounting a heat-generating integrated circuit. To provide a hybrid module. Disclosure of the invention
  • the object is to provide a circuit board having a concave portion, a heat-generating integrated circuit and an integrated passive element mounted in the concave portion in a face-down manner.
  • the problem is solved by a hybrid module characterized by being performed on the same side as the integrated circuit. That is, by mounting an integrated passive element in which a heat-generating integrated circuit and a circuit component are integrated in a concave portion provided in the circuit board, the circuit component conventionally mounted on the circuit board becomes unnecessary. As a result, the height is reduced. Further, the heat generated by bringing the back surface of the heat-generating integrated circuit into contact with the external substrate can be efficiently dissipated.
  • the purpose can also be achieved by mounting the integrated passive element in a recess formed on a surface opposite to the recess in which the integrated circuit having heat generation is mounted. Further, the purpose can be achieved even if the integrated passive element is mounted in a concave portion formed on the surface opposite to the same side surface of the concave portion in which the integrated circuit having heat generation is mounted.
  • the problem can also be solved by thermally connecting the heat-generating integrated circuit and the external substrate via a thermally conductive thin film.
  • the object is to provide a circuit board having at least one recess, An integrated circuit having at least one heat-generating element mounted in the recess in a face-down manner; and an integrated circuit having at least one integrated passive element and having an electric connection with an external substrate having the heat-generating property.
  • the problem is solved by a hybrid module in which the integrated circuit and the external substrate are in contact with each other directly or via a conductive material on the same surface. That is, by mounting a heat-generating integrated circuit in a recess provided in a circuit board and mounting the integrated passive element on a surface opposite to the surface on which the heat-generating integrated circuit is mounted, the conventional circuit board The circuit components mounted above are not required. This achieves a reduction in height. Further, heat generated by bringing the back surface of the heat-generating integrated circuit into contact with the external substrate can be efficiently dissipated.
  • the problem can also be solved by thermally connecting the heat-generating integrated circuit and the external substrate via a thermally conductive thin film.
  • the integrated passive element used in the present invention includes a plurality of elements selected from a capacitor element, an inductor element, and a resistance element, which are composed of an organic insulating film, a metal wiring, and a dielectric material on an insulating substrate.
  • an integrated passive element with high accuracy and high integration can be formed by using a thin film wiring method.
  • the integrated passive device formed in this way has a mounting density 10 times or more higher than that of conventional 105 circuit components (capacitors, inductors, resistors).
  • the mounting density indicates the number of circuit components that can be mounted per unit area.
  • a capacitor element refers to a structure in which one or more capacitor elements with a dielectric material made of an inorganic material sandwiched between two metal electrodes and a structure in which a dielectric material made of an organic material is sandwiched between two metal electrodes.
  • the metal electrode is preferably a conductive material having a low electric resistance.
  • gold examples include copper, nickel, aluminum, platinum, tungsten, molybdenum, iron, niobium, titanium, nickel / chromium alloy, iron / nickel / chromium alloy, and tantalum nitride.
  • copper is preferable because of its low electric resistance.
  • the surface of the metal electrode needs to be flat, and the surface irregularities are preferably 1/25 or less of the thickness of the dielectric material.
  • a resist pattern is formed and formed by dry or hot etching, or after forming a resist pattern, It may be formed by electrolytic or electroless plating.
  • the inorganic material is not limited as long as it is generally used as a dielectric material for capacitors, and examples thereof include oxides such as Ta, Mg, and Sr.
  • oxides such as Ta, Mg, and Sr.
  • Other T a 2 0 5, B s T, S r T i 0 3, T I_ ⁇ 2, Mn0 25 Upsilon 2 ⁇ 3, S n0 2, ⁇ g ⁇ i 0 3 oxide such specifically, Bali Umuchi Yun acid compound Ya burr Umuchi Yun acid compound compound doped zirconium or tin compounds, W0 3, S r 0, mixed barium / scan oxides of strontium, BaW0 4, C ⁇ 0 2, etc. Is mentioned.
  • a dry method such as a sputtering method or a plasma CVD method, and a jet method such as an anodic oxidation method can be used.
  • the inductor element of the present invention is not particularly limited as long as it is a so-called inductive circuit element.
  • a spiral type formed on a plane, a plurality of such elements are stacked, or a solenoid type is used.
  • the material of the inductor element and the metal wiring may be the same material or different materials, and are appropriately selected depending on electric conductivity, adhesion to surrounding materials, forming method, and the like.
  • the forming method is not particularly limited. For example, Cu May be formed, and T i, Cr, etc. may be formed at the interface in consideration of the adhesiveness with surrounding materials.
  • a thin film serving as a seed film may be formed by Cu or the like by a sputtering method or the like, and then formed by an electrolytic plating method or the like.
  • a patterning method for the wiring and the inductor element a general wiring patterning method such as an etching method and a lift-off method can be used. Further, it may be formed by a printing method using a resin base containing a metal such as Ag. Further, when the formation temperature of the inorganic dielectric is high, a metal having high oxidation resistance and heat resistance such as Pt can be used.
  • the resistance element of the present invention has a structure in which a resistance material is sandwiched between two metal electrodes, and the resistance material is not particularly limited as long as it is generally used as a resistance material.
  • the resistance material is not particularly limited as long as it is generally used as a resistance material.
  • C r S i, T i N or the like is used.
  • the formation method is not particularly limited, and for example, a sputtering method, a plasma CVD method, or the like is used.
  • the organic insulating material is not particularly limited as long as it is an organic material generally used for semiconductor applications, and may be either thermosetting or thermoplastic.
  • polyimide, polycarbonate, polyester, polytetrafluoroethylene, polyethylene, polypropylene, polyvinylidene fluoride, cellulose acetate, polysulfone, polyacrylonitrile, polyamide, polyamide imide, epoxy, maleimid , Phenol, cyanate, polyolefin, polyurethane and these compounds can be used.
  • a mixture of these compounds with a rubber component such as acrylic rubber, silicone rubber, or butyryl butadiene rubber, or an inorganic filer such as an organic compound filler such as polyimide filler may be used.
  • photosensitive materials including the above materials May be formed.
  • polyimide resins are excellent in heat resistance and chemical resistance, and those imparted with photosensitivity are also excellent in workability and are preferred.
  • benzocyclopentene resin has a low dielectric loss tangent and is preferable when the capacitor of the present invention is used as a high frequency component.
  • a low dielectric loss tangent resin composition containing a cross-linking component having a plurality of styrene groups represented by the following general formula and further containing a polymer having a weight average molecular weight of 500 or more has a low transmission loss. Reduced and preferred.
  • a hydrocarbon skeleton containing an alkylene group such as methylene and ethylene is preferable.
  • an alkylene group such as methylene and ethylene
  • 1,2-bis (p-biphenyl) ethane, 1,2-bis (m-biphenyl) ethane and its analogs 1,2-bis (p-biphenyl) ethane, 1,2-bis (m-biphenyl) ethane and its analogs, homopolymers of divinylbenzene having a vinyl group in the side chain, styrene, etc.
  • oligomers such as copolymers of the above.
  • R represents a hydrocarbon skeleton which may have a substituent
  • R 1 represents any of hydrogen, methyl and ethyl
  • m represents 1 to 4
  • n represents an integer of 2 or more. I forgot.
  • a pattern printing method such as a printing method, an ink jet method, an electronic photographic method, etc .
  • the shape There is a method of combining them and a method of combining them.
  • epoxy resin unsaturated polyester resin, epoxy resin resin, maleimide resin, maleimide epoxy resin, cyanate ester resin, cyanate ester epoxy resin, ester cyanide cyanide resin, phenolic resin Resin, diallyl phthalate resin, urethane resin, cyanamide resin, maleimide cyanamide resin, etc., thermosetting resins, materials combining two or more of the above resins, and inorganic fillers. Materials may be used. It is also possible to impart photosensitivity to the resin and control the shape of the stress buffer layer by a predetermined exposure and development process.
  • the insulating substrate of the present invention is not particularly limited as long as it can form an integrated passive element and can withstand use conditions.
  • a glass substrate with a smooth surface is used, a fine pattern can be formed with high precision, excellent heat resistance and chemical resistance, and an excellent integrated passive element with low dielectric loss can be obtained.
  • the smooth surface refers to a surface having an average roughness Ra of 20 m or less.
  • the glass material is not particularly limited as long as it is a glass substrate having a high insulating property, and is selected in consideration of strength, workability, and the like.
  • the rare earth element L n 2 0 3 (L n is a rare earth element) in terms of oxide of, and for the entire glass containing 0.5 to 20 wt%, S i O 2
  • Other ingredients 40-80 wt%
  • B 2 0 3 0 ⁇ 2 0 wt%
  • a 1 2 0 3: 0 ⁇ comprises 1 7 wt%, cut 11 2 0 + RO: 1 0 ⁇ 3 0 wt% It is desirable that By doing so, the strength of the glass substrate is greatly improved, and workability is significantly improved.
  • the conductive thin film used in the present invention there is no particular limitation on the conductive thin film used in the present invention, as long as the conductive thin film has predetermined conductivity. Die bonding materials typified by silver paste, solder, and conductive films that combine resin and metal are common.
  • circuit components it is also possible to mount circuit components together within a range that does not hinder miniaturization of the circuit board. At this time, it is desirable from the viewpoint of reducing the height if a recess is provided in the circuit board and mounted inside the circuit board.
  • a resin board, a thick-film wiring board, or the like can be used as the circuit board used in the present invention.
  • FIG. 1 is a schematic sectional view of an integrated passive element used in the present invention.
  • FIG. 2 is a schematic sectional view showing a first embodiment of the present invention.
  • FIG. 3 is a schematic sectional view showing a second embodiment of the present invention.
  • FIG. 4 is a schematic sectional view showing a third embodiment of the present invention.
  • FIG. 5 is a schematic sectional view showing first and third comparative examples of the present invention
  • FIG. 6 is a schematic sectional view showing second and fourth comparative examples of the present invention
  • FIG. 11 is a schematic sectional view illustrating a fourth embodiment of the present invention.
  • FIG. 8 is a schematic sectional view showing a fifth embodiment of the present invention.
  • FIG. 9 is a schematic sectional view showing a sixth embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a sectional view of an integrated passive device used in the present invention.
  • 1 is a glass substrate (NEC, BLC) and its thickness is 0.3 mm.
  • reference numeral 2 denotes an organic insulating material, which is made of photosensitive polyimide (Hitachi Chemical, HD-600).
  • Capacitor elements 3 inside organic insulating material 2 are all lower electrodes
  • the lower electrode 3a is composed of Cu
  • the dielectric material 3b is composed of an oxide of Ta
  • the upper electrode 3c is composed of Cu.
  • the inductor element 4 is a spiral inductor, is formed on the same surface as the upper electrode 3a of the capacitor element 3, and is made of Cu.
  • the resistance element 5 includes a resistor 5a and electrodes 5b and 5c.
  • the resistor is a compound of Ta and Ti, and the electrodes 5b and 5c are made of Cu.
  • each element formed inside the organic insulator 2 is a circuit having a predetermined function.
  • reference numeral 6 denotes a metal terminal used for connection to the outside.
  • a solder ball 7 is mounted on the metal terminal 12.
  • Cr is deposited to a thickness of 50 nm on the glass substrate main surface by a sputtering method, and An OO nm film was formed, and this was used as a power supply seed film for copper plating.
  • Negative liquid resist PMER-N-CA1000 (manufactured by Tokyo Ohka) is spin-coated on this Cu film, prebaked with a hot plate, and then exposed and developed to form a resist mask. did.
  • Electroless copper plating was performed on the resist opening at a current density of 1 A / dm. Thereafter, the resist mask was removed, and the copper seed film was removed using a copper etching solution, Cobra Etch (manufactured by Ebara Densan). Further, the Cr seed film was removed using a permanganate-based Cr etching solution to form a lower electrode.
  • a photosensitive polyimide HD 6 O 00 (manufactured by Hitachi Chemical) is applied by a spin coat, pre-baked by a hot plate, exposed, developed, and processed to form a film on the lower electrode.
  • the dielectric material was exposed.
  • the polyimide coating was opened so that it was 80 zm inside the scribe area used to cut and divide the polyimide as an integrated passive element into individual pieces. It was cured at 250 ° C for 2 hours in the air to form an organic insulating material of 10 ⁇ m.
  • a TaN film was formed by a 500 nm sputtering method.
  • a positive liquid resist OFPR800, 100 cp was spin-coated on this.
  • exposure and development were performed to form a resist pattern mask.
  • the TaN film was CF 4 dry-etched using this mask.
  • the resist was peeled off to form a plurality of resistance elements.
  • a Cr film was formed to a thickness of 5 O nm and a Cu film was formed to a thickness of 500 nm using a sputtering method, and this was used as a seed film.
  • a negative liquid resist PMER-N-CA100 (manufactured by Tokyo Ohka) is spin-coated on this Cu film, prebaked with a hot plate, and then exposed and developed to form a resist mask. Formed. Electroless copper plating was performed on the resist opening at a current density of 1 A / dm for 10 m. Thereafter, the resist mask was removed, and the copper seed film was removed using a copper etchant, Cobra Etch (manufactured by Ebara Densan). Further, the Cr seed film was removed by using a permanganate-based Cr etching solution to form an upper electrode, a resistor electrode, and an inductor element.
  • a seed film for electroplating Cr 50 nm and Cu: 500 nm were formed.
  • a negative liquid resist material PMER-N-CA1000 Tokyo Ohka
  • pre-baking exposing and developing to form a plating resist mask
  • a further 2 m of electric nickel plating film was formed as a barrier layer.
  • the resist was peeled off, the electroplated seed film was peeled off, and the wiring and metal terminals were formed.
  • the surface on which the metal terminals are formed is spin-coated with photosensitive polyimide HD600 (made by HDMS), prebaked, and then exposed and developed to form openings for forming solder balls. Formed. At this time, an opening was made so that the polyimide coating was located 80 m inside the scribe area used to cut and separate the integrated passive elements. Further, curing was performed at 250 ° C. for 1 hour to form an organic insulating material.
  • photosensitive polyimide HD600 made by HDMS
  • FIG. 1 shows an embodiment of the integrated passive element used in the present invention, and the arrangement of each element is not limited to this.
  • the semiconductor chip (1 mm x 2 mm) is mounted on a ceramic circuit board (4 nra x 4 mm, thickness: 65 mm), which is created in advance so that the connection terminals are exposed on the bottom of the counterbore.
  • a recess for mounting an integrated passive device (1 mm x 2 mm, 0.34 mm in thickness) and a recess for mounting an integrated passive device (1 mm x 2 mm, 0.34 mm in thickness) were formed.
  • the power element is mounted in the recess for mounting the power element, and when the circuit board is mounted on the external board, it is necessary to design so that the external board and the back of the power semiconductor are in close contact with each other.
  • a power semiconductor and integrated passive elements were mounted in predetermined recesses of the circuit board using solder balls to form a module.
  • the height of the module is 0.65 mm, achieving a low profile.
  • this module was mounted on an external board (glass epoxy wiring board) to form a hybrid module (Fig. 2). Since the recess for mounting the integrated passive element and the power semiconductor is on the same side, the manufacturing process is simple. When the power semiconductor was operated and the thermal resistance of the power semiconductor section of the hybrid module was measured, high heat dissipation was achieved at 5 ° C / W. This is because the heat generated by the power semiconductor was efficiently dissipated from the back surface of the power semiconductor to the external substrate. (Example 2)
  • Example 2 The same circuit as in Example 1 was provided with a concave portion for mounting an integrated passive element on a surface opposite to a surface on which a power semiconductor was mounted, thereby forming a hybrid module.
  • the dimensions of the module are 3 mm X 3 mm and 0.8 mm thick (Fig. 3).
  • the thermal resistance measured in the same manner as in Example 1 was still 5 ° C / W.
  • the power semiconductor (1 mm x 2 mm, thickness: 1 mm x 2 mm 0.2 mm) recess and integrated passive element 1 (1 mm x 2 mm, 0.34 mm thick)
  • integrated passive element 2 (1 mm x 2 mm, 0.3 mm thick)
  • a recess for mounting the integrated passive device 3 (1 mm x 2 mm, thickness 0.34 mm) was formed on the surface opposite to the surface on which the power semiconductor was mounted.
  • this module was mounted on an external board (glass epoxy wiring board) to form a hybrid module (Fig. 4).
  • a hybrid module (Fig. 4).
  • the power semiconductor was operated and the thermal resistance of the power semiconductor section of the hybrid module was measured, high heat dissipation was achieved at 5 ° CZW. This is because the heat generated by the power semiconductor was efficiently dissipated from the back of the power semiconductor to the external substrate.
  • Example 1 A circuit similar to that of Example 1 was formed on a circuit board having similar dimensions (FIG. 5). At this time, individual components were used as passive elements. 18 Eight individual components were required and could not be accommodated in the recess, so the module was mounted on the surface facing the power semiconductor mounting surface. The height of the module was 1.2 mm, which was about twice as high as that of Example 1.
  • Example 2 A circuit similar to that of Example 1 was formed on a similar circuit board (FIG. 6). However, the connection with the external board was made on the surface facing the power semiconductor mounting surface. The thermal resistance of the power semiconductor part of this hybrid module was measured and was 3 CTC / W.
  • Example 2 A module similar to that of Example 1 was formed, and a silver paste was interposed between the power semiconductor and the external substrate when mounted on an external substrate.
  • the power semiconductor (1 mm x 2 mm) is set in a predetermined position on a ceramic circuit board (4 mm x 4 mm, 0.65 mm thick) created in advance so that the connection terminals are exposed on the bottom of the countersunk. mm, 0.2 mm thick). At this time, it is necessary to mount the power element in the recess for mounting the power element, and to design the heat sink so that when the circuit board is mounted on the external board, the external board and the back of the power semiconductor are in close contact.
  • a power semiconductor is mounted in a predetermined recess of the circuit board using a solder ball, and an integrated passive element (l mm x 2 mm, thickness 0.1 mm) is mounted on a surface opposite to the surface on which the power semiconductor is mounted.
  • the height of the module is 0.8 mm, achieving a low profile.
  • This module was mounted on an external board (glass epoxy wiring board) to form a hybrid module (Fig. 8).
  • Fig. 8 glass epoxy wiring board
  • the power semiconductor was operated and the thermal resistance of the power semiconductor portion of the hybrid module was measured, high heat radiation was realized at 5 ° C ZW. This is because the heat generated by the power semiconductor was efficiently dissipated from the back surface of the power semiconductor to the external substrate.
  • Example 5 A circuit similar to that of Example 5 was formed on a circuit board having similar dimensions (FIG. 5). At this time, individual components were used as passive elements. Eighteen individual components were mounted on the surface facing the power semiconductor mounting surface to form a module. The height of the module is 1.2 mm, which is about 1.5 times as high as that of the fifth embodiment. I got it.
  • Example 5 A circuit similar to that of Example 5 was formed on a similar circuit board (FIG. 6). However, the connection with the external board was made on the surface facing the power semiconductor mounting surface. The thermal resistance of the power semiconductor portion of this hybrid module was measured to be 30 ° C / W.
  • Example 9 A module similar to that of Example 5 was formed, and a silver paste was interposed between the power semiconductor and the external substrate when mounted on an external substrate (FIG. 9).
  • the thermal resistance of the power semiconductor section of this hybrid module was measured4. (High heat dissipation was realized.
  • the silver paste promoted the thermal contact between the power semiconductor and the external substrate, so the heat generated by the power semiconductor was radiated from the rear surface of the power semiconductor to the external substrate more efficiently. Because it was done.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

L'invention concerne un module hybride utilisant un élément passif intégré formé par intégration d'éléments passifs. Ce module est monté sur ledit élément avec un profil réduit/surbaissé, un circuit intégré de chauffage étant disposé dans un évidement ménagé dans une carte de circuit imprimé.
PCT/JP2002/007090 2001-07-12 2002-07-12 Module hybride WO2003007374A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2001211537A JP2003031757A (ja) 2001-07-12 2001-07-12 ハイブリッドモジュール
JP2001-211537 2001-07-12
JP2001-211534 2001-07-12
JP2001211534A JP2003031756A (ja) 2001-07-12 2001-07-12 ハイブリッドモジュール

Publications (1)

Publication Number Publication Date
WO2003007374A1 true WO2003007374A1 (fr) 2003-01-23

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PCT/JP2002/007090 WO2003007374A1 (fr) 2001-07-12 2002-07-12 Module hybride

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WO (1) WO2003007374A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278565A (ja) * 1990-03-28 1991-12-10 Nec Corp 混成集積回路装置
JPH0613535A (ja) * 1992-06-26 1994-01-21 Ibiden Co Ltd 電子部品搭載装置
EP0822595A2 (fr) * 1996-07-31 1998-02-04 Taiyo Yuden Co., Ltd. Module de type hybride

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278565A (ja) * 1990-03-28 1991-12-10 Nec Corp 混成集積回路装置
JPH0613535A (ja) * 1992-06-26 1994-01-21 Ibiden Co Ltd 電子部品搭載装置
EP0822595A2 (fr) * 1996-07-31 1998-02-04 Taiyo Yuden Co., Ltd. Module de type hybride

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