WO2002103801A1 - Structure et procede pour dispositif a semi-conducteur a grande vitesse - Google Patents

Structure et procede pour dispositif a semi-conducteur a grande vitesse Download PDF

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Publication number
WO2002103801A1
WO2002103801A1 PCT/US2002/019384 US0219384W WO02103801A1 WO 2002103801 A1 WO2002103801 A1 WO 2002103801A1 US 0219384 W US0219384 W US 0219384W WO 02103801 A1 WO02103801 A1 WO 02103801A1
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WO
WIPO (PCT)
Prior art keywords
layer
strained
relaxed
channel layer
channel
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PCT/US2002/019384
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English (en)
Inventor
Minjoo L. Lee
Christopher W. Leitz
Eugene A. Fitzgerald
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Massachusetts Institute Of Technology
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Publication of WO2002103801A1 publication Critical patent/WO2002103801A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors

Definitions

  • the invention relates to the field of MOSFET fabrication, and in particular to the formation of Ge channel MOSFETs grown on SiGe/Si virtual substrates.
  • Channel engineering in the silicon-germanium (SiGe) materials system can result in increased electron and hole mobilities over conventional bulk Si, leading to enhanced metal-oxide-semiconductor field-effect transistor (MOSFET) performance.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • increases in mobility () realized through channel engineering lead to increases in MOSFET drain currents and ultimately to higher switching speeds.
  • the low hole mobility of bulk Si ho ⁇ 0.5rf «m> «) leads to increased p-MOSFET gate widths to compensate for their reduced drive currents.
  • Compressively strained SiGe layers deposited on bulk Si and capped with bulk Si to preserve the Si/Si ⁇ 2 gate interface, lead to modest increases in hole mobility, though electron mobility is unchanged. Increased process complexity and degraded short channel effects further moderate gains in circuit performance through this channel architecture.
  • Tensile strained Si layers grown on relaxed SiGe virtual substrates offer large gains in electron and hole mobility, but the ratio of electron to hole mobility remains unbalanced.
  • MODFETs Schottky-gated modulation-doped field-effect transistors
  • CMOS complementary MOSFET
  • Pure Ge has the highest hole mobility of all semiconductors, along with an electron mobility comparable to bulk Si.
  • MOSFETs based on pure Ge channels thus offer large performance gains over bulk Si.
  • Effective mobilities as high as 1000 cm 2 /V-s have been reported for n- and p-MOSFETs fabricated on bulk Ge and utilizing germanium oxynitride as a gate material.
  • bulk Ge substrates are not an economical manufacturing technology for integrated circuits.
  • an effective hole mobility of 430 cm 2 /V-s has been attained for relaxed Ge deposited directly onto a (111) Si substrate with no buffers and utilizing a Si ⁇ 2 gate.
  • neither of these device structures provides the consistent control of defect density (imparted by SiGe virtual substrate technology) or well-developed gate interface (as, for example, in Si/Si ⁇ 2) required for large-scale integrated applications.
  • the invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer.
  • a strained Ge channel MOSFET is provided.
  • the strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate.
  • a gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si.
  • a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate.
  • a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.
  • FIG. 1 is a cross-section schematic of a strained Ge channel layer structure used in accordance with the invention
  • FIG. 2 is a cross-section schematic of a strained Ge MOSFET in accordance with the invention.
  • FIG. 3 is a cross-section schematic of a relaxed Ge channel layer structure used in accordance with the invention.
  • FIG. 4 is a cross-section schematic of a relaxed Ge MOSFET in accordance with the invention.
  • FIG. 5 is a cross-section schematic of a strained or relaxed Ge channel structure on a virtual substrate comprising an insulating layer
  • FIG. 6 is a cross-section schematic of a strained or relaxed Ge channel layer structure with a thin Si cap used in accordance with the invention
  • FIG. 7 is a graph that demonstrates the effective hole mobilities of two strained Ge p-
  • FIG. 8 is a graph that demonstrates the hole mobility enhancement associated with two strained Ge -MOSFET devices.
  • FIG. 1 is a schematic of the layer structure upon which strained Ge channel MOSFETs are created.
  • the layer structure includes a high quality strained Ge channel layer 14 provided on a virtual substrate 10.
  • This strained Ge channel layer 14 may be provided on virtual substrate 10 either through epitaxial deposition or through wafer bonding techniques.
  • the virtual substrate 10 includes a Si substrate 11, a graded composition SiGe layer 12, and a relaxed SiGe cap layer 13.
  • the graded composition SiGe layer 12 is graded from approximately 0% Ge to a final concentration between 50% Ge and 95% Ge at a grading rate, for example, of 10% Ge/micron for a final thickness of approximately 5.0 - 9.5 microns.
  • a method for providing high quality graded buffer layers is disclosed in U.S. Patent 6,107,653 by Fitzgerald et al.
  • the relaxed SiGe cap layer 13 contains 50% Ge to 95% Ge, for example, and has a thickness of 0.2 - 2.0 microns.
  • a strained Ge channel layer 14 is provided on the virtual substrate 10.
  • the strained Ge channel layer 14 has a thickness of 50 A - 500 A and is compressively strained.
  • the strained Ge channel layer 14 may grown at reduced temperature (Tgmwth ⁇ 550°C) to suppress strain-induced surface undulations and improve surface morphology, forming a strained Ge channel layer that is substantially planar. This planarity improves carrier mobility and facilitates device fabrication.
  • the strained Ge channel layer 14 provides enhanced mobility and performance when it is used to create MOSFETs, while the virtual substrate 10 provides the necessary defect control and large area substrates for integrated circuit manufacturing.
  • the strained Ge channel layer 14 is fabricated on the virtual substrate 10, which includes a relaxed SiGe cap layer 13 that is 70% Ge.
  • FIG. 2 is a cross-section of a schematic diagram of a strained Ge channel
  • the MOSFET 20 in accordance with the invention.
  • the MOSFET 20 includes virtual substrate 10 and a strained Ge channel layer 14.
  • a gate dielectric layer 21 is formed upon the strained Ge channel layer 14.
  • the gate dielectric may be, for example, a dielectric comprising Si ⁇ 2 or a deposited dielectric, and possesses satisfactory integrity required for MOSFETs in operation within integrated circuits.
  • a gate dielectric with satisfactory integrity is one that has, for example, a relatively low interface state density, e.g., less than 1 x 10" eV 'cm 2 , and/or a relatively low leakage current, e.g., ⁇ 10 nanoamperes/square micrometer (nA/m 2 ) to 1 microampere/square micron (A/m 2 ) or even 10 A/m 2 , preferably approximately 10 - 100 nA/m 2 at 100°C.
  • the leakage current may range from approximately 10 - 100 nA/m 2 .
  • the gate dielectric thickness may be, for example 15 A.
  • the layers are patterned by photolithography and etching.
  • the MOSFET 20 also includes a source 23 and drain 24. The source and drain regions are defined by ion implantation. The dopant species in the source and drain is n-type or p-type for either n-MOSFET or p-MOSFET operation, respectively.
  • the MOSFET 20 also includes three terminals 25, 26, and 27. The terminals 25 and 26 are used to establish electrical voltages between the source 23 and drain 24 while the terminal 27 is used to modulate the conductivity of the strained Ge channel 14 under the gate dielectric 21.
  • FIG. 3 is a schematic of the layer structure upon which relaxed Ge channel MOSFETs are created.
  • the layer structure includes a high quality relaxed Ge layer 34 provided on a virtual substrate 30.
  • This relaxed Ge layer 34 may be provided on the virtual substrate 30 either through epitaxial deposition or through wafer bonding techniques.
  • the virtual substrate includes a Si substrate 31 and a graded composition SiGe layer 32.
  • the graded composition layer
  • the relaxed Ge channel layer 34 may have a thickness of 50 A - 2 microns.
  • FIG. 4 is a cross-section of a schematic diagram of a relaxed Ge channel MOSFET
  • the MOSFET 40 includes a virtual substrate 30 and a relaxed Ge channel layer 34.
  • a gate dielectric layer 41 is formed upon the relaxed Ge channel 34.
  • the gate dielectric may be, for example, a dielectric comprising SiO ⁇ or a deposited dielectric, and possesses satisfactory integrity required for MOSFETs in operation within integrated circuits.
  • the gate dielectric thickness may be, for example 15 A.
  • a gate contact 42, such as doped polysilicon, is deposited on the gate dielectric layer 41. The layers are patterned by photolithography and etching.
  • the MOSFET 40 also includes a source 43 and drain 44. The source and drain regions are defined by ion implantation.
  • the dopant species in the source and drain is n-type or p-type for either n- MOSFET or p-MOSFET operation, respectively.
  • the MOSFET 40 also includes three terminals 45, 46, and 47. The terminals 45 and 46 are used to establish electrical voltages between the source 43 and drain 44 while the terminal 47 is used to modulate the conductivity of the relaxed Ge channel 34 under the gate dielectric 41.
  • the virtual substrate 50 may comprise an insulating layer 52 on which the strained or relaxed Ge channel 54 is provided via wafer bonding.
  • an optional relaxed SiGe layer with a Ge concentration between 50% and 95% may also be provided between the insulating layer and the strained Ge channel layer.
  • a thin Si layer 65 that may be strained or partially relaxed is provided on either the strained or relaxed Ge channel layer 64.
  • the thin Si layer may be grown at reduced temperature (Tgrowth ⁇ 550°C) initially to improve surface mo ⁇ hology and stabilize the compressively strained Ge channel layer against strain- induced undulations, forming a strained Ge channel layer that is substantially planar.
  • the thin Si layer may then be grown at high temperatures (Tmwth > 400°C) to improve the growth rate in chemical vapor deposition.
  • the thin Si layer 65 may be initially grown upon strained or relaxed Ge channel layer at low temperatures to improve the mo ⁇ hology of this layer and form a thin Si layer that is substantially planar.
  • the thickness of the thin Si layer may be minimized to reduce carrier population in this layer.
  • the strained or relaxed Ge channel layer 64 provides enhanced mobility and performance when it is used to create MOSFETs, while the virtual substrate 60 provides the necessary defect control and large area substrates for integrated circuit manufacturing.
  • the virtual substrate 60 may be the virtual substrates 10, 30 or 50 shown in previous embodiments.
  • the thin Si layer 65 provides a high quality interface between the semiconductor layer structure and the gate dielectric.
  • FIG. 7 is a graph that demonstrates effective hole mobilities 71, 72, and 73 versus effective vertical field.
  • Effective hole mobility 71 corresponds to a first strained Ge p- MOSFET device with a Si cap thickness of 60 A
  • effective hole mobility 72 corresponds to a second strained Ge p-MOSFET device with a Si cap thickness of 50 A
  • effective hole mobility 73 corresponds to a bulk silicon control p-MOSFET.
  • the strained-Ge channel devices exhibit a peak hole mobility of 1160 cm 2 /V-s.
  • FIG. 8 is a graph that demonstrates effective hole mobility enhancements 81 and 82 versus effective vertical field.
  • Effective hole mobility enhancement 81 corresponds to a first strained Ge p-MOSFET device with a Si cap thickness of 60 A
  • effective hole mobility enhancement 82 corresponds to a second strained Ge p-MOSFET device with a Si cap thickness of 50 A.
  • FIG. 8 shows that mobility enhancement 81 is degraded as compared to mobility enhancement 82. This indicates that the holes can be pulled into the Si cap layer 65 where their mobility is not as high as in the Ge channel layer 64.
  • the consistency of the Ge channel hole mobility enhancement 82 over a wide range of vertical electric fields demonstrates that maintaining a sufficiently low Si cap thickness (less than approximately 50 A) allows the high field mobility enhancement to be completely preserved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne une structure � semi-conducteur comprenant une couche � canal Ge contraint ainsi qu'un di�lectrique de grille dispos� sur cette couche � canal Ge contraint. Dans un aspect de l'invention, on fait intervenir un MOSFET � canal Ge contraint.Le MOSFET � canal Ge contraint comprend un substrat virtuel SiGenon contraint pr�sentant une teneur en Ge comprise entre 50 et 95 %, un canal Ge contraint �tant form� sur ce substrat virtuel. Une structure de grille est form�e sur le canal Ge contraint, un MOSFET �tant form� avec un rendement accru sur du Si brut. Dans uautre mode de r�alisation de l'invention, on fait intervenir unestructure � semi-conducteur comprenant une couche � canal Ge nocontraint et un substrat virtuel, la couche � canal Ge non contraint �tant dispos�e au-dessus du substrat virtuel. Dans un autre aspect de l'invention, on utilise un MOSFET � canal Ge non contraint. Un proc�d� correspondant consiste � obtenir un substrat virtuel non contraint pr�sentant une proportion de Ge d'environ 100 %, un canal Ge non contraint �tant form� sur ce substrat virtuel.
PCT/US2002/019384 2001-06-18 2002-06-18 Structure et procede pour dispositif a semi-conducteur a grande vitesse WO2002103801A1 (fr)

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US60/229,139 2001-06-18

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Citations (11)

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