WO2002100035A3 - Verfahren zum digitalen verarbeiten eines analogen datenstroms und schaltungsanordnung - Google Patents

Verfahren zum digitalen verarbeiten eines analogen datenstroms und schaltungsanordnung Download PDF

Info

Publication number
WO2002100035A3
WO2002100035A3 PCT/EP2002/006115 EP0206115W WO02100035A3 WO 2002100035 A3 WO2002100035 A3 WO 2002100035A3 EP 0206115 W EP0206115 W EP 0206115W WO 02100035 A3 WO02100035 A3 WO 02100035A3
Authority
WO
WIPO (PCT)
Prior art keywords
data stream
analogue data
analogue
digitally processing
clock pulse
Prior art date
Application number
PCT/EP2002/006115
Other languages
English (en)
French (fr)
Other versions
WO2002100035A2 (de
Inventor
Ronalf Kramer
Original Assignee
Infineon Technologies Ag
Ronalf Kramer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Ronalf Kramer filed Critical Infineon Technologies Ag
Publication of WO2002100035A2 publication Critical patent/WO2002100035A2/de
Publication of WO2002100035A3 publication Critical patent/WO2002100035A3/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Die Erfindung schafft ein Verfahren zum digitalen Verarbeiten eines analogen Datenstroms (101), wobei der analoge Datenstrom (101) in einem analogen Datenstromempfänger (102) empfangen wird, der empfangene analoge Datenstrom (102a) in einen digitalen Datenstrom (104) mittels eines Analog-Digital-Umsetzers (103) umgesetzt wird, indem der empfangene analoge Datenstrom (102a) zu vorgegebenen Abtastzeitpunkten eines Abtasttaktsignals (107) abgetastet wird, der digitale Datenstrom (104) in einer Interpolationseinrichtung (105) zum Erzeugen eines interpolierten Datenstroms (106) interpoliert wird, wobei mindestens ein Symbolwert (109) aus dem interpolierten Datenstrom (106) bestimmt wird, der Symbolwert (109) in einer digitalen Verarbeitungseinrichtung (110) zum Erzeugen eines Phasensteuersignals (111) verarbeitet wird und optimale Abtastzeitpunkte eines Abtasttaktsignals (107) in Abhängigkeit einer Steuerung durch das Phasensteuersignal (111) und in Abhängigkeit von einem vorgegebenen Taktsignal (114) in einer Berechnungseinrichtung (112) bestimmt werden.
PCT/EP2002/006115 2001-06-07 2002-06-04 Verfahren zum digitalen verarbeiten eines analogen datenstroms und schaltungsanordnung WO2002100035A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2001127447 DE10127447C1 (de) 2001-06-07 2001-06-07 Verfahren zum digitalen Verarbeiten eines analogen Datenstroms und Schaltungsanordnung
DE10127447.5 2001-06-07

Publications (2)

Publication Number Publication Date
WO2002100035A2 WO2002100035A2 (de) 2002-12-12
WO2002100035A3 true WO2002100035A3 (de) 2003-09-18

Family

ID=7687369

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/006115 WO2002100035A2 (de) 2001-06-07 2002-06-04 Verfahren zum digitalen verarbeiten eines analogen datenstroms und schaltungsanordnung

Country Status (2)

Country Link
DE (1) DE10127447C1 (de)
WO (1) WO2002100035A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8675298B2 (en) 2009-01-09 2014-03-18 Lsi Corporation Systems and methods for adaptive target search
US7969337B2 (en) * 2009-07-27 2011-06-28 Lsi Corporation Systems and methods for two tier sampling correction in a data processing circuit
US8854752B2 (en) 2011-05-03 2014-10-07 Lsi Corporation Systems and methods for track width determination
US8762440B2 (en) 2011-07-11 2014-06-24 Lsi Corporation Systems and methods for area efficient noise predictive filter calibration
US9112538B2 (en) 2013-03-13 2015-08-18 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for loop feedback
US8848776B1 (en) 2013-03-25 2014-09-30 Lsi Corporation Systems and methods for multi-dimensional signal equalization
US8929010B1 (en) 2013-08-21 2015-01-06 Lsi Corporation Systems and methods for loop pulse estimation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996016482A1 (en) * 1994-11-22 1996-05-30 Analog Devices, Inc. Variable sample rate adc
US5671257A (en) * 1995-06-06 1997-09-23 Sicom, Inc. Symbol timing recovery based on complex sample magnitude
WO1998012836A1 (en) * 1996-09-20 1998-03-26 Thomson Consumer Electronics, Inc. Component timing recovery system for qam

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996016482A1 (en) * 1994-11-22 1996-05-30 Analog Devices, Inc. Variable sample rate adc
US5671257A (en) * 1995-06-06 1997-09-23 Sicom, Inc. Symbol timing recovery based on complex sample magnitude
WO1998012836A1 (en) * 1996-09-20 1998-03-26 Thomson Consumer Electronics, Inc. Component timing recovery system for qam

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MEYR H ET AL: "ON SAMPLING RATE, ANALOG PREFILTERING, AND SUFFICIENT STATISTICS FOR DIGITAL RECEIVERS", IEEE TRANSACTIONS ON COMMUNICATIONS, IEEE INC. NEW YORK, US, vol. 42, no. 12, 1 December 1994 (1994-12-01), pages 3208 - 3213, XP000486744, ISSN: 0090-6778 *

Also Published As

Publication number Publication date
WO2002100035A2 (de) 2002-12-12
DE10127447C1 (de) 2002-10-10

Similar Documents

Publication Publication Date Title
WO1999043087A3 (en) Apparatus and method for the clocking of digital and analog circuits on a common substrate to reduce noise
WO2006076420A3 (en) High-speed sampling architecture
EP0921654A3 (de) Digitale PLL Schaltung und Verfahren zur Signalrückgewinnung
KR0178750B1 (ko) 전-디지탈 심볼타이밍 복구장치
EP0793363A3 (de) Taktrückgewinnungssystem für einen digitalen Signalprozessor
JPH06260887A (ja) サンプリング周波数変換装置
CA2110826A1 (en) Clock Recovery Circuit of Demodulator
CA2484281A1 (en) Clock timing recovery methods and circuits
EP0853383A3 (de) Abtastratenwandlerschaltung und Verfahren zur Abtastratenwandlung
DE60314152D1 (de) Verfahren zur seriellen, asynchronen analog-digital wandlung mit dynamisch eingestellter bandbreite
WO2002100035A3 (de) Verfahren zum digitalen verarbeiten eines analogen datenstroms und schaltungsanordnung
AU2003201703A1 (en) Method and apparatus for alias suppressed digitizing of high frequency analog signals
EP0300633A3 (de) Zeitbasiskorrigiereinrichtung
EP1271284A3 (de) Taktsignalgeneratorsystem
WO1999056427A3 (en) Sample rate converter using polynomial interpolation
JP2004521568A (ja) オーバーサンプリングされたデータを用いた端数間引きフィルタ
EP0230310A3 (de) Schaltung zur Korrektur von Geschwindigkeitsfehlern
US7327288B2 (en) Variable interpolator for non-uniformly sampled signals and method
WO2003023951A3 (en) Data sampler for digital frequency/phase determination
EP1184980A3 (de) Digitaler Empfänger
JPH04291822A (ja) Ａ／ｄ変換器
EP0793365A3 (de) Filter in einem digitalen Taktrückgewinnungssystem
KR960000542B1 (ko) 디지탈 무선 통신 시스템에서 동기 신호를 이용한 프레임 타이밍신호 추출방법 및 시스템
KR100261141B1 (ko) 데이터 송수신시스템의 타이밍 복원장치
KR19980077667A (ko) 심볼 타이밍 복구장치

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP