WO2002084743A1 - Mis-halbleiterleistungsbauelement und entsprechendes herstellungsverfahren - Google Patents
Mis-halbleiterleistungsbauelement und entsprechendes herstellungsverfahren Download PDFInfo
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- WO2002084743A1 WO2002084743A1 PCT/DE2002/001196 DE0201196W WO02084743A1 WO 2002084743 A1 WO2002084743 A1 WO 2002084743A1 DE 0201196 W DE0201196 W DE 0201196W WO 02084743 A1 WO02084743 A1 WO 02084743A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
- H01L29/102—Cathode base regions of thyristors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect
Definitions
- the present invention relates to a semiconductor power device and a corresponding manufacturing method.
- the ESTs are used as circuit breakers in the range from a few hundred to a few thousand volts reverse voltage.
- the use of such ESTs as an ignition transistor, i.e. as a switch on the primary side of an ignition coil, of particular interest.
- the * structure of the EST results from that of the known V-IGBT (Vertical Insulated Gate Bipolar Transistor) by adding additional, floating emitter structures shielded by diffusion regions on the chip top.
- V-IGBT Very Insulated Gate Bipolar Transistor
- the advantage of ESTs over V-IGBTs is generally seen in better transmission behavior, ie a lower voltage drop when switched on. condition.
- the connection that is connected to the rear emitter is referred to as the anode
- the control connection as the gate
- the connection to the source and body diffusions as the cathode.
- the first type is the so-called single-channel EST (SC-EST), whose half-cell cross-section 100 is shown in FIGS. 7 and 9, respectively.
- the second type is the so-called dual-channel EST (DC EST), the half-cell cross section 200 of which is shown in FIGS. 8 and 10, respectively.
- the punch-through type As with the V-IGBT, there are essentially two types with regard to the design of the emitter on the back of the chip, the punch-through type (PT type), the half-cell cross-section 300 of which is shown in FIGS. 9 and 10, and the non Punch-through type, the half-cell cross-section 400 of which is shown in FIGS. 7 and 8, respectively.
- PT type punch-through type
- non Punch-through type the half-cell cross-section 400 of which is shown in FIGS. 7 and 8, respectively.
- the gate 103 which is usually made of polysilicon, is composed of two parts per half cell, which are connected to one another via the third dimension, not shown.
- the gate which is isolated from the semiconductor only by means of a thin gate oxide layer 109, is brought to a potential above the threshold voltage of the MOS control heads 106, 107, 108, 160, 180 relative to the cathode 101, the metallization of which is at a reference potential.
- the intermediate oxide layer 110 serves to isolate the cathode 101 from the gate 103.
- inversion channels are generated on the HL surface under the gate 103 in the region of the p regions (p body region 108, p region 180) and the semiconductor surface is brought into accumulation in the region of the n " -doped drift region 104 cathode 101 positive anode voltage at the chip rear side metallization of the anode 102 are electrons over the n + regions 106, 160, the injected influen proceeden MOS channels and the accumulation layer in the drift region n ⁇ 104th then injected the anode-side p + -doped emitters 105 holes in the n ⁇ - drift region 104, which flow to the cathode 101 via the p-regions 180, 108 and the p + -contact region 107.
- the now active four-layer structure consisting of the n + region 160, the p region 180, the n ⁇ drift region 104 and the rear p + emitter 105 acts as a thyristor, its n + emitter 160 over the n + region 106 and the MOS channel formed under the left part of the gate 103 is supplied with electrons and can thus be switched or controlled by means of the gate 103.
- the EST Compared to a normal thyristor, the EST therefore has the advantage that it can be switched off by lowering the gate cathode voltage below the threshold voltage and the current flowing through it can be controlled via the gate voltage. Its pass characteristic shows a current saturation range. • In the forward mode, the n _ drift region 104 is flooded with charge carriers in such a way that its conductivity is increased. It is in high injection at normal forward current densities. The intermediate oxide layer 110 serves to isolate the cathode 101 from the gate 103.
- the mode of operation in the forward case for the SC-PT-EST 300 according to FIG. 9 is completely analogous to the SC-NPT-EST.
- the SC-PT-EST has an additional n-buffer layer 150, the function of which is explained in connection with the blocking situation.
- the n-buffer layer 150 makes it possible to reduce the thickness of the n " drift region 104 in order to achieve a better transmission characteristic.
- the SC-PT-EST can be produced, for example, on a p + substrate with the rear emitter 105, wherein the n buffer layer 150 and the n " drift region 104 are grown epitaxially on this p + substrate.
- the mode of operation in the forward case for the DC-PT-EST 200 according to FIG. 8 is similar to that of the SC-PT-EST 300 according to FIG. 9.
- the gate 103 which is usually made of polysilicon, has only one part per half cell.
- the gate 103 which is only insulated from the semiconductor surface by means of the thin gate oxide layer 109, is brought to a potential above the threshold voltage of the MOS control heads 106, 107, 108, 160, 180 with respect to the cathode 101, the metallization of which is at a reference potential. representation thereupon, inversion channels are generated on the semiconductor surface under the gate 103 in the region of the p regions (p body region 108, p region 180) and the semiconductor surface is brought to accumulation in the region of the n " -doped drift region 104.
- the anode-side p + -doped emitter 105 injects holes into the n ⁇ - drift region 104, which on the one hand via the p + contact region 107 and the -p body region 108, on the other hand via the p + contact region 107 and via the p regions 180, 108 and the part of the drift region 104 lying between them Drain cathode 101.
- the now active four-layer structure consisting of the n + region 160, the p region 180, the n ⁇ drift region 104 and the rear p + emitter 105 acts as a thyristor, its n + emitter 160 over the n + region 106 and the one under the Te 103 trained channel is supplied with electrons and can thus be switched or controlled by means of the gate.
- the n ⁇ drift region 104 is flooded with charge carriers in such a way that its conductivity is increased. It is in high injection at normal forward current densities.
- dual-channel ESTs have the advantage of a further extended safe working area in the forward direction (FBSOA).
- the operation in the forward case for the DC-PT-NPT according to FIG. 10 is completely analogous to the DC-NPT-EST.
- the DC-PT-EST has the additional n buffer layer 150, the function of which is explained in connection with the blocking case ,
- the n buffer layer 150 makes it possible to reduce the thickness of the n " drift region 104 in order to achieve a better transmission characteristic.
- a DC-PT-EST can be produced analogously to the SC-PT-EST.
- the gate 103 is brought to a voltage below the threshold voltage with respect to the cathode 101. Bring to the anode 102 is now at a positive potential, expands the ten at the boundary between the p-Gebie- 108, 180 and n _ drift region 104 formed space charge zone almost exclusively in the drift region n ⁇ 104 out.
- the thickness of the n ⁇ drift zone 104 is chosen to be greater than the width that the space charge zone has for a given maximum blocking capability of the component, which is determined primarily by the drift zone doping. This leads to the triangular course of the electric field strength
- the maximum field strength is in the area of the MOS control heads 106, 107, 108, 160, 180.
- the thickness of the n _ drift zone 104 is selected to be smaller than the width that the space charge zone would have for a given maximum blocking capability of the component.
- the n-doped buffer zone 150 is introduced here with the aim of avoiding the punch-through. This leads to the trapezoidal course of the electric field strength
- the maximum field strength is also in the area of the MOS control heads 106, 107, 108, 160, 180.
- the n-buffer zone 150 also enables the emitter efficiency and thus the pass-through and switching behavior of the PT ESTs.
- DE 198 16 448 C1 proposes a universal semiconductor wafer for high-voltage components, inter alia for V-IGBTs, in which at least one n-doped epitaxial layer is provided on an, for example, n-doped semiconductor substrate, the interfaces between the Embedded in the substrate and the ' at least one epitaxial layer, a multiplicity of floating, p-doped semiconductor regions which are dimensioned such that the dimension of a floating region is small compared to the layer thickness of the at least one epitaxial layer and essentially that. Distance between the floating areas in an interface corresponds to or is less than this. The floating areas lying in one plane can be connected to one another so that they form a grid. In the example of the V-IGBT, it is assumed that the charge carriers in the active region of the V-IGBT are not completely cleared from the floating p regions when the reverse voltage is applied.
- DE 198 40 032 C1 proposes a MOS transistor (for example n-channel V-DMOS) with a non-floating compensation structure in the n-drift region.
- MOS transistor for example n-channel V-DMOS
- a non-floating compensation structure in the n-drift region shows that the compensation structure and / or the n-drift region are doped in such a way that the degree of compensation changes monotonically (continuously or step-wise) in the depth of the component as follows.
- the p-doping dose on the source side outweighs the n-doping dose, while on the drain-side end of the compensation structure the n-doping dose outweighs the p-doping dose.
- a hump-shaped field distribution occurs, which has its maximum approximately in the middle of the vertical extension of the compensation structure, where n- and p-doping doses are currently being compensated.
- a lightly doped n-layer may be optionally disposed. The purpose in any case is increased process reliability and increased robustness in the breakthrough.
- DE 196 04 043 A1 has proposed possibilities for favorably influencing the field distribution in a MOS transistor or V-IGBT by means of n-doped and p-doped regions let into the drift region in order to reduce the forward voltage drop for a given blocking capability.
- the total amount of doping of the introduced n-regions is approximately equal to the total amount of doping of the introduced p-regions.
- the areas introduced can be statistically distributed or structured in the form of spheres, strips or filaments and can be introduced in pairs. Their distance is bigger or zero, but smaller than the space charge zone.
- the p regions are floating. In the case of statistically distributed p and n regions, the average concentration of the distributed p regions should be equal to or greater than that of the n regions introduced.
- FIG. 11 shows a common circuit topology as used for IGBTs in ignition applications and which would also be suitable for ESTs. If one were to use a known EST in such a topology as a switching element, there would be * problems with the pulse strength of the component. These problems are described after a brief explanation of the functionality of the circuit.
- a switching element 900 with a typical blocking capability of 400-600V and the connections cathode 901, anode 902 and gate 903 is connected to the battery voltage 911 via an ignition coil 912.
- a spark plug 913 is connected to the secondary side of the ignition coil 912.
- the diode 904 serves for ESD protection and the optionally available diode 906 prevents a current flow from the gate to the anode in the event of transmission.
- the elements 904, 905, 906, 907, 914 are usually monolithically integrated, the diodes 904, 906 normally being made of polysilicon.
- the circuit arrangement can be operated by a control unit directly via the control connection 908.
- a positive voltage of e.g. 5V whereupon a conductive path between the electrodes 901, 902 of the switching element is opened and a current rise is initiated by the ignition coil.
- the voltage at the control connection 908 is reduced to approximately 0 V, whereupon the conductive path between the electrodes 901, 902 of the switching element disappears and the voltage at the nodes 902, 909 rises steeply.
- the voltage rise is transformed up to the secondary side of the ignition coil 912 and leads to a spark at the spark plug 913.
- the clamp diode 905 has the task of limiting the voltage rise at the anode 902 to the so-called clamp voltage of approx. 400V, on the one hand the switching element and on the other hand the other circuit components. to protect. This is particularly important in the so-called impulse case.
- Electrons are injected into the drift region via the MOS channel formed and are controlled via the trained MOS channel into the drift region by means of the clamp electrodes 905, 906, which control the p + emitter 105. Due to the high 'current density, the high electric field strength and thus the high power loss in the MOS control heads, the device is very hot, in particular at the cathode, whereupon it comes to an electrical nenleckstro from the MOS control heads. The electrons run in the direction of the anode and open the p + emitter 105. So they act like an additional control of the EST.
- the control of the gate 103 is reduced accordingly via the clamp diode 905.
- the activation by the thermally induced electron leakage current is so strong that the EST can carry the load current without gate activation (this is particularly favored if the emitter efficiency increases with increasing temperature).
- the controllability of the ESTs is' lost, the temperature continues to rise, the leakage current is increasing. Eventually there is a thermal positive feedback and the EST is destroyed.
- the semiconductor power component according to the invention is easier to manufacture than the structures proposed in DE 196 04 043 AI or has an increased pulse strength compared to the structures proposed in DE 198 40 032 Cl.
- the semiconductor power components according to the invention in particular also allow small half-cell widths in a simple manner.
- drift regions of the first conductivity type are provided in the form of strips or columns, which are connected, for example, via a body region of the first conductivity type with contact diffusion of the first conductivity type to the cathode metal, so that their potential does not float. They are used for charge compensation when absorbing reverse voltage.
- the structures according to the invention can be manufactured more easily since only one further type of drift area is always introduced into the drift area be uss.
- the structures proposed here differ from those in DE 196 04 043 AI, which describes those in the active area of the EST, e.g. per half cell, the total net dose of the drift areas of the first conduction type introduced is greater than the net dose of the part of the drift area of the second conduction type arranged in the active area between the drift areas of the first conduction type.
- a buffer region of the second conduction type is provided between the first drift region and the rear emitter region.
- a contact area of the first conduction type partially encloses the source area.
- the first body region and the source region on the one hand and the third drift region on the other hand run in strips and not parallel to one another.
- the third drift region encloses a trench filled with an insulation material.
- the first line type is the n type and the second line type is the p type.
- Fig. 1 is a schematic cross-sectional view of a
- a semiconductor power device according to a first embodiment of the present invention
- FIG. 2 shows a schematic cross-sectional illustration of a semiconductor power component according to a second embodiment of the present invention
- FIG. 3 shows a schematic cross-sectional illustration of a semiconductor power component according to a third embodiment of the present invention
- FIG. 4 shows a schematic cross-sectional illustration of a semiconductor power component according to a fourth embodiment of the present invention.
- 5a-e a representation of the essential process steps. an embodiment of the manufacturing method according to the invention for the semiconductor power component according to the first or second embodiment; 6a-e show a representation of the essential process steps of an embodiment of the manufacturing method according to the invention for the semiconductor power component according to the third or fourth embodiment;
- FIG. 11 shows a conventional circuit topology in which an EST is used as an ignition switch in the primary circuit of an ignition coil for an internal combustion engine.
- FIG. 1 shows a schematic cross-sectional illustration of a semiconductor power component according to a first embodiment of the present invention.
- y is the coordinate pointing from the first semiconductor surface in the direction of the back of the chip
- ND (x, y, z) and NA (x, y, z) are the donor and acceptor concentrations at a point P (x, y, z) within the device.
- a degree of compensation K (y)> 1 is set, which has a maximum in the region of the end of the p-drift region 514 that is distant from the front semiconductor surfaces.
- the entire active area is obtained by repeatedly mirroring the sketched structure on its boundary surfaces.
- Fig. 1 is 501 the cathode metallization, 502 the anode metallization, 503 the two-part gate, the two parts of which are connected to one another via the third dimension and which preferably consists of polysilicon, 514 the p-drift region of the width bs ⁇ 4 and ' length 1 * - *, 504 a first part of the n-drift region of depth ' t 5 o 4 with optionally non-constant doping, 540 a second part of the n-drift region with optionally 504 different doping concentrations, 550 an optional n-region with an increased doping concentration compared to 540, which can serve, for example, as a buffer, 505 a p + region serving as an emitter, 506 an n + -doped source region r 560 an n + -doped emitter region, 507 a p + contact diffusion, which in some cases extends below 506 and additionally serves to reduce the latch-up sensitivity of the
- l z is less than or equal to 1 and b 5 ⁇ 4 less than or equal to b, where l z and hsu are always to be selected such that a continuous vertical path of the n-drift region 504 from the front semiconductor surface to region 540 is retained, through which a current flow of electrons is possible.
- the function is analogous to the SC-EST according to the state of the art.
- the gate 503 which is isolated from the semiconductor only by means of a thin gate oxide layer 509, is brought to a potential above the threshold voltage of the MOS control heads in relation to the cathode connection 501.
- An inversion channel is then generated on the semiconductor surface under the gate oxide 509 in the region of the p-body regions 508, 580 and, if b 5 ⁇ 4 is correspondingly wide, of the p-drift region 514.
- the semiconductor surface in the area of n-drift region 504 is then in the state of accumulation.
- the anode voltage at the anode connection 502 is positive in relation to the cathode connection 501, electrons are injected into the n-drift region 504 via the n + regions 506, the influenced MOS channels and the accumulation layer.
- the anode-side p + emitter then injects 505 holes.
- the thyristor structure consisting of the regions 560, 580, 514, 504, 540, 550, 505 ignites, as a result of which the n ⁇ drift region 540 and, depending on the level of the doping, also the p / n drift regions 514 or 504 such flooded of 'charge carriers, that the conductivity is increased by the mechanism of high-injection. Good transmission properties can thus be achieved.
- the current through the EST remains controllable via the gate-cathode voltage.
- the functionality in the event of a lock is as follows.
- the gate 503 is brought to a voltage below the threshold voltage in relation to the cathode connection 501. If the anode connection 502 is now brought to a positive potential, the space charge zone formed at the boundary between the p-drift region 514 and the n-drift regions 504, 540 expands more into the n-drift regions 504, 540 than because of K (y)> l into the p-drift region 514.
- the p-drift region 514 is completely cleared of charge carriers only for large reverse voltages in the order of magnitude of the breakdown voltage.
- the region 550 is omitted and the thickness of the n ⁇ drift zone 540 is selected to be greater than the width which the space charge zone has for a predetermined maximum blocking capability of the component in the n ⁇ Drift zone 540.
- the n-region 550 is present and can either be used to optimize the emitter efficiency and the switching behavior, and / or the thickness of the n " drift zone 540 is chosen to be smaller than the width that would have the space charge zone for a given maximum blocking capability of the component in the n ⁇ drift zone 540. Then the n region 550 can be used to prevent the space charge zone from striking the p + emitter 505. This leads to a course of the electric field strength
- the EST is operated in a circuit according to FIG. 11, and it is again assumed that no ignition spark can be generated.
- the mode of operation is analogous to the EST according to the prior art. Due to the special structure of the EST according to the invention, however, the field maximum and the location of the highest heat generation for it lies in the depth of the semiconductor. Thus, it takes a certain amount of time until the MOS control head area is captured by the heat front after the onset of the pulse case, and the thermal positive feedback effect described above, which initiates the destruction of the component, only occurs significantly later. As a result of this additional time which the EST survives in the pulse case according to this embodiment, it achieves a significantly increased pulse strength compared to the EST according to the prior art.
- FIG. 2 shows a schematic cross-sectional illustration of a semiconductor power component according to a second embodiment of the present invention.
- the second embodiment 600 of the EST according to the invention with or without n-region 550 in FIG. 2 shows a DC EST, whose mode of operation is analogous to that of the structure in FIG. 1.
- Structure 600 shown in FIG. 2 advantageously has a higher FBSOA.
- the p-drift region 514 borders directly on the second p-body region 580. It is important here that the dimensions b 5 i 4 , l z are selected such that a continuous vertical path of the region 504 from the first semiconductor surface to the Area 540 is preserved, through which a current flow of electrons is possible.
- FIGS. 3 and 4 show a respective schematic cross-sectional representation of a semiconductor power component according to a third or fourth embodiment of the present invention with optional n-region 550, specifically FIG. 3 as SC-EST and FIG. 4 as DC.EST.
- the p-drift regions 514 are produced by means of a deep trench or trench 724, which can optionally be filled with dielectric or polysilicon. A possible process flow for production is explained later in connection with FIGS. 6a ⁇ e. It is essential for the structures shown in FIGS.
- the degree of compensation K (y)> l is set such that it has a maximum in the region of the end of the p-drift regions 514 remote from the first semiconductor surface and further that a Continuous vertical path of region 504 from the front semiconductor surface to n " drift region 540 is maintained, via which current flow of electrons is possible.
- 5a-e show a representation of the essential process steps of an embodiment of the manufacturing method according to the invention for the semiconductor power component according to the first or second embodiment.
- the starting point is, for example, a p + substrate 505a with a first n layer 550a optionally produced thereon, onto which a part of the n ⁇ drift region 540a has been deposited by epitaxy.
- an n-substrate with p + back diffusion or an n-substrate with p + epitaxial layer can also be used.
- a p-layer 1061a is implanted, which is structured by means of a photomask • 1060a.
- FIG. * • 5b the growth of a partial thickness of the n-drift region 504a, the previously implanted p-regions 1014a to some extent diffuse.
- n-drift region 504a This is followed by an epitaxial growth of a further partial thickness of the n-drift region 504a, the p regions 1014a, 1014c previously introduced again diffusing out somewhat. *.
- This step implantation with subsequent. Epitaxy is repeated until the n-drift region 504a has reached its target thickness (see FIG. 5d), which can be defined, for example, on the basis of the desired pulse strength.
- the desired degree of compensation K (y) can be set by appropriate selection of the implantation doses and / or window widths in the photomasks and / or variable doping during the epitaxy.
- 6a-e show a representation of the essential process steps of an embodiment of the manufacturing method according to the invention for the semiconductor power component according to the third or fourth embodiment.
- trenches 724 are etched from the upper side of the wafer, wherein a mask 1101 is used for structure mapping.
- a mask 1101 is used for structure mapping.
- These can have vertical parallel side walls. However, they can also have sloping side walls so that they have a V- cross section. are shaped or are U-shaped with increasing width upwards.
- p-type doping 514c, 514d can be introduced into the walls and the bottom of the trenches 724 such that K (y)> 1.
- the degree of compensation has a maximum at the level of the bottom of the trenches 724.
- process steps that reduce carrier lifespan can be inserted into the process flows according to FIGS. 5a-e or 6a-e.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Thyristors (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02737772A EP1384269B1 (de) | 2001-04-10 | 2002-04-03 | Mis-halbleiterleistungsbauelement und entsprechendes herstellungsverfahren |
US10/474,614 US7084438B2 (en) | 2001-04-10 | 2002-04-03 | Metal insulator power semiconductor component (MIS) and a method for producing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10117802.6 | 2001-04-10 | ||
DE10117802A DE10117802A1 (de) | 2001-04-10 | 2001-04-10 | Halbleiterleistungsbauelement und entsprechendes Herstellungsverfahren |
Publications (2)
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WO2002084743A1 true WO2002084743A1 (de) | 2002-10-24 |
WO2002084743A8 WO2002084743A8 (de) | 2003-01-09 |
Family
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PCT/DE2002/001196 WO2002084743A1 (de) | 2001-04-10 | 2002-04-03 | Mis-halbleiterleistungsbauelement und entsprechendes herstellungsverfahren |
Country Status (4)
Country | Link |
---|---|
US (1) | US7084438B2 (de) |
EP (1) | EP1384269B1 (de) |
DE (1) | DE10117802A1 (de) |
WO (1) | WO2002084743A1 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US7554137B2 (en) * | 2005-10-25 | 2009-06-30 | Infineon Technologies Austria Ag | Power semiconductor component with charge compensation structure and method for the fabrication thereof |
CN111735549A (zh) * | 2019-03-25 | 2020-10-02 | 株洲中车时代电气股份有限公司 | 集成于igbt芯片的温度传感器及其制造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5216275A (en) * | 1991-03-19 | 1993-06-01 | University Of Electronic Science And Technology Of China | Semiconductor power devices with alternating conductivity type high-voltage breakdown regions |
DE19604043A1 (de) * | 1996-02-05 | 1997-08-07 | Siemens Ag | Durch Feldeffekt steuerbares Halbleiterbauelement |
DE19736981A1 (de) * | 1997-02-10 | 1998-08-20 | Mitsubishi Electric Corp | Halbleitereinrichtung mit hoher Durchbruchsspannung |
DE19840032C1 (de) * | 1998-09-02 | 1999-11-18 | Siemens Ag | Halbleiterbauelement und Herstellungsverfahren dazu |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19816448C1 (de) * | 1998-04-14 | 1999-09-30 | Siemens Ag | Universal-Halbleiterscheibe für Hochspannungs-Halbleiterbauelemente, ihr Herstellungsverfahren und ihre Verwendung |
DE19848828C2 (de) * | 1998-10-22 | 2001-09-13 | Infineon Technologies Ag | Halbleiterbauelement mit kleiner Durchlaßspannung und hoher Sperrfähigkeit |
DE10024480B4 (de) * | 2000-05-18 | 2006-02-16 | Infineon Technologies Ag | Kompensationsbauelement mit verbesserter Robustheit |
DE10117801B4 (de) * | 2001-04-10 | 2005-12-22 | Robert Bosch Gmbh | Halbleiterleistungsbauelement und entsprechendes Herstellungsverfahren |
-
2001
- 2001-04-10 DE DE10117802A patent/DE10117802A1/de not_active Ceased
-
2002
- 2002-04-03 US US10/474,614 patent/US7084438B2/en not_active Expired - Fee Related
- 2002-04-03 EP EP02737772A patent/EP1384269B1/de not_active Expired - Lifetime
- 2002-04-03 WO PCT/DE2002/001196 patent/WO2002084743A1/de active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5216275A (en) * | 1991-03-19 | 1993-06-01 | University Of Electronic Science And Technology Of China | Semiconductor power devices with alternating conductivity type high-voltage breakdown regions |
DE19604043A1 (de) * | 1996-02-05 | 1997-08-07 | Siemens Ag | Durch Feldeffekt steuerbares Halbleiterbauelement |
DE19736981A1 (de) * | 1997-02-10 | 1998-08-20 | Mitsubishi Electric Corp | Halbleitereinrichtung mit hoher Durchbruchsspannung |
DE19840032C1 (de) * | 1998-09-02 | 1999-11-18 | Siemens Ag | Halbleiterbauelement und Herstellungsverfahren dazu |
Non-Patent Citations (2)
Title |
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IWAMURO N ET AL: "A study of EST's short-circuit SOA", POWER SEMICONDUCTOR DEVICES AND ICS, 1993. ISPSD '93., PROCEEDINGS OF THE 5TH INTERNATIONAL SYMPOSIUM ON MONTEREY, CA, USA 18-20 MAY 1993, NEW YORK, NY, USA,IEEE, US, PAGE(S) 71-76, ISBN: 0-7803-1313-5, XP010116915 * |
SHEKAR M S ET AL: "Experimental demonstration of the emitter switched thyristor", POWER SEMICONDUCTOR DEVICES AND ICS, 1991. ISPSD '91., PROCEEDINGS OF THE 3RD INTERNATIONAL SYMPOSIUM ON BALTIMORE, MD, USA 22-24 APRIL 1991, NEW YORK, NY, USA,IEEE, US, PAGE(S) 128-131, ISBN: 0-7803-0009-2, XP010044326 * |
Also Published As
Publication number | Publication date |
---|---|
EP1384269A2 (de) | 2004-01-28 |
US7084438B2 (en) | 2006-08-01 |
DE10117802A1 (de) | 2002-10-24 |
US20040155285A1 (en) | 2004-08-12 |
EP1384269B1 (de) | 2012-12-26 |
WO2002084743A8 (de) | 2003-01-09 |
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