WO2002065523A1 - Couche d'arret de siliciuration d'electrode grille - Google Patents

Couche d'arret de siliciuration d'electrode grille Download PDF

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Publication number
WO2002065523A1
WO2002065523A1 PCT/US2001/043807 US0143807W WO02065523A1 WO 2002065523 A1 WO2002065523 A1 WO 2002065523A1 US 0143807 W US0143807 W US 0143807W WO 02065523 A1 WO02065523 A1 WO 02065523A1
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WO
WIPO (PCT)
Prior art keywords
layer
silicide
silicon
metal
gate
Prior art date
Application number
PCT/US2001/043807
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English (en)
Inventor
Eric N. Paton
Paul R. Besser
Matthew S. Buynoski
Qi Xiang
Paul L. King
John Clayton Foster
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO2002065523A1 publication Critical patent/WO2002065523A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon

Definitions

  • the present invention relates to the formation of a silicided gate electrode. More particularly, the semiconductor device and method of the present invention allows for controlled silicidation of semiconductor material in a standard gate semiconductor structure utilizing a silicide stop layer.
  • Standard gate semiconductor structures are well known in the semiconductor device industry. Typically, to form a standard gate structure, layers of materials that will comprise a gate are deposited on a silicon substrate. The layers of materials are then etched in a controlled manner to define the borders of the gate. Dielectric sidewall spacers are then formed on the side surfaces of the gate electrode. Examples of standard gate semiconductor devices include transistors, memory units, LEDs, and other well known semiconductor devices.
  • one of the material layers formed in a standard gate semiconductor structure is a silicide layer.
  • the silicide layer typically comprises the reaction product of a metal or alloy with silicon. It is often advantageous for a silicide to be formed in a semiconductor structure in a self-aligned manner, thereby avoiding the need to selectively etch any of the silicide layers away to define the silicide regions.
  • Suicides are often formed in standard gate semiconductor structures to provide low resistivity regions for various reasons. Such reasons include the provision of interconnect structures between semiconductor devices, lowering the resistivity of a region of a semiconductor structure to enhance the operability of a semiconductor device, or other reasons that are well-known in the art.
  • Figures 1-8 exemplify the formation of silicide regions in a standard gate semiconductor structure.
  • Figure 1 shows a silicon substrate 10.
  • Figure 2 shows a dielectric layer 12 deposited on the silicon substrate 10.
  • Figure 3 shows a semiconductor layer 14, e.g., doped polycrystalline silicon, deposited on the dielectric layer 12. The dielectric layer 12 and the semiconductor layer 14 are then etched to define the gate electrode structure on the silicon substrate 10.
  • Figure 4 shows semiconductor structure of Figure 3 after the etching of the gate dielectric layer 12 and the semiconductor layer 14.
  • the silicon substrate may be N* doped to form source/drain regions 13.
  • Figure 5 shows dielectric sidewall spacers 16, e.g., an oxide, silicide or oxynitride, deposited on the side surfaces of the gate electrode structure.
  • Figure 6 shows a metal or alloy layer 18 deposited on the semiconductor layer 14, spacers 16, and the silicon substrate 10. Heating is then conducted to form metal silicide layer 24 and metal silicide regions 22.
  • Figure 7 shows a metal silicide layer 24 formed on the gate dielectric layer 12 and metal silicide regions 22 in silicon substrate 10. Metal silicide layer 24 and metal silicide regions 22 are formed during heating by reaction of the metal or alloy layer 18 with underlying silicon. Unreacted metal or alloy layer 20 from the metal or alloy layer 18 ( Figures 6-7) is stripped away from the semiconductor structure using conventional stripping techniques.
  • Figure 8 shows the semiconductor structure of Figure 7 after the unreacted metal or alloy layer 20 has been stripped away. Depending on the type of metal silicide formed, additional heat treatments may be performed to produce the lowest resistivity phase of the metal silicide.
  • the exemplary semiconductor structure of Figure 8 is a typical structure of a metal-oxide semiconductor field-effect-transistor (MOSFET).
  • Metal silicide layer 24 serves as a gate while metal silicide regions 22 serve as a low resistivity interconnection for the source/drain region 13 of a MOSFET.
  • the entire semiconductor layer 14 is silicidized to form silicide layer 24.
  • the silicide layer 24 is in direct contact with gate dielectric layer 12.
  • semiconductor layer 14 is completely silicidized to form a metal silicide layer 24 in direct contact with the dielectric layer 12. This situation has an undesirable effect on the work function.
  • the gate such as formed metal silicide layer 22, and the semiconductor substrate with the source/drain region 13, such as semiconductor substrate 10, to have the same work function. As it is difficult to control the silicidation of semiconductor layer 14 during the temperature treatment, it is therefore difficult to control the work function of the gate.
  • the work function is the minimal energy needed to remove an electron from the fermi energy level (E F ) of a material to the vacuum energy level (Eo).
  • the fermi energy level is the average energy of electrons in the material in the resting state.
  • Figure 9 exemplifies a band diagram of an ideal MOSFET, wherein region 23 represents a gate, region 25 represents a gate dielectric, and region 27 represents a silicon substrate.
  • Figure 9 is characterized as being an ideal MOSFET because the work function ( I A ) 29 of region 23 and the work function ( I B ) 31 of region 27 are substantially equivalent. This characteristic prevents the effect of a bias voltage between the gate and the semiconductor substrate.
  • the work function of the gate and the work function of the semiconductor substrate should be approximately the same, preventing an effective bias voltage.
  • Figure 10 exemplifies the band diagram of a non- ideal MOSFET, wherein region 35 represents a gate and region 33 represents a semiconductor substrate that are separated by the gate dielectric represented by region 37.
  • the work function ( I c ) 39 of region 35 and the work function ( I D ) 41 of region 33 are not equal.
  • An exemplary MOSFET with a band diagram of Figure 10 has an effective bias voltage applied to the gate. Such a bias voltage can interfere with the operation of a transistor having the general structure of Figure 8. Transistors are, therefore, normally engineered such that the work function of the gate region and the work function of the semiconductor region are the same.
  • a disadvantage of the MOSFETs exemplified in Figure 8 is that it is difficult to control the silicidation of silicon layer 14 of Figure 6 and, therefore, control the work function of the gate region 24 to match the work function of the semiconductor substrate 10. These differences in work functions result in an effective bias voltage applied to the gate of the MOSFET, which is undesirable. Other disadvantages are apparent to those of ordinary skill in the art.
  • embodiments of the present invention which provides a standard gate semiconductor structure with a silicide stop layer which enables improved control of the silicidation of semiconductor material.
  • a silicide stop layer is formed over a first semiconductor layer.
  • a second semiconductor layer is formed over the silicide stop layer.
  • the silicide stop layer, the second semiconductor layer, and any other intervening layers are etched.
  • a metal or alloy layer is then deposited and heating is implemented to effect complete silicidation of the second semiconductor layer by reacting the metal or alloy layer with underlying silicon.
  • the unreacted metal or alloy layer is then stripped away and the semiconductor structure of the present invention is accomplished.
  • An advantage of the present invention is the controlled silicidation of the gate to preserve the silicon gate work functions.
  • the silicide stop layer prevents silicidation of the polycrystalline silicon gate layer below the silicide stop layer by blocking the diffusion of metal from the metal or alloy layer, thereby enabling, among other things, tailoring the work function of a gate and a semiconductor substrate.
  • a MOSFET can be in the form of a standard gate semiconductor structure.
  • An ideal MOSFET has a gate and semiconductor layer separated by a dielectric with the work functions of the gate and semiconductor layer substantially equal. Complete silicidation of the gate material inhibits the engineering of the work function of the gate.
  • the use of a silicide stop layer enables engineering the work functions of a MOSFET to form an ideal MOSFET with efficient and effective operation.
  • Figures 1-8 show the formation of a standard gate in accordance with a prior art method.
  • Figure 9 is a prior art energy band diagram of an ideal MOSFET.
  • Figure 10 is a prior art energy band diagram of a non-ideal MOSFET.
  • FIGS. 11-20 depict the formation of a standard gate in accordance with the embodiments of the present invention.
  • the present invention addresses problems related to the use of conventional gate electrode silicidation techniques. These problems, including changing of the work function, are solved in part by providing a silicide stop layer to prevent complete silicidation of the gate electrode. Since silicon, e.g. polycrystalline silicon, remains in contact with the gate dielectric layer, even after silicidation, it is not necessary to reengineer the work function.
  • Figure 11 shows a semiconductor substrate 21.
  • Figure 12 shows a dielectric dielectric layer 19 deposited on semiconductor substrate 21.
  • the gate dielectric layer 19 may comprise a high k dielectric (i.e. k>4.0), an oxide material, or any other material conventionally employed as a gate dielectric layer.
  • Figure 13 shows first semiconductor layer 26 deposited on gate dielectric layer 19.
  • first semiconductor layer 26 is tailored such that the work function of the gate and the work function of the semiconductor substrate 21 are substantially equal, as required in an idea MOSFET.
  • First semiconductor layer 26 may be polycrystalline silicon and have a thickness of about 200 A to about 500 A.
  • Figure 14 shows a silicide stop layer 28 deposited on the first semiconductor layer 26.
  • the silicide stop layer 28 may be comprised of silicon nitride, titanium nitride, tungsten nitride, tungsten carbide, or chromium nitride. Other materials may be used for the silicon stop layer 28 that are conductive and act as a diffusion barrier to prevent diffusion of metal during silicidation.
  • the silicide stop layer 28 may be formed at a suitable thickness given its function, e.g., at about 10 A to about 200 A.
  • Second semiconductor layer 30 is then deposited over silicide stop layer 28, as depicted in Figure 15.
  • Second semiconductor layer 30 can comprise doped polycrystalline silicon.
  • Gate dielectric layer 19, first semiconductor layer 26, silicide stop layer 28, and second semiconductor layer 30 are then etched to define a gate electrode stack structure, as shown in Figure 16.
  • Dielectric sidewall spacers 32 are then formed on the side surfaces of the gate electrode stack.
  • Semiconductor layer 21 may be ion implanted before forming sidewall spacer 32 to form shallow source/drain extensions 23A and ion implanted after spacer formations to form moderately or heavily doped source/drain regions 23B in a conventional manner; the resulting structures are shown in Figure 17.
  • Sidewall spacers 32 may be formed from a suitable dielectric material, such as an oxide, nitride, or oxynitride.
  • a metal or alloy layer 34 for example of nickel, titanium, cobalt or alloys, is heated to effect silicidation by reaction of the deposit metal with underlying silicon in the second silicon layer 30 and substrate 21.
  • the heating is conducted at a temperature of about 250°C to about 850°C, to form metal silicide layer 38 on silicide stop layer 34 and metal silicide layers 36 which may serve as source/drain contacts.
  • Figure 20 shows the semiconductor structure of Figure 19 after the removal of the unreacted metal 40 from deposited layer 34 using conventional stripping techniques, as with sulfuric and hydrogen peroxide, hydrochloric acid, nitric acid, phosphoric acid, or mixtures thereof.
  • Embodiments of the present invention advantageously enable control or engineering of polycrystalline silicon gate electrode to obtain optimum compatible work function with the silicon substrate, thereby preventing an effective bias voltage and, hence, improving device performance and reliability.
  • the strategic formation of a silicide stop layer an the polycrystalline silicon layer protects the engineered polycrystalline silicon layer during silicidation of the silicon layer on the silicide stop layer.
  • the present invention enjoys industrial applicability in fabricating various types of semiconductor devices.
  • the present invention is particularly applicable in fabricating high density semiconductor devices with a design rule in the deep sub-micron range, e.g., about 0.12 micron and under, exhibiting high circuit speed.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne une siliciuration régulée d'une couche électrode grille, mise en place au moyen d'une couche d'arrêt de siliciure (28). Une couche diélectrique grille (19) est d'abord formée sur un substrat semi-conducteur (21), et une première couche de silicium (26) est ensuite formée sur la couche diélectrique grille (19). Une couche d'arrêt de siliciure (28) est alors déposée sur la première couche de silicium (26), et une seconde couche de silicium (30) est déposée sur la couche d'arrêt de siliciure (28). Une couche métallique ou d'alliage (34) est ensuite déposée sur la seconde couche de silicium (30) et un chauffage est effectué pour faire réagir le métal ou l'alliage métallique (34) avec le silicium sous-jacent (28) pour former une couche de siliciure métallique (36, 38), la siliciuration prenant fin lorsque la couche d'arrêt de siliciure est atteinte.
PCT/US2001/043807 2001-02-12 2001-11-13 Couche d'arret de siliciuration d'electrode grille WO2002065523A1 (fr)

Applications Claiming Priority (2)

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US78047401A 2001-02-12 2001-02-12
US09/780,474 2001-02-12

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10234931A1 (de) * 2002-07-31 2004-02-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Metallsilizidgates in einer standardmässigen MOS-Prozesssequenz
US6815235B1 (en) 2002-11-25 2004-11-09 Advanced Micro Devices, Inc. Methods of controlling formation of metal silicide regions, and system for performing same
US7217657B2 (en) 2002-02-28 2007-05-15 Advanced Micro Devices, Inc. Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device
US7226859B2 (en) 2002-02-28 2007-06-05 Advanced Micro Devices, Inc. Method of forming different silicide portions on different silicon-containing regions in a semiconductor device
CN100340006C (zh) * 2003-09-15 2007-09-26 台湾积体电路制造股份有限公司 形成具有完全硅化结构的半导体组件及晶体管的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62111466A (ja) * 1985-11-09 1987-05-22 Toshiba Corp 半導体装置
US5164333A (en) * 1990-06-19 1992-11-17 Siemens Aktiengesellschaft Method for manufacturing a multi-layer gate electrode for a mos transistor
US5543362A (en) * 1995-03-28 1996-08-06 Motorola, Inc. Process for fabricating refractory-metal silicide layers in a semiconductor device
US5861340A (en) * 1996-02-15 1999-01-19 Intel Corporation Method of forming a polycide film

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62111466A (ja) * 1985-11-09 1987-05-22 Toshiba Corp 半導体装置
US5164333A (en) * 1990-06-19 1992-11-17 Siemens Aktiengesellschaft Method for manufacturing a multi-layer gate electrode for a mos transistor
US5543362A (en) * 1995-03-28 1996-08-06 Motorola, Inc. Process for fabricating refractory-metal silicide layers in a semiconductor device
US5861340A (en) * 1996-02-15 1999-01-19 Intel Corporation Method of forming a polycide film

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 011, no. 320 (E - 550) 17 October 1987 (1987-10-17) *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7217657B2 (en) 2002-02-28 2007-05-15 Advanced Micro Devices, Inc. Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device
US7226859B2 (en) 2002-02-28 2007-06-05 Advanced Micro Devices, Inc. Method of forming different silicide portions on different silicon-containing regions in a semiconductor device
DE10234931A1 (de) * 2002-07-31 2004-02-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Metallsilizidgates in einer standardmässigen MOS-Prozesssequenz
US6821887B2 (en) 2002-07-31 2004-11-23 Advanced Micro Devices, Inc. Method of forming a metal silicide gate in a standard MOS process sequence
US6815235B1 (en) 2002-11-25 2004-11-09 Advanced Micro Devices, Inc. Methods of controlling formation of metal silicide regions, and system for performing same
CN100340006C (zh) * 2003-09-15 2007-09-26 台湾积体电路制造股份有限公司 形成具有完全硅化结构的半导体组件及晶体管的方法

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