WO2002059966A1 - Agents de planarisation pour planarisation par gravure centrifuge de composants electroniques et procedes d'utilisation - Google Patents

Agents de planarisation pour planarisation par gravure centrifuge de composants electroniques et procedes d'utilisation Download PDF

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Publication number
WO2002059966A1
WO2002059966A1 PCT/US2002/001861 US0201861W WO02059966A1 WO 2002059966 A1 WO2002059966 A1 WO 2002059966A1 US 0201861 W US0201861 W US 0201861W WO 02059966 A1 WO02059966 A1 WO 02059966A1
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Prior art keywords
layer
protective layer
conductive layer
electronic component
conductive
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PCT/US2002/001861
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English (en)
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WO2002059966A8 (fr
Inventor
Shyama Mukherjee
Joseph Levert
Donald Debear
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Honeywell International Inc.
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Priority claimed from US09/768,439 external-priority patent/US6696358B2/en
Application filed by Honeywell International Inc. filed Critical Honeywell International Inc.
Priority to KR10-2003-7009631A priority Critical patent/KR20030086251A/ko
Priority to JP2002560195A priority patent/JP2004523898A/ja
Priority to CA002432012A priority patent/CA2432012A1/fr
Priority to EP02704222A priority patent/EP1354355A1/fr
Priority to AU2002237917A priority patent/AU2002237917A1/en
Publication of WO2002059966A1 publication Critical patent/WO2002059966A1/fr
Publication of WO2002059966A8 publication Critical patent/WO2002059966A8/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F3/00—Brightening metals by chemical means
    • C23F3/04—Heavy metals
    • C23F3/06—Heavy metals with acidic solutions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the field of the invention is planarization and electronic components.
  • any defects that are present in the larger components are going to be exaggerated in the scaled down components.
  • the defects that are present or could be present in the larger component should be identified and corrected, if possible, before the component is scaled down for the smaller electronic products.
  • Electronic components are composed,, in some cases, of layers of materials, such as metals, polymers, metal alloys, inorganic materials or organometallic materials.
  • the layers of materials are often thin (on the order of less than a millimeter in thickness) and delicate.
  • Copper has several advantages that make it an ideal material for use in electronic components: a) copper has the highest conductivity of any metal except pure silver, b) copper is readily solderable, c) copper has excellent corrosion resistance in natural environments. Copper alloys are also considered excellent alloys for use in electronic components-. Harper, Charles A. ed., Electronic Packaging and Interconnect Handbook, Second Edition, McGraw-Hill (New York), 1997. Copper also has the disadvantage of being diffusive - diffusing easily and widely through other materials typically used in the fabrication of ICs, seriously degrading IC performance.
  • barrier materials or layers may be deposited prior to copper deposition (or deposition of any "copper-like" conductive material) to liinder diffusion of copper or another conductive material into the surrounding material or dielectric material.
  • CMP Chemical Mechanical Planarization
  • Non-contact planarization such as Spin Etch Planarization (SEP) is another method of planarization whereby there is no mechanical abrasion of the surface of the wafer.
  • SEP Spin Etch Planarization
  • the planarization process takes place purely through application of appropriate chemicals.
  • the process of Spin Etch Planarization is described in US Patent Application 09/356,487 and is incorporated by reference herein in its entirety.
  • Aspects of non-contact planarization and Spin Etch Planarization have been reported and discussed in the following publications: J. Levert, S. Mukherjee and D. DeBear, "Spin Etch Planarization Process for Copper Damascene Interconnects" in Proceedings of SEMI Technology Symposium 99, December 1-3, 1999, pp. 4- 73 to 4-82; J. Levert, S.
  • Non-contact planarization suffers from a considerable drawback - surface defects and imperfections are influenced by the planarization process and portions of the conductive layer in the imperfections or defect are undesirably removed resulting in a dish-like geometry. Dishing is a common and undesirable side effect of removing the field region conductive layer and the barrier layer overlying the field region. In other words, the polishing or planarization procedure wears down the tops of the imperfections but also can wear down the crevices of the imperfections, which results in a surface that contains constant imperfections despite applied planarization techniques.
  • planarization techniques used in the fabrication of integrated circuits, such that imperfections and surface defects in the conductive layers are not removed or are minimally removed as the surface is being planarized. Further, it is important that the improved planarization techniques do not hinder or disrupt -the process of build-up of the integrated circuit.
  • An electronic component contemplated comprises a) a substrate layer, b) a dielectric material or layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric material or layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer coupled to the conductive layer.
  • the electronic component contemplated herein can be produced by a) providing a substrate; b) coupling a dielectric layer to the substrate; c) coupling a barrier layer to the dielectric material or layer; d) coupling a conductive layer to the barrier layer; and e) coupling a protective layer, which planarizers or can be planarized, to the conductive layer.
  • the protective layer may then be cured to a desirable hardness.
  • a method of planarizing a conductive surface of an electronic component may comprise a) introducing or coupling a protective layer onto a conductive layer; b) dispersing and planarizing the protective layer across the conductive layer; c) curing the protective layer; d) introducing an etching solution onto the conductive layer; and e) etching the conductive surface to substantial planarity.
  • Fig. 1 is a schematic diagram of a conventional damascene metal interconnection structure before planarization.
  • Fig. 2 is a schematic diagram of a conventional component where the surface is polished and all imperfections are removed.
  • Fig. 3 is a schematic diagram showing a conventional layered material.
  • Fig. 4 is a schematic diagram of a conventional layered material where the barrier layer is removed after its exposure by subsequent planarization along with removal of sufficient conductive material or layer to retain coplanarity of the metal-filled feature and dielectric.
  • Fig. 5 is a schematic diagram of a contemplated embodiment of the present invention.
  • Fig. 6 is a schematic diagram of a contemplated embodiment of the present invention.
  • Fig. 7 is a graph showing the Degree of Planarization versus the Feature Size in micrometers.
  • Prior art Figure 1 shows a schematic diagram of a conventional damascene metal interconnection structure before planarization comprising a) a substrate layer 110, b) a dielectric material or layer 120 coupled to the substrate layer 110, c) a barrier layer 130 coupled to the dielectric layer 120 and d) a conductive layer 140 coupled to the barrier layer 130.
  • This type of conventional interconnection structure might be found in several types of typical electronic components.
  • the dielectric material or layer 120 in Figure 1 is usually patterned by techniques such as photolithography, and plasma etching. (Note: the terms “dielectric material” and “dielectric layer” are intended to be used interchangeably throughout this disclosure).
  • the barrier layer 130 is typically deposited on the patterned dielectric followed by deposition of the conductive layer 140.
  • Conventional barrier layers 130 comprise tantalum/tantalum nitride (Ta/TaN) and are used with copper conductive layers 140.
  • the conductive layer in these conventional components contains imperfections that can be significant problems when building a layered component.
  • Figure 1 shows what imperfections 160 might look like on the surface of the conductive layer 140.
  • Surface topography imperfections are created because of the conformal application of the conductive layer to the surface topography of trenches and vias formed by the underlying barrier material and dielectric material.
  • the surface of the conductive layer is planarized or polished by some means, such as mechanical polishing, chemical polishing, or chemical mechanical polishing.
  • Figure 2 shows an ideal situation where the surface is polished and all imperfections are removed. Perfect planarization removes copper until the upper or elevated surface 142 of the conductive layer 140 is co-planar with the upper surface 132 of the barrier layer 130 on the field region, and at that point, etching is halted. Ideal planarization also removes the barrier layer 130 at the same rate as the conductive layer 140 - substantially a 1 to 1 selectivity.
  • the imperfections 160 in the conductive layer 140 are influenced by the planarization process and portions of the conductive layer 140 in the imperfections 160 are undesirably removed resulting in a dish-like geometry, which is termed "dishing".
  • the imperfections 160 can be created through dishing and by surface topography defects. Dishing is a result of a non-efficient planarization process during removal of excess conductive material. (See Figure 3). Dishing is a common and undesirable side-effect of removing the field region conductive layer 140 and the barrier layer 130 overlying the field region. In other words, the polishing or planarization procedure wears down the tops of the imperfections but also can wear down the crevices of the imperfections. Further, the etchants being used frequently do not remove the barrier layer 130 at the same rate as the conductive layer 140, which contributes to additional formation of surface defects.
  • Figure 4 shows another conventional layered material where the barrier layer 130 is removed after its exposure by subsequent planarization along with removal of sufficient conductive material or layer 140 to retain coplanarity of the metal-filled feature and dielectric layer 120. If the planarization procedure achieves substantially a 1:1 selectivity in the removal of barrier material 130 and conductive layer 140, the direct planarization may be accomplished in one step. However, this is quite an idealistic achievement for any planarization process. Any practical planarization process, such as the one disclosed herein, must take into consideration the effects of dishing and surface topography defects.
  • Figure 5 shows a preferred embodiment of an electronic component 10 contemplated herein comprising a) a substrate layer 110, b) a dielectric layer 120 coupled to the substrate layer 110, c) a barrier layer 130 coupled to the dielectric layer 120, d) a conductive layer 140 coupled to the barrier layer 130, and e) a protective layer 150 coupled to the conductive layer 140.
  • the term "electronic component” means that component that is part of an electronic device, such as a circuit board, a capacitor, a resistor, chip packaging, a layered integrated circuit or an inductor. It is preferred that the electronic component 10 comprises a circuit board or layered integrated circuit.
  • the substrate layer 110 in this embodiment, is designed to a) be functional within the electronic component 10 and b) provide support to the dielectric layer 120.
  • the substrate can comprise virtually any substance upon which a compound or dielectric material can be deposited, as well as repeating layers like the layered structures contemplated herein.
  • contemplated substrates include metals and non-metals, conductors and non-conductors, flexible and inflexible materials, absorbent and non-absorbent materials, flat and curved materials, textured and non-textured materials, and both large and small objects.
  • the substrate comprises silicon, silicon-germanium, gallium-arsenide, indium phosphide, quartz, or sapphire wafer, with the silicon wafer being the most preferred.
  • dielectric constant means a dielectric constant evaluated at 1 MHz to 2 GHz for a material, unless otherwise inconsistent with context. It is contemplated that the value of the dielectric constant of the dielectric layer 120 is less than 3.0. hi a preferred embodiment, the value of the dielectric constant is less than 2.5, and in still more preferred embodiments, the value of the dielectric constant is less than 2.0.
  • the dielectric material or dielectric layer 120 can be designed to satisfy several design goals, such as providing support for the substrate layer 110 and the barrier layer 130, while maintaining a relatively low dielectric constant.
  • the dielectric layer 120 can be coupled to the substrate layer 110 by any suitable process, such as use of an adhesive, hydrogen bonding, electrostatic interactions, Van der Waals forces, and coulombic interactions.
  • the dielectric material 120 may also either be porous or non-porous depending on the structural, electrical, and dielectric needs of the component.
  • Porous dielectric layers 120 are dielectric layers that contain both a solid component, such as an organic, inorganic or organometallic compound, and a plurality of voids.
  • void means a volume in which a mass is replaced with a gas.
  • the composition of the gas is generally not critical, and appropriate gases include relatively pure gases and mixtures thereof, including air.
  • Voids 125 are typically spherical, but may alternatively or additionally have any suitable shape, including tubular, lamellar, discoidal, or other shapes. It is also contemplated that voids 125 may have any appropriate diameter.
  • voids 125 may connect with adjacent voids 125 to create a structure with a significant amount of connected or "open" porosity.
  • Voids 125 preferably have a mean diameter of less than 1 micrometer, and , more preferably have a mean diameter of less than 100 nanometers, and still more preferably have a mean diameter of less than 10 nanometers.
  • voids 125 may be uniformly or randomly dispersed within the dielectric layer 120. h a preferred embodiment, voids 125 are uniformly dispersed within the dielectric layer 120.
  • the dielectric material or layer 120 can be composed of inorganic, organic, or organometallic compounds, as well as mixtures of these materials.
  • contemplated inorganic compounds are silicates, aluminates and compounds containing transition metals.
  • organic compounds include polyarylene ether, polyimides and polyesters.
  • contemplated organometallic compounds include poly(dimethylsiloxane), ⁇ oly(vinylsiloxane) and poly(trifmoropropylsiloxane).
  • the dielectric material 120 may also include substantially polymeric material, substantially monomeric material or a mixture of both polymers and monomers depending on the desired final dielectric composition, desired electrical properties, and desired use of the dielectric material. It is further contemplated that the dielectric material 120 may be composed of amorphous, cross-linked, crystalline, or branched polymers. Preferred components of the dielectric material 120 are inorganic polymers. More preferred components of the dielectric material 120 are inorganic, cross-linked polymers because of the increased durability and polymer strength.
  • crosslinking refers to a process in which at least two molecules, or two portions of a long molecule, are joined together by a chemical interaction.
  • Such interactions may occur in many different ways, including formation of a covalent bond, formation of hydrogen bonds, hydrophobic, hydrophilic, ionic or electrostatic interaction.
  • molecular interaction may also be characterized by an at least temporary physical connection between a molecule and itself or between two or more molecules.
  • Contemplated polymers may also comprise a wide range of functional or structural moieties, including aromatic systems, and halo genated groups. Furthermore, appropriate polymers may have many configurations, including a homopolymer, and a heteropolymer. Moreover, alternative polymers may have various fo ⁇ ns, such as linear, branched, super- branched, or three-dimensional. The molecular weight of contemplated polymers spans a wide range, typically between 400 Dalton and 400000 Dalton or more.
  • the dielectric material 120 comprises inorganic molecules or polymers. In a most preferred embodiment, the dielectric material 120 comprises a polysilicate.
  • the dielectric material 120 may additionally or alternately comprise monomers in order to meet certain design goals and/or structural requirements.
  • the term "monomer” refers to any chemical compound that is capable of forming a covalent bond with itself or a chemically different compound in a repetitive manner. The repetitive bond formation between monomers may lead to a linear, branched, super-branched, or three-dimensional product.
  • monomers may themselves comprise repetitive building blocks, and when polymerized the polymers formed from such monomers are then termed "blockpolymers".
  • Monomers may belong to various chemical classes of molecules including organometallic or inorganic molecules.
  • contemplated organometallic monomers are octamethylcyclotetrasiloxane, methylphenylcyclotetrasiloxane, hexanethyldisilazane, and triethyoxysilane.
  • contemplated inorganic monomers include tetraethoxysilane or aluminum isopropoxide.
  • the molecular weight of monomers may vary greatly between about 40 Dalton and 20000 Dalton. However, especially when monomers comprise repetitive building blocks, monomers may have even higher molecular weights.
  • Monomers may also include additional groups, such as groups used for crosslinking.
  • silicon-containing materials are contemplated as components of the dielectric material 120, including colloidal silica, fumed silica, siloxanes, silsequioxanes, and sol-gel-derived monosize silica.
  • Appropriate silicon- containing compounds preferably have a size of below 100 nm, more preferably below 10 run and most preferably below 5 nm.
  • the dielectric material 120 may comprise materials other than silicon- containing materials, including organic, organometallic or partially-inorganic materials, provided that such materials can be dissolved at least in part in a solvent that does not dissolve the dielectric material 120.
  • appropriate organic materials are polystyrene, and polyvinyl chloride.
  • Contemplated organometallic materials are, for example, octamethylcyclotetrasiloxane.
  • Contemplated inorganic materials are, for example, KNO 3 .
  • the organic and inorganic compounds can be selected such that the inorganic component can be dissolved at least in part by a solution that does not dissolve the organic component of the dielectric material 120.
  • colloidal silica can be dissolved by a dilute HF solution without dissolving an organic polymer such as polyarylene ether.
  • dielectric material 120 may comprise dielectric materials contemplated, produced or disclosed by Honeywell, Inc. including, but not limited to: a) FLARE (poly(arylene ether)), such as those compounds disclosed in issued patents US 5959157, US 5986045, US 6124421, US 6156812, US 6172128, US 6171687, US 6214746, and pending applications 09/197478, 09/538276, 09/544504, 09/741634, 09/651396, 09/545058, 09/587851, 09/618945, 09/619237, 09/792606, b) GX3 (adamantane-based materials), such as those shown in pending application 09/545058, c) nanoporous silica materials and silica-based compounds, such as those compounds disclosed in issued patents US 6022812, US 6037275, US 6042994, US 6048804, US 6090448, US 6126733, US 6140254, US 6204202,
  • FLARE poly(
  • a barrier layer 130 is coupled to the dielectric material 120 by any suitable process, such as use of an adhesive, hydrogen bonding, electrostatic interactions, Van der Waals forces, and coulombic interactions.
  • the barrier layer 130 may comprise any suitable material or materials that is capable of meeting several and sometimes conflicting design goals, such as a) successfully protecting the dielectric layer 120 from any diffusion of the conductive layer 140, b) acting as an "etch stop" - which indicates the end point of the conductive field planarization step, c) reacting to etching chemicals in a 1 to 1 selectivity rate with the conductive layer materials 140, and/or d) not reacting to the etching chemicals at all, such that when the etching chemicals reach the barrier layer 130 none of the barrier layer 130 is removed.
  • Contemplated barrier layers 130 comprise tantalum, tantalum nitride, titanium, titanium nitride, tungsten-nitride, tungsten cobalt phosphorus, and nickel.
  • the barrier layer 130 comprises tantalum, tantalum nitride, or tantalum/tantalum nitride (Ta TaN) stacks.
  • a conductive layer 140 is applied to and coupled to the barrier layer 130 by any suitable deposition method, such as electrodeposition, chemical vapor deposition (CVD), plasma vapor deposition (PVD), and fill deposition.
  • Fill deposition is a process where the conductive layer 140 is applied to fill the interconnect features (vias and trenches) and to coat the flat "field" regions between features leading to a conductive layer 140 covering the entire dielectric layer 120 and the barrier layer 130. Fill deposition typically results in a non-planar surface topography of the conductive layer 140 because of the variation of the size of the underlying dielectric layer 120 features being coated or filled.
  • Conductive layers 140 may generally comprise metals, metal alloys, conductive polymers, conductive composite materials, and any other suitable conductive materials.
  • metal means those elements that are in the d-block and f-block of the Periodic Chart of the Elements, along with those elements that have metal-like properties, such as silicon and germanium.
  • d-block means those elements that have electrons filling the 3d, 4d, 5d, and 6d orbitals surrounding the nucleus of the element.
  • f-block means those elements that have electrons filling the 4f and 5f orbitals surrounding the nucleus of the element, including the lanthanides and the actinides.
  • Preferred metals include titanium, silicon, cobalt, copper, nickel, iron, zinc, vanadium, aluminum, tin, chromium, platinum, palladium, gold, silver, tungsten, molybdenum, cerium, promethium, and thorium. More preferred metals include aluminum, titanium, silicon, copper, nickel, platinum, tin, gold, silver and tungsten. Most preferred metals include copper, aluminum and tungsten.
  • the term "metal” also includes alloys, metal/metal composites, metal ceramic composites, metal polymer composites, as well as other metal composites.
  • the protective layer 150 is coupled to the conductive layer 140 by any suitable process, such as use of an adhesive, hydrogen bonding, electrostatic interactions, Van der Waals forces, and coulombic interactions.
  • the protective layer 150 is also generally contemplated to be a protective or passivating overlayer, which planarizes or can be planarized and that is coupled to the conductive layer 140 initially or at some stage of processing as a liquid, but may be converted into a harder or solid protective layer upon application of a curing process.
  • the protective layer 150 can be deposited onto the conductive layer 140 by a variety of processes, including electroplating, spin-on deposition, evaporative deposition, electroless plating, sputtering/PVD, PECVD, CVD, and/or vacuum evaporation with or without a voltage bias.
  • the protective layer 150 can be composed of inorganic, organic, or organometallic compounds, metals and metal alloys as well as mixtures of these materials.
  • Contemplated inorganic and organic compounds should be those compounds that are a) capable of being controllably etchable at the same time that the coupled conductive layer 140 is being etched, and b) planarizes on the conductive layer 140 before the etching step begins.
  • Planarizing on the conductive layer 140 may comprise either a) a material that melts with a low viscosity and a high surface tension that can flow to form on the conductive layer 140 and/or b) can self-catalyze or self-cure to the desirable hardness on the conductive layer 140 after being applied to the conductive layer 140, or a fluid material that can be mechanically planarized.
  • a material that melts with a low viscosity and a high surface tension that can flow to form on the conductive layer 140 and/or b) can self-catalyze or self-cure to the desirable hardness on the conductive layer 140 after being applied to the conductive layer 140, or a fluid material that can be mechanically planarized.
  • contemplated inorganic compounds are silicates, aluminates, siloxane compounds, HOSP compounds, such as those that are commercially available from Honeywell International, hie.
  • Spin- on Glass compounds such as Honeywell 512B, and compounds containing transition metals.
  • organic compounds include polyarylene ether (FLARE materials), polyimides, Accuflow mixtures (Novalac Resins), acrylic polymers, polyvinyl acetates, PMMA, polyoctadecyl methacrylate, polyvinyl pyridine, Superglues (cyanoacrylates), PVB (polyvinyl buterol) and polyesters.
  • contemplated organometallic compounds include poly(dimethylsiloxane), poly(vinylsiloxane) and poly(trifluoropropylsiloxane).
  • contemplated metals and metal alloys include copper; liquid metals, such a mercury; lead free solder, tin, tin etchant (HC1 + HNO 3 ), gallium and gallium alloys, and bismuth and bismuth alloys (including those with indium), indium and indium alloys.
  • the protective layer 150 may also include substantially polymeric material, substantially monomeric material or a mixture of both polymers and monomers depending on the desired viscous consistency, the desired final consistency if curing is applied to the protective layer, and the desired planarization and etch properties. It is further contemplated that the protective layer 150 maybe composed of amorphous, cross-linked, crystalline, or branched polymers.
  • Contemplated polymers may also comprise a wide range of functional or structural moieties, including aromatic systems, and halogenated groups. Furthermore, appropriate polymers may have many configurations, including a homopolymer, and a heteropolymer. Moreover, alternative polymers may have various forms, such as linear, branched, super- branched, or three-dimensional. The molecular weight of contemplated polymers spans a wide range, typically between 400 Dalton and 400000 Dalton or more.
  • the protective layer 150 comprises inorganic molecules or polymers. In a most preferred embodiment, the protective layer 150 comprises a polysilicate.
  • the protective layer 150 may additionally or alternately comprise monomers in order to meet certain design goals and/or structural requirements, such as those mentioned previously.
  • Monomers may belong to various chemical classes of molecules including organometallic or inorganic molecules. Examples of contemplated organometallic monomers are octamethylcyclotetrasiloxane, methylphenylcyclotetrasiloxane, hexanethyldisilazane, and triethyoxysilane. Examples of contemplated inorganic monomers include tetraethoxysilane or aluminum isopropoxide. Monomers may also include additional groups, such as groups used for crosslinking.
  • silicon-containing materials are contemplated as components of the protective layer 150, including colloidal silica, fumed silica, siloxanes, silsequioxanes, and sol-gel-derived monosize silica.
  • Appropriate silicon-containing compounds preferably have a size of below 100 nm, more preferably below 10 nm and most preferably below 5 nm.
  • Preferred silicon-containing compounds include Honeywell spin-on glass materials, such as Honeywell 314 and Honeywell 512B.
  • the protective layer 150 may also comprise low temperature melting metals or metal alloys, preferably lead free, and will generate environmentally benign etching byproducts.
  • a protective layer 150 comprising these metals or metal alloys must have a melting temperature below 400°C, which is considered the thermal budget of the wafer.
  • Contemplated metals or metal alloys must not rapidly form alloys or intermetallic compounds with the existing conductive layer 140 onto which they have been deposited.
  • An additional barrier layer can be deposited over the conductive copper layer, as part of the protective layer, to prevent liquid of solid-state diffusion of the overlayer metal into the conductive material.
  • Nickel is an example of a material that has successfully prevented this type of diffusion into the conductive layer, which could damage the final electrical properties of the conductive layer.
  • An electronic component 10 can be produced by a) providing a substrate 110; b) coupling a dielectric layer 120 to the substrate 110; c) coupling a barrier layer 130 to the dielectric layer 120; d) coupling a conductive layer 140 to the barrier layer 130; and e) coupling a protective layer 150 to the conductive layer 140.
  • the protective layer 150 may then be cured to a desirable hardness.
  • the barrier layer 130 can be deposited onto the dielectric layer, the conductive layer 140 can be deposited on the barrier layer 130 and the protective layer 150 can be deposited onto the conductive layer 140 by a variety of processes, including electroplating, spin-on deposition, evaporative deposition, electroless plating, sputtering/PVD, PECVD, CVD, and/or vacuum evaporation with or without a voltage bias.
  • the protective layer 150 can be cured either by a process external to the material in the protective layer 150 or may be cured by a process internal to the material in the protective layer
  • External processes include but are not limited to heat, radiation, air flow, pressure, and decrease in temperature.
  • Internal processes are those processes that take place within the compound itself, such as crosslinking, chemical reactions between constituents that are not initiated by outside forces and other related processes.
  • a method of planarizing a conductive layer 150 of an electronic component 10 may comprise a) introducing or coupling a protective layer 140 onto a conductive layer 150; b) dispersing and planarizing the protective layer 150 across the conductive layer 140; c) curing the protective layer 150; d) introducing an etching solution 170 (not shown) onto the conductive layer 140; and e) etching the conductive layer 140 to substantial planarity.
  • Introducing or coupling the protective layer 150 onto the conductive layer 140 can be achieved by a variety of processes, including electroplating, spin-on deposition, evaporative deposition, electroless plating, sputtering/PVD, PECVD, CVD, and/or vacuum evaporation with or without a voltage bias. It is contemplated that the protective layer 150 will be introduced onto the conductive surface 140 in such quantities that preferential protection to depressed regions of the conductive surface 140 will be accomplished.
  • Dispersing the protective layer 150 across the conductive layer 140 is accomplished through relative motion of the electronic component 10. Relative motion is contemplated to mean spinning the component 10, shaking the component 10, rocking the component 10, or otherwise moving the component 10 around to disperse the protective layer 150.
  • Curing the protective layer 150 is contemplated to encompass the methods previously discussed herein, including external and internal curing processes.
  • External processes include but are not limited to heat, radiation or irradiation, air flow, pressure, ashing (exposure to an oxygen or oxygen-mixture with nitrogen, hydrogen or forming gas plasma), a decrease in temperature or a combination of any of the above-mentioned curing processes.
  • Internal processes are those processes that take place within the compound itself, such as crosslinking, chemical reactions between constituents that are not initiated by outside forces and other related processes.
  • etching solution 170 (not shown) onto the conductive layer 140 maybe accomplished by any suitable means, including spin-on deposition, random deposition, surface washing, dipping, dripping, and rolling the etching solution 170 onto the surface.
  • Typical and contemplated etching solutions comprise one or more of the following: HNO 3 , H 3 PO , CH 3 COOH, HCl, chlorides of copper and zinc, HBr, H 2 SO and HF.
  • Preferred etching solutions comprise: a) 69 weight % (wt %)/10 volume % (vol %) HNO 3 , 85 wt %/50 vol % H 3 PO 4 , and 98 wt %/40 vol % CH 3 COOH; b) 69 weight % (wt %)/6 volume % (vol %) HNO 3 , 85 wt %/70 vol % H 3 PO 4 , and 98 wt %/24 vol % CH 3 COOH; 69 weight % (wt %)/1.6 volume % (vol %) HNO 3 , 85 wt %/53.9 vol % H 3 PO 4 , and 98 wt %/43.2 vol % CH 3 COOH; 49 wt %/l .3 vol % HF.
  • substantially planarity generally means that degree of planarity that is considered to be acceptable for the contemplated or desired electronic component.
  • Substantial planarity is considered herein to be a degree of planarity of at least 0.6 or 60% or achieving perfect planarity.
  • substantial planarity is considered to be a degree of planarity of at least 0.8 or 80%.
  • substantial planarity is considered to be a degree of planarity of at least 0.9 or 90%.
  • a 1000 Angstrom thick nickel barrier layer is deposited on a copper substrate/conductive layer by vacuum evaporation.
  • a planarizer material/protective layer comprising 66.3 wt % Indium and 33.7 wt % of Bismuth as a eutectic alloy is deposited on the barrier layer by vacuum evaporation to a thickness of 1.5 ⁇ m.
  • Both the nickel barrier layer and indium bismuth protective layer are deposited by using a vacuum evaporative deposition tool to form a wafer. This deposition tool uses electron beam evaporation of any elemental or alloy metal allowing deposition under a vacuum atmosphere.
  • the copper substrate/conductive layer surface was precleaned with an argon sputter using a voltage bias before the nickel barrier layer and the indium bismuth protective layer were deposited. Both the nickel barrier layer and the indium bismuth protective layer were deposited without "breaking" or turning off the vacuum after precleaning.
  • the barrier layer and the conductive layer discussed above may also be deposited also by electroplating and electroless plating, which are both economical methods. Electroplating is a simple scale-up from existing copper plating technology used today by the integrated circuits industry. Lead free solder materials, similar to the ones used herein, are generally developed by using electroplating or electroless plating options for the electronics packaging industries to eliminate toxic lead from the solder. Tin Copper and Indium Tin alloys were also successfully deposited with these methods.
  • the wafer containing the barrier layer and the protective layer was predipped in 85 wt % H 3 PO and rinsed with deionized (DI) water to remove oxidized surface material.
  • DI deionized
  • the wafer is then rapidly heated on a hotplate with an approximate temperature of 280°C, which is well above the 75°C indium bismuth melting point, but well below the nickel or copper melting point or the allowable 400°C that the wafer substrate can withstand without damage to the pre-existing electrical materials/structures.
  • the wafer was heated until the indium bismuth melted (less than 2 seconds) and then the wafer was rapidly cooled.
  • the final structure allowed surface planarization of even very large features or surface defects, i.e. those greater than 100 ⁇ m across for 0.5 ⁇ , deep features.
  • the final indium bismuth planarization was measured using a KLA- Tencor HRP-220 mechanical stylus profilometer.
  • the planarization results are summarized in Figure 7.
  • DoP is an abbreviation for "degree of planarization” where 1.0 is perfect planarization of a trench feature and 0.0 is no planarization.
  • hi situ reflow within the above- mentioned vacuum chamber will give improved results over conventional methods with fewer surface defects or features.
  • immediate reflow of the indium bismuth after electroplating or electroless plating deposition will give improves results over conventional methods with fewer surface defects or features.
  • etch rate results (Angstroms/min) for individual metal films are as follows for each type of etchant mix as listed above:
  • the across-wafer non- uniformity will be less than 5 % 3-sigma for all metals.
  • the planar indium bismuth surface will be uniformly etched at an equal rate as both the nickel and copper substrate leaving a final copper surface that is planar. Once the copper surface is planar and all sacrificial nickel and indium smuth is gone, then Mix A can be used to finish copper removal and polishing until stopping in the Ta on the field.
  • a composition for a protective layer comprises the following components: colloidal copper oxide, copper hydrogen phosphate salts, copper acetate, copper nitrate and/or colloidal copper; and a polymeric solution of high viscosity having gelling/solidification properties suitable for functioning as the protective layer defined herein, to be used as the binder or matrix phase of the protective layer.
  • the polymeric binder composition is an aqueous solution of high molecular weight polyethylene, polyvinyl alcohol, polyvinylpyrrolidone of such polymeric solutions doped with a solution of colloidal silica or boehmite to facilitate the formation of a rigid gel at a suitable temperature (preferably near room temperature) in the course of time and also to reduce the etch rate of the coatings to achieve nearly 1:1 selectivity with copper etching.
  • the etching behavior of the standard etch solution can be altered by adding a polyethylene glycol or high molecular weight polyethylene oxide (when using a polyethylene-based protective layer). Such additives tend to lower the etch rate of the spin-on protective layer but do not change the copper etch rate, permitting an etch selectivity of 1 : 1 to be achieved.
  • phosphate-containing groups in a copper phosphate protective layer will likewise contribute to a reduction in the etch rate, when etching with etchants containing phosphoric acid.
  • copper salts such as copper hydrogen phosphate
  • copper hydrogen phosphate can reduce the dissolution of copper at the copper interface as the etching solution produces this type of insoluble copper phosphate.
  • saturation of copper-containing compound at the interface will act as a chemical inhibiting layer.
  • a planarizer material/protective layer comprising an Accuflow material (Novalac Resin) is deposited on the conductive layer by spin track dispense.
  • the spin speed of the chuck is ramped up to create a uniform layer of Accuflow of a thickness of 1.5 um. This ramping and subsequent hot plate bakes drive off the solvent dispensed with the Accuflow as well as partially reflow the protective layer.
  • the wafer containing the protective layer was cured in a furnace to drive off all remaining solvents and to complete the reflow of the Accuflow at a temperature of 350°C, well below the copper melting point or the allowable 400C that the wafer substrate can withstand without damage to the pre-existing electrical materials/structures.
  • the final structure allowed surface, planarization of even very large features or surface defects, i.e. those greater than 100 ⁇ m across for 0.5 ⁇ , deep features.
  • the final Accuflow planarization was measured using a KLA- Tencor HRP-220 mechanical stylus profilometer. Once cured the Accuflow and conductor can be etched with 1 : 1 selectivity maintaining planarity of the surface.
  • A can be used to finish copper removal and polishing until stopping in the Ta on the field.
  • a planarizer material/protective layer comprising Honeywell 512B spin on glass material is deposited on the conductive layer by spin track dispense.
  • the spin speed of the chuck is ramped up to create a uniform layer of 512B of a thickness of 1.0 um. This ramping and subsequent hot plate bakes drive off the solvent dispensed with the 512B as well as partially reflow the protective layer.
  • the wafer containing the protective layer was cured in a furnace to drive off all remaining solvents and to complete the reflow of the 512B at a temperature of 350°C, well below the copper melting point or the allowable 400°C that the wafer substrate can withstand without damage to the pre-existing electrical materials/structures.
  • the final structure allowed surface planarization of even very large features or surface defects, i.e. those greater than 100 ⁇ m across for 0.5 ⁇ , deep features.
  • the final Honeywell 512B planarization was measured using a KLA- Tencor HRP-220 mechanical stylus profilometer. Once cured the 512B and conductor can be etched with 1 : 1 selectivity maintaining planarity of the surface.
  • Mix A can be used to finish copper removal and polishing until stopping in the Ta on the field.
  • Gallium, gallium indium, gallium alloys, and indium alloys were successfully evaporatively deposited onto bare, blanket copper, patterned copper and blanket Ta coated silicon wafers.
  • the melted material can be spun onto the wafer using standard spin tools.
  • the wafer will stand for a few seconds to allow the molten metal flow fill recesses and thereby planarize the wafer.
  • the wafer is chilled to slightly below sub-ambient temperature (less than 20°C) to solidify the metal planarizer.
  • a warm solution or warm water can be used along with many common etchants (nitric acid) to remove the metal planarizer at a 1 :1 selectivity with the copper from the wafer which has its sub-ambient temperature maintained by the surrounding instrumentation.
  • the copper will require an active acid or base for its removal while a warm liquid - even warm water could be used for the metal planarizer removal while an acid (which does not attack the metal planarizer) could be used in the etching solution to remove the copper.
  • the salt-like or molten salt Planarizers such as BiONO 3 , B 10 H 1 , B(OH) 3 , HBO 2 - alpha, beta or gamma, copper acetate, copper nitrate, FeCl 3 , LiClO , Mg(OH) 2 , Mn(C2H 3 O 2 )*4H 2 O, KNO 3 , Ag 2 CO 3 , SO 2 (NH 2 )2, SNC1 2 , and Zn(OH) 2 , are applied as a powder or spun on as a slurry to control thickness. The wafer is then heated in a controlled atmosphere (vacuum or inert gas) to melt the salt without damaging the existing patterned copper damascene features.
  • a controlled atmosphere vacuum or inert gas
  • the melted salt can then flow into the recessed areas, in a similar manner to the molten metals/metal planarizers listed above, thereby planarizing patterned copper features.
  • the wafer is then cooled to re-solidify the salts into a planar film on top of the pattered copper.
  • the etchant is then formulated to remove the copper and at the same time have the proper water and/or acid composition to remove the salt at a substantially 1 : 1 rate with the copper.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

L'invention concerne un composant électronique comprenant une couche (110) de substrat, une couche (120) diélectrique couplée à la couche (110) de substrat, un couche (130) d'arrêt couplée avec la couche (120) diélectrique, une couche (140) conductrice couplée avec la couche d'arrêt et une couche (150) protectrice couplée avec la couche (140) conductrice. L'invention concerne également un procédé permettant de produire un composant électronique. Ce procédé comprend les étapes suivantes : on introduit une couche (150) protectrice dans la couche (140) conductrice ou on assemble une couche protectrice à la couche à la couche (140) conductrice, on disperse cette couche (150) protectrice dans la couche (140) conductrice, on fait durcir la couche (150) protectrice, on introduit une solution de gravure dans la couche (140) conductrice et on grave la surface conductrice jusqu'à la rendre sensiblement plane.
PCT/US2002/001861 2001-01-23 2002-01-22 Agents de planarisation pour planarisation par gravure centrifuge de composants electroniques et procedes d'utilisation WO2002059966A1 (fr)

Priority Applications (5)

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KR10-2003-7009631A KR20030086251A (ko) 2001-01-23 2002-01-22 전자 컴포넌트의 스핀 에칭 평탄화를 위한 평탄화기 및이를 이용한 방법
JP2002560195A JP2004523898A (ja) 2001-01-23 2002-01-22 電子素子のスピンエッチ平坦化のための平坦化材およびその使用方法
CA002432012A CA2432012A1 (fr) 2001-01-23 2002-01-22 Agents de planarisation pour planarisation par gravure centrifuge de composants electroniques et procedes d'utilisation
EP02704222A EP1354355A1 (fr) 2001-01-23 2002-01-22 Agents de planarisation pour planarisation par gravure centrifuge de composants electroniques et procedes d'utilisation
AU2002237917A AU2002237917A1 (en) 2001-01-23 2002-01-22 Planarizers for spin etch planarization of electronic components and methods of use thereof

Applications Claiming Priority (4)

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US09/768,439 US6696358B2 (en) 2001-01-23 2001-01-23 Viscous protective overlayers for planarization of integrated circuits
US09/768,439 2001-01-23
US09/847,766 2001-05-01
US09/847,766 US6600229B2 (en) 2001-01-23 2001-05-01 Planarizers for spin etch planarization of electronic components

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006520541A (ja) * 2003-03-14 2006-09-07 ラム　リサーチ　コーポレーション 改良された局所的なデュアルダマシン平坦化のためのシステム、方法、および装置
WO2007096095A2 (fr) * 2006-02-22 2007-08-30 Fraunhofer-Gesellschaft Zür Förderung Der Angewandten Forschung E.V. Solution d'attaque et procédé de structuration d'un système de couches de métallisation sous bosse
JP2007533116A (ja) * 2003-03-14 2007-11-15 ラム　リサーチ　コーポレーション 改良されたグローバルデュアルダマシン平坦化のためのシステム、方法、及び装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6146991A (en) * 1999-09-03 2000-11-14 Taiwan Semiconductor Manufacturing Company Barrier metal composite layer featuring a thin plasma vapor deposited titanium nitride capping layer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6146991A (en) * 1999-09-03 2000-11-14 Taiwan Semiconductor Manufacturing Company Barrier metal composite layer featuring a thin plasma vapor deposited titanium nitride capping layer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006520541A (ja) * 2003-03-14 2006-09-07 ラム　リサーチ　コーポレーション 改良された局所的なデュアルダマシン平坦化のためのシステム、方法、および装置
JP2007533116A (ja) * 2003-03-14 2007-11-15 ラム　リサーチ　コーポレーション 改良されたグローバルデュアルダマシン平坦化のためのシステム、方法、及び装置
JP4859664B2 (ja) * 2003-03-14 2012-01-25 ラム リサーチ コーポレーション 改良されたグローバルデュアルダマシン平坦化方法
WO2007096095A2 (fr) * 2006-02-22 2007-08-30 Fraunhofer-Gesellschaft Zür Förderung Der Angewandten Forschung E.V. Solution d'attaque et procédé de structuration d'un système de couches de métallisation sous bosse
WO2007096095A3 (fr) * 2006-02-22 2008-02-07 Fraunhofer Ges Zuer Foerderung Solution d'attaque et procédé de structuration d'un système de couches de métallisation sous bosse

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JP2004523898A (ja) 2004-08-05
WO2002059966A8 (fr) 2003-10-16

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