WO2002058163A8 - Verfahren zum herstellen von halbleiterbauelementen - Google Patents

Verfahren zum herstellen von halbleiterbauelementen

Info

Publication number
WO2002058163A8
WO2002058163A8 PCT/EP2001/014614 EP0114614W WO02058163A8 WO 2002058163 A8 WO2002058163 A8 WO 2002058163A8 EP 0114614 W EP0114614 W EP 0114614W WO 02058163 A8 WO02058163 A8 WO 02058163A8
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
layer
crystalline
semiconductor components
laminae
Prior art date
Application number
PCT/EP2001/014614
Other languages
English (en)
French (fr)
Other versions
WO2002058163A2 (de
WO2002058163A3 (de
Inventor
Holger Juergensen
Assadullah Alam
Alois Krost
Armin Dadgar
Michael Heuken
Original Assignee
Aixtron Ag
Holger Juergensen
Assadullah Alam
Alois Krost
Armin Dadgar
Michael Heuken
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aixtron Ag, Holger Juergensen, Assadullah Alam, Alois Krost, Armin Dadgar, Michael Heuken filed Critical Aixtron Ag
Priority to AU2002238422A priority Critical patent/AU2002238422A1/en
Publication of WO2002058163A2 publication Critical patent/WO2002058163A2/de
Publication of WO2002058163A3 publication Critical patent/WO2002058163A3/de
Publication of WO2002058163A8 publication Critical patent/WO2002058163A8/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0201—Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth

Abstract

Die Erfindung betrifft ein Verfahren zum Herstellen von kleinen kristalinen Plättchen, wie Halbleiterbauelemente, insbesondere LED's, bei dem auf ein kristallines Substrat eine oder mehrere kristalline Schichten abgeschieden werden und anschliessend die Schicht(en) vom Substrat getrennt, in die Plättchen bildenden Teilstükke zerteil werden. Zur Vereinfachung der Vereinzelung sieht die Erfindung vor, dass das Substrat (1) in den Teilstücken (7) entsprechende Felder (3) vorstrukturiert wird und die Gitterkonstanten von Substrat (1) und Schicht(en) (9, 10) derart voneinander abweichen, dass an den Feldgrenzen (4) zufolge der Gitterverspannung Trennrisse entstehen.
PCT/EP2001/014614 2001-01-18 2001-12-12 Verfahren zum herstellen von halbleiterbauelementen WO2002058163A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002238422A AU2002238422A1 (en) 2001-01-18 2001-12-12 Method for producing semiconductor components

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10102315.4 2001-01-18
DE10102315A DE10102315B4 (de) 2001-01-18 2001-01-18 Verfahren zum Herstellen von Halbleiterbauelementen und Zwischenprodukt bei diesen Verfahren

Publications (3)

Publication Number Publication Date
WO2002058163A2 WO2002058163A2 (de) 2002-07-25
WO2002058163A3 WO2002058163A3 (de) 2002-12-12
WO2002058163A8 true WO2002058163A8 (de) 2003-03-06

Family

ID=7671092

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/014614 WO2002058163A2 (de) 2001-01-18 2001-12-12 Verfahren zum herstellen von halbleiterbauelementen

Country Status (3)

Country Link
AU (1) AU2002238422A1 (de)
DE (1) DE10102315B4 (de)
WO (1) WO2002058163A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8168000B2 (en) 2005-06-15 2012-05-01 International Rectifier Corporation III-nitride semiconductor device fabrication
KR101039970B1 (ko) * 2010-02-11 2011-06-09 엘지이노텍 주식회사 반도체층 형성방법 및 발광 소자 제조방법
DE102018111227A1 (de) * 2018-05-09 2019-11-14 Osram Opto Semiconductors Gmbh Verfahren zum Durchtrennen eines epitaktisch gewachsenen Halbleiterkörpers und Halbleiterchip

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52135667A (en) * 1976-05-10 1977-11-12 Toshiba Corp Dicing method of semiconductor wafer
KR930008861B1 (ko) * 1991-05-16 1993-09-16 재단법인 한국전자통신연구소 단결정 실리콘 기판상에 화합물 반도체층이 형성된 기판의 제조방법
JP2748354B2 (ja) * 1993-10-21 1998-05-06 日亜化学工業株式会社 窒化ガリウム系化合物半導体チップの製造方法
JPH0864791A (ja) * 1994-08-23 1996-03-08 Matsushita Electric Ind Co Ltd エピタキシャル成長方法
US5882988A (en) * 1995-08-16 1999-03-16 Philips Electronics North America Corporation Semiconductor chip-making without scribing
JPH10125629A (ja) * 1996-10-17 1998-05-15 Nec Eng Ltd 半導体ウェーハ割断方法
DE19715572A1 (de) * 1997-04-15 1998-10-22 Telefunken Microelectron Verfahren zum Herstellen von epitaktischen Schichten eines Verbindungshalbleiters auf einkristallinem Silizium und daraus hergestellte Leuchtdiode
KR20010021494A (ko) * 1997-07-03 2001-03-15 추후제출 에피택셜 증착에 의한 프리 스탠딩 기판의 제조를 위한열적 부정합 보정
DE19838810B4 (de) * 1998-08-26 2006-02-09 Osram Opto Semiconductors Gmbh Verfahren zum Herstellen einer Mehrzahl von Ga(In,Al)N-Leuchtdiodenchips
EP0996145A3 (de) * 1998-09-04 2000-11-08 Canon Kabushiki Kaisha Verfahren zur Herstellung von Halbleitersubstraten
JP3235586B2 (ja) * 1999-02-25 2001-12-04 日本電気株式会社 半導体装置及び半導体装置の製造方法
JP2001015721A (ja) * 1999-04-30 2001-01-19 Canon Inc 複合部材の分離方法及び薄膜の製造方法

Also Published As

Publication number Publication date
AU2002238422A1 (en) 2002-07-30
WO2002058163A2 (de) 2002-07-25
WO2002058163A3 (de) 2002-12-12
DE10102315B4 (de) 2012-10-25
DE10102315A1 (de) 2002-07-25

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