WO2002048880A3 - Unterbrecher-steuereinrichtung - Google Patents

Unterbrecher-steuereinrichtung Download PDF

Info

Publication number
WO2002048880A3
WO2002048880A3 PCT/EP2001/014792 EP0114792W WO0248880A3 WO 2002048880 A3 WO2002048880 A3 WO 2002048880A3 EP 0114792 W EP0114792 W EP 0114792W WO 0248880 A3 WO0248880 A3 WO 0248880A3
Authority
WO
WIPO (PCT)
Prior art keywords
interrupt
processor
interfaces
priority value
branching
Prior art date
Application number
PCT/EP2001/014792
Other languages
English (en)
French (fr)
Other versions
WO2002048880A2 (de
Inventor
Joerg Franke
Joachim Ritter
Original Assignee
Micronas Gmbh
Joerg Franke
Joachim Ritter
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micronas Gmbh, Joerg Franke, Joachim Ritter filed Critical Micronas Gmbh
Priority to US10/204,122 priority Critical patent/US20030172215A1/en
Priority to JP2002550524A priority patent/JP2004516547A/ja
Priority to EP01990568A priority patent/EP1417579A2/de
Publication of WO2002048880A2 publication Critical patent/WO2002048880A2/de
Publication of WO2002048880A3 publication Critical patent/WO2002048880A3/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Abstract

Unterbrecher-Steuereinrichtung zur Zugangssteuerung von Unterbrecherquellen (11, 12, 13, 14) an einen Prozessor (100) und zur Steuerung der zugehörigen Programmverzweigung der aktuell ablaufenden Signalverarbeitung (Rx) mit einer aktuellen Priorität (Px) im Prozessor. Eingangsseitig enthält die die Unterbrecher-Steuereinrichtung eine vorgegebene Anzahl von Unterbrecherschnittstellen (21, 22, 23,24) zum Anschluß der Unterbrecherquellen, wobei jeder Unterbrecherschnittstelle (21, 22, 23, 24) ein Prioritätswert (Pi) und eine Adresse (Adi) zugeordnet ist. Eine Auswahleinrichtung (30) bestimmt aus den aktivierten Unterbrecherschnittstellen diejenige mit dem höchsten Prioritätswert (Pmax). Die Durchschaltung der einzelnen Unterbrecherschnittstellen (21, 22, 23, 24) auf den Prozessor (100) als Interrupt-Request (IR) ist von einem Prioritätsvergleicher (40) und einer Verzweigungslogik (60) abhängig, die in Abhängigkeit von dem ermittelten Prioritätswert (Pmax) und dem aktuellen Prioritätswert (Px) das Auslösung einer Kontextsicherung (I) im Prozessor (100) steuern, wobei die Verzweigungslogik die zugehörigen Verzweigungsadressen (Vi) möglichst erst am Ende der ablaufenden Kontextsicherung (I) bestimmt, um während der Kontextsicherung I noch eingehende Unterbrechungsanforderungen zu berücksichtigen.
PCT/EP2001/014792 2000-12-16 2001-12-14 Unterbrecher-steuereinrichtung WO2002048880A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/204,122 US20030172215A1 (en) 2000-12-16 2001-12-14 Interrupt- controller
JP2002550524A JP2004516547A (ja) 2000-12-16 2001-12-14 中断制御装置
EP01990568A EP1417579A2 (de) 2000-12-16 2001-12-14 Unterbrecher-steuereinrichtung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10062995.4 2000-12-16
DE10062995A DE10062995A1 (de) 2000-12-16 2000-12-16 Unterbrecher-Steuereinrichtung

Publications (2)

Publication Number Publication Date
WO2002048880A2 WO2002048880A2 (de) 2002-06-20
WO2002048880A3 true WO2002048880A3 (de) 2004-02-26

Family

ID=7667591

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/014792 WO2002048880A2 (de) 2000-12-16 2001-12-14 Unterbrecher-steuereinrichtung

Country Status (5)

Country Link
US (1) US20030172215A1 (de)
EP (1) EP1417579A2 (de)
JP (1) JP2004516547A (de)
DE (1) DE10062995A1 (de)
WO (1) WO2002048880A2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030004763A (ko) * 2001-07-06 2003-01-15 삼성전자 주식회사 인터럽트 처리장치
CN100382017C (zh) * 2002-07-09 2008-04-16 徐肇昌 子序网模块及其调用方法
WO2004114132A1 (ja) * 2003-06-20 2004-12-29 Fujitsu Limited 割り込み制御方法、割り込み制御装置及び割り込み制御プログラム
EP1531395A1 (de) * 2003-11-17 2005-05-18 Infineon Technologies AG Verfahren zum Ermitteln von Informationen über Prozesse bei der Ausführung eines Programms in einer programmgesteuerten Einheit
CN101128808A (zh) * 2005-02-28 2008-02-20 皇家飞利浦电子股份有限公司 具有中断控制器的数据处理系统和中断控制方法
GB2433794B (en) 2005-12-21 2010-08-18 Advanced Risc Mach Ltd Interrupt controller utiilising programmable priority values
FR2896934A1 (fr) * 2006-02-01 2007-08-03 Parrot Sa Composant integre comprenant des circuits de gestion de l'alimentation et de gestion des etats d'urgence
JP5308383B2 (ja) * 2010-03-18 2013-10-09 パナソニック株式会社 仮想マルチプロセッサシステム
JP7249968B2 (ja) * 2020-03-09 2023-03-31 株式会社東芝 情報処理装置およびストレージ
CN113138949A (zh) * 2021-04-29 2021-07-20 上海阵量智能科技有限公司 中断控制器、中断控制方法、芯片、计算机设备以及介质

Citations (2)

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Publication number Priority date Publication date Assignee Title
US3984820A (en) * 1975-06-30 1976-10-05 Honeywell Information Systems, Inc. Apparatus for changing the interrupt level of a process executing in a data processing system
WO1999034298A1 (en) * 1997-12-31 1999-07-08 Intel Corporation Apparatus and method for initiating hardware priority management by software controlled register access

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Publication number Priority date Publication date Assignee Title
US4972342A (en) * 1988-10-07 1990-11-20 International Business Machines Corporation Programmable priority branch circuit
US5287523A (en) * 1990-10-09 1994-02-15 Motorola, Inc. Method for servicing a peripheral interrupt request in a microcontroller
JPH0721035A (ja) * 1993-07-02 1995-01-24 Mitsubishi Denki Eng Kk データ処理装置
US5850555A (en) * 1995-12-19 1998-12-15 Advanced Micro Devices, Inc. System and method for validating interrupts before presentation to a CPU
US6021458A (en) * 1998-01-21 2000-02-01 Intel Corporation Method and apparatus for handling multiple level-triggered and edge-triggered interrupts
JP3097648B2 (ja) * 1998-02-04 2000-10-10 日本電気株式会社 情報処理装置及び情報処理方法
US6081867A (en) * 1998-05-20 2000-06-27 Sony Corporation Software configurable technique for prioritizing interrupts in a microprocessor-based system
KR100317237B1 (ko) * 1999-10-01 2001-12-22 윤종용 유사 벡터 방식의 인터럽트 컨트롤러 및 그것의 인터럽트 처리 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3984820A (en) * 1975-06-30 1976-10-05 Honeywell Information Systems, Inc. Apparatus for changing the interrupt level of a process executing in a data processing system
WO1999034298A1 (en) * 1997-12-31 1999-07-08 Intel Corporation Apparatus and method for initiating hardware priority management by software controlled register access

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "CEVF-3 V3.2 Dashboard Controller-Emulator", 29 July 1999, MICRONAS INTERMETALL, XP002260202 *

Also Published As

Publication number Publication date
JP2004516547A (ja) 2004-06-03
EP1417579A2 (de) 2004-05-12
US20030172215A1 (en) 2003-09-11
WO2002048880A2 (de) 2002-06-20
DE10062995A1 (de) 2002-07-11

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