WO2002045165A3 - Dicht gepackte halbleiterstruktur und verfahren zum herstellen einer solchen - Google Patents

Dicht gepackte halbleiterstruktur und verfahren zum herstellen einer solchen Download PDF

Info

Publication number
WO2002045165A3
WO2002045165A3 PCT/EP2001/013900 EP0113900W WO0245165A3 WO 2002045165 A3 WO2002045165 A3 WO 2002045165A3 EP 0113900 W EP0113900 W EP 0113900W WO 0245165 A3 WO0245165 A3 WO 0245165A3
Authority
WO
WIPO (PCT)
Prior art keywords
insulation layer
semiconductor structure
insulation
metallic conductor
conductor strips
Prior art date
Application number
PCT/EP2001/013900
Other languages
English (en)
French (fr)
Other versions
WO2002045165A2 (de
Inventor
Albrecht Kieslich
Falko Hoehnsdorf
Detlef Weber
Original Assignee
Infineon Technologies Ag
Albrecht Kieslich
Falko Hoehnsdorf
Detlef Weber
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Albrecht Kieslich, Falko Hoehnsdorf, Detlef Weber filed Critical Infineon Technologies Ag
Priority to EP01999003A priority Critical patent/EP1340260A2/de
Priority to US10/432,770 priority patent/US6864170B2/en
Priority to KR10-2003-7007108A priority patent/KR100533401B1/ko
Priority to JP2002547229A priority patent/JP2004515079A/ja
Publication of WO2002045165A2 publication Critical patent/WO2002045165A2/de
Publication of WO2002045165A3 publication Critical patent/WO2002045165A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Die Erfindung betrifft eine dicht gepackte Halbleiterstruktur, die umfasst: eine Isolatorschicht auf einem Halbleitersubstrat und wenigstens zwei metallische Leiterbahnen (7, 8) in der Isolatorschicht. Um die kapazitive Kopplung zwischen benachbarten metallischen Leiterbahnen einer Halbleiterstruktur zu verringern und damit die Herstellung einer dichter gepackten Halbleiterstruktur zu ermöglichen, ist die erfindungsgemäße Halbleitervorrichtung dadurch gekennzeichnet, dass die Isolatorschicht eine erste Isolatorschicht (1) vorgegebener Dicke aus einem ersten Isolatormaterial und einer zweite Isolatorschicht (10) vorgegebener Dicke aus einem zweiten Isolatormaterial umfasst, die über der ersten Isolatorschicht (1) angeordnet ist, wobei die wenigstens zwei metallischen Leiterbahnen (7, 8) sich aus der ersten Isolatorschicht (10) hinein erstrecken, und das zweite Isolatormaterial eine niedrigere relative Dielektrizitätskonstante als das erste Isolatormaterial aufweist.
PCT/EP2001/013900 2000-11-28 2001-11-28 Dicht gepackte halbleiterstruktur und verfahren zum herstellen einer solchen WO2002045165A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP01999003A EP1340260A2 (de) 2000-11-28 2001-11-28 Dicht gepackte halbleiterstruktur und verfahren zum herstellen einer solchen
US10/432,770 US6864170B2 (en) 2000-11-28 2001-11-28 Compact semiconductor structure
KR10-2003-7007108A KR100533401B1 (ko) 2000-11-28 2001-11-28 반도체 구조체 상의 상호 접속부들간에 용량성 결합을 감소시키기 위한 반도체 제조 방법
JP2002547229A JP2004515079A (ja) 2000-11-28 2001-11-28 小型の半導体構造およびその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10059935.4 2000-11-28
DE10059935A DE10059935A1 (de) 2000-11-28 2000-11-28 Dicht gepackte Halbleiterstruktur und Verfahren zum Herstellen einer solchen

Publications (2)

Publication Number Publication Date
WO2002045165A2 WO2002045165A2 (de) 2002-06-06
WO2002045165A3 true WO2002045165A3 (de) 2002-11-21

Family

ID=7665549

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/013900 WO2002045165A2 (de) 2000-11-28 2001-11-28 Dicht gepackte halbleiterstruktur und verfahren zum herstellen einer solchen

Country Status (6)

Country Link
US (1) US6864170B2 (de)
EP (1) EP1340260A2 (de)
JP (1) JP2004515079A (de)
KR (1) KR100533401B1 (de)
DE (1) DE10059935A1 (de)
WO (1) WO2002045165A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103124474B (zh) * 2006-04-25 2017-11-28 日立化成株式会社 带粘接层的导体箔、贴有导体的层叠板、印制线路板及多层线路板
KR101106318B1 (ko) * 2008-12-03 2012-01-18 전주대학교 산학협력단 한지난석 제조 방법 및 장치

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4319070A1 (de) * 1992-06-24 1994-01-05 Mitsubishi Electric Corp Halbleitervorrichtung und Herstellungsverfahren dafür
EP0687004A1 (de) * 1994-06-07 1995-12-13 Texas Instruments Incorporated Verfahren zur Herstellung von Dielektrica auf Halbleiterbauelemente
EP0759635A2 (de) * 1995-08-23 1997-02-26 International Business Machines Corporation Planare Endpassivierung für Halbleiterbauelemente
US5747880A (en) * 1994-05-20 1998-05-05 Texas Instruments Incorporated Interconnect structure with an integrated low density dielectric
JPH11163523A (ja) * 1997-11-06 1999-06-18 United Microelectron Corp ランドレスバイアホールとガス誘電体を備えた多層間接続構造の形成方法
JPH11354638A (ja) * 1998-06-12 1999-12-24 Fujitsu Ltd 配線形成方法及び配線構造
US6066577A (en) * 1996-11-08 2000-05-23 International Business Machines Corporation Method for providing fluorine barrier layer between conductor and insulator for degradation prevention
JP2001068548A (ja) * 1999-08-31 2001-03-16 Fujitsu Ltd 半導体装置及びその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69531571T2 (de) * 1994-05-27 2004-04-08 Texas Instruments Inc., Dallas Verbesserungen in Bezug auf Halbleitervorrichtungen
US5760480A (en) * 1995-09-20 1998-06-02 Advanced Micro Devics, Inc. Low RC interconnection
KR0179792B1 (ko) * 1995-12-27 1999-04-15 문정환 고밀도 플라즈마 식각장비를 이용한 슬로프 콘택 홀 형성방법
JP2910713B2 (ja) * 1996-12-25 1999-06-23 日本電気株式会社 半導体装置の製造方法
US6306754B1 (en) * 1999-06-29 2001-10-23 Micron Technology, Inc. Method for forming wiring with extremely low parasitic capacitance
KR100382738B1 (ko) * 2001-04-09 2003-05-09 삼성전자주식회사 반도체 소자의 메탈 컨택 형성 방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4319070A1 (de) * 1992-06-24 1994-01-05 Mitsubishi Electric Corp Halbleitervorrichtung und Herstellungsverfahren dafür
US5747880A (en) * 1994-05-20 1998-05-05 Texas Instruments Incorporated Interconnect structure with an integrated low density dielectric
EP0687004A1 (de) * 1994-06-07 1995-12-13 Texas Instruments Incorporated Verfahren zur Herstellung von Dielektrica auf Halbleiterbauelemente
EP0759635A2 (de) * 1995-08-23 1997-02-26 International Business Machines Corporation Planare Endpassivierung für Halbleiterbauelemente
US6066577A (en) * 1996-11-08 2000-05-23 International Business Machines Corporation Method for providing fluorine barrier layer between conductor and insulator for degradation prevention
JPH11163523A (ja) * 1997-11-06 1999-06-18 United Microelectron Corp ランドレスバイアホールとガス誘電体を備えた多層間接続構造の形成方法
JPH11354638A (ja) * 1998-06-12 1999-12-24 Fujitsu Ltd 配線形成方法及び配線構造
JP2001068548A (ja) * 1999-08-31 2001-03-16 Fujitsu Ltd 半導体装置及びその製造方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 11 30 September 1999 (1999-09-30) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 03 30 March 2000 (2000-03-30) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 20 10 July 2001 (2001-07-10) *

Also Published As

Publication number Publication date
KR20030059279A (ko) 2003-07-07
DE10059935A1 (de) 2002-06-06
US20040029374A1 (en) 2004-02-12
US6864170B2 (en) 2005-03-08
JP2004515079A (ja) 2004-05-20
KR100533401B1 (ko) 2005-12-02
WO2002045165A2 (de) 2002-06-06
EP1340260A2 (de) 2003-09-03

Similar Documents

Publication Publication Date Title
WO2000041459A3 (de) Halbleiterbauelement mit einer wolframoxidschicht und verfahren zu dessen herstellung
EP2267760A3 (de) Mehrlagiges Dielektrikum auf Siliziumkarbid-Halbleiterstrukturen
WO2002017387A3 (en) Conductive material patterning methods
TW200505033A (en) Capacitor and method of fabricating the same
WO2003009380A3 (en) Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates
WO2003052794A3 (en) Process for formation of a wiring network using a porous interlevel dielectric and related structures
WO2002009178A3 (en) Semiconductor device and a process for forming the same
WO2003019649A8 (de) Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnung
WO1995027313A1 (en) Method of manufacturing an antifuse with silicon spacers and resulting antifuse
WO2003001594A3 (de) Hochspannungsmodul und verfahren zu dessen herstellung
EP0572214A3 (de) Herstellungsverfahren einer Verbindungsstruktur in einer integrierten Schaltung
WO2007126488A3 (en) Method for fabricating a semiconductor component including a high capacitance per unit area capacitor
AU6079799A (en) Transponder module and a method for producing the same
WO2002029865A3 (en) Method of manufacturing a semiconductor component and semiconductor component thereof
EP1248297A3 (de) Induktives Element und Halbleiterbauelement
TW200518265A (en) Copper damascene structure and semiconductor device including the structure and method of fabricating the same
TWI255935B (en) Method to manufacture address line of flat-panel display having repairing layer, and structure thereof
EP1408724A4 (de) Schaltungsausgebildetes substrat und verfahren zur herstellung des schaltungsausgebildeten substrats
WO2002045165A3 (de) Dicht gepackte halbleiterstruktur und verfahren zum herstellen einer solchen
WO2002047148A3 (en) Electrically isolated via in a multilayer ceramic package
TW346666B (en) Process for producing dielectric layer in an integrated circuit
WO2000008686A3 (de) Substrat für hochspannungsmodule
TW347587B (en) Antifuse structure and process for producing the same
WO2002037576A3 (de) Halbleitereinrichtung und verfahren zu deren herstellung
EP0905778A3 (de) Verbesserte Mehrlagenleitungsstruktur und Verfahren dafür

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2001999003

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2002547229

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 1020037007108

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1020037007108

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2001999003

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 10432770

Country of ref document: US

WWG Wipo information: grant in national office

Ref document number: 1020037007108

Country of ref document: KR