WO2002041673A2 - Adding electrical resistance in series with bypass capacitors to achieve a desired value of electrical impedance between conductors of an electrical power distribution structure - Google Patents

Adding electrical resistance in series with bypass capacitors to achieve a desired value of electrical impedance between conductors of an electrical power distribution structure Download PDF

Info

Publication number
WO2002041673A2
WO2002041673A2 PCT/US2001/043553 US0143553W WO0241673A2 WO 2002041673 A2 WO2002041673 A2 WO 2002041673A2 US 0143553 W US0143553 W US 0143553W WO 0241673 A2 WO0241673 A2 WO 0241673A2
Authority
WO
WIPO (PCT)
Prior art keywords
electrical
capacitors
resistance
capacitor
discrete
Prior art date
Application number
PCT/US2001/043553
Other languages
English (en)
French (fr)
Other versions
WO2002041673A3 (en
Inventor
Istvan Novak
Valerie A. St. Cyr
Merle Tetreault
Daniel C. Irish
Original Assignee
Sun Microsystems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems, Inc. filed Critical Sun Microsystems, Inc.
Priority to AU2002225683A priority Critical patent/AU2002225683A1/en
Publication of WO2002041673A2 publication Critical patent/WO2002041673A2/en
Publication of WO2002041673A3 publication Critical patent/WO2002041673A3/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0234—Resistors or by disposing resistive or lossy substances in or near power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10022—Non-printed resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10446—Mounted on an edge
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/1053—Mounted components directly electrically connected to each other, i.e. not via the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates to electronic systems, and more particularly to electrical interconnecting apparatus forming electrical power distribution structures.
  • a power distribution network of a typical printed circuit board includes several capacitors coupled between conductors used to convey direct current (d.c.) electrical power voltages and ground conductors.
  • the power distribution network of a digital PCB typically includes a bulk decoupling or "power entry" capacitor located at a point where electrical power enters the PCB from an external power supply.
  • the power distribution network also typically includes a decoupling capacitor positioned near each of several digital switching circuits (e.g., digital integrated circuits coupled to the PCB).
  • the digital switching circuits dissipate electrical power during switching times (e.g., clock pulse transitions).
  • Each decoupling capacitor typically has a capacitance sufficient to supply electrical current to the corresponding switching circuit during switching times such that the d.c.
  • the power entry capacitor may, for example, have a capacitance greater than or equal to the sum of the capacitances of the decoupling capacitors.
  • decoupling capacitors also provide low impedance paths to the ground electrical potential for alternating current (a.c.) voltages. Decoupling capacitors thus shunt or "bypass" unwanted a.c. voltages present on d.c. power trace conductors to the ground electrical potential. For this reason, the terms "decoupling capacitor” and "bypass capacitor” are often used synonymously.
  • bypass capacitor is used to describe any capacitor coupled between a d.c. voltage conductor and a ground conductor, thus providing a low impedance path to the ground electrical potential for a.c. voltages.
  • a typical bypass capacitor is a two ⁇ e ⁇ ninal electrical component.
  • Fig. 1 is a diagram of an electrical model 10 of a capacitor (e.g., a bypass capacitor) valid over a range of frequencies mcluding a resonant frequency f res of the capacitor.
  • Electrical model 10 includes an ideal capacitor, an ideal resistor, and an ideal inductor in series between the two te ⁇ ninals of the capacitor.
  • the ideal capacitor has a value C equal to a capacitance of the capacitor.
  • the ideal resistor has a value equal to an equivalent series resistance (ESR) of the capacitor
  • the ideal inductor has a value equal to an equivalent series inductance (ESL) of the capacitor.
  • ESR equivalent series resistance
  • ESL equivalent series inductance
  • C capacitance
  • ESL tire inductance
  • Fig. 2 is a graph of the logarithm of the magnitude of the electrical impedance (Z) between the terminals of electrical model 10 versus the logarithm of frequency/.
  • Z the electrical impedance
  • the impedance of electrical model 10 is dominated by the capacitance, and the magnitude of Z decreases with increasing frequency/
  • the magnitude of Z is a minimum and equal to the ESR of the capacitor.
  • the impedance of electrical model 10 is dominated by the resistance, and the magnitude of Z is substantially equal to the ESR of the capacitor.
  • the impedance of electrical model 10 is dominated by the inductance, and the magnitude of Z increases with increasing frequency/
  • a desired electrical impedance between a d.c. voltage conductor and a ground conductor is less than the ESR of a single capacitor, it is common to couple more than one of the capacitors in parallel between the d.c. voltage conductor and the ground conductor. In this situation, all of the capacitors have substantially the same resonant frequency f res , and the desired electrical impedance is achieved over a range of frequencies including the resonant frequency f res .
  • a digital signal alternating between high and low voltage levels includes contributions from a fundamental sinusoidal frequency (i.e., a first harmonic) and integer multiples of the first harmonic.
  • the frequency content of a digital signal extends to a frequency equal to the reciprocal of ⁇ times the transition time (i.e., rise or fall time) of the signal.
  • a digital signal with a 1 nanosecond transition time has a frequency content extending up to about 318 MHz.
  • All conductors have a certain amount of electrical inductance.
  • the voltage across the inductance of a conductor is directly proportional to the rate of change of current through the conductor.
  • a significant voltage drop occurs across a conductor having even a small inductance.
  • Transient switching currents flowing through electrical impedances of d.c. power conductors cause power supply voltage perturbations (e.g., power supply "droop" and ground “bounce”).
  • power supply voltage perturbations e.g., power supply "droop" and ground “bounce”
  • continuous power supply planes e.g., power planes and ground planes
  • the parallel power and ground planes are commonly placed in close proximity to one another in order to further reduce the inductances of the planes.
  • the magnitude of electrical impedance between two parallel conductive planes may vary widely wifr ⁇ n the frequency ranges of electronic systems with digital signals having short transition times.
  • the parallel conductive planes may exhibit multiple electrical resonances, resulting in alternating high and low impedance values.
  • High impedance values between power and ground planes are undesirable as transient switching currents flowing through the high electrical impedances cause relatively large power supply voltage perturbations. It would thus be desirable to have a bypass capacitor method for achieving a desired value of electrical impedance between parallel conductive planes of an electrical power distribution structure, wherein variations in the electrical impedance are relatively small over a wide range of frequencies.
  • the desired method would provide for optional suppression of the electrical resonances of the planes in addition to achieving the desired value of electrical impedance over a wide range of frequencies. Magnitudes of power supply voltage perturbations resulting from transient switching currents would be significantly reduced in electrical power distribution structures resulting from applications of the above methods.
  • An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n ⁇ 2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors.
  • the n capacitors have substantially the same capacitance C, mounted resistance R m , mounted inductance L m , and mounted resonant frequency f m . res .
  • the mounted resistance R m of each of the n capacitors includes an electrical resistance of the corresponding electrical resistance element.
  • the electrical power distribution structure achieves an electrical impedance Z at the resonant frequency f m , res of the capacitors.
  • the mounted resistance R m of each of the n capacitors is substantially equal to (n ⁇ Z).
  • the mounted inductance L m of each of the n capacitors is less than or equal to (0.2 • n ⁇ ⁇ o ⁇ h), where ⁇ o is the permeability of free space, and h is a distance between the planar conductors. It is noted that dielectric materials used to form dielectric layers are typically non-magnetic, and thus the relative permeability ⁇ . of the dielectric layer is assumed to be unity.
  • the mounted resistance R m of each of the n capacitors may be, for example, the sum of an equivalent series resistance (ESR) of the capacitor, the electrical resistance of the corresponding electrical resistance element, and the electrical resistances of all conductors coupling the capacitor between the planar conductors.
  • ESR equivalent series resistance
  • each of the n capacitors may be the electrical inductance resulting from the coupling of the capacitor between the planar conductors.
  • each of the n capacitors may have a body.
  • the mounted resistance R m of each of the n capacitors may be the sum of the ESR of the capacitor body, the electrical resistance of the corresponding electrical resistance element, and the electrical resistances of all conductors (e.g., solder lands and vias) coupling the capacitor body between the planar conductors.
  • the mounted inductance L, statement of each of the n capacitors may be the electrical inductance resulting from the coupling of the capacitor body between the planar conductors.
  • the mounted resonant frequency f m . res resulting from capacitance C and mounted inductance L, finish may be given by:
  • the n discrete capacitors may or may not be used to suppress electrical resonances between tire planar conductors. Where the n discrete capacitors are not used to suppress the electrical resonances, the n discrete capacitors may be located upon, and distributed about, one or more surfaces of the planar conductors. On the other hand, when the n discrete capacitors are used to suppress the electrical resonances, the n discrete capacitors may be positioned along at least a portion of corresponding outer edges of the planar conductors. In this situation, adjacent capacitors may be separated by substantially equal spacing distances.
  • an electrical power distribution structure including an electrical resistance element coupled in series with a capacitor between a pair of parallel conductive planes separated by a dielectric layer (e.g., between a power plane and a ground plane).
  • the electrical resistance elements are incorporated in ways which do not appreciably increase physical dimensions of current loops coupling the capacitor between the pair of parallel conductive planes.
  • the mounted inductance L m of the capacitor is not changed substantially over a corresponding conventional structure.
  • a first method for achieving a target electrical impedance Z t in an electrical power distribution structure including a pair of parallel planar conductors separated by a dielectric layer may be useful where bypass capacitors will not be used to suppress plane resonances.
  • the bypass capacitors may be distributed about a surface of at least one of the planar conductors.
  • the first method includes deterrnining a required number n of a selected type of discrete electrical capacitor dependent upon an inductance of the electrical power distribution structure L p and a mounted inductance L m of a representative one of the selected type of discrete electrical capacitor when electrically coupled between the planar conductors, wherein n ⁇ 2.
  • the required number n of the selected type of capacitor may be determined using:
  • the target electrical impedance Z t is used to determine a required value of mounted resistance R m . reg fo ⁇ the n discrete electrical capacitors.
  • the required value of mounted resistance R, originate. reg may be determined using:
  • the required number n of the selected type of discrete electrical capacitor may be selected such that each of the n capacitors has an equivalent series resistance (ESR) which is less than the required value of mounted resistance R, whil. req .
  • ESR equivalent series resistance
  • the mounted resistance R, strig of a representative one of the n capacitors may be deteimined when the representative capacitor is coupled between the pair of parallel planar conductors and when the electrical resistance of a corresponding electrical resistance element is zero.
  • the electrical resistance of each of n electrical resistance elements may be determined by subtracting the mounted resistance R m of the representative capacitor from the required value of mounted resistance R m . reg .
  • the n discrete electrical capacitors and the n electrical resistance elements may be electrically coupled between the planar conductors such that each of the n discrete electrical capacitors is coupled in series with a corresponding one of the n electrical resistance elements.
  • the first method may also include determining a separation distance h between the parallel planar conductors required to achieve the target electrical impedance Z,.
  • the separation distance h may be determined using:
  • a thickness t for the dielectric layer may be selected such that the thickness t is less than or equal to the required separation distance h. Thickness t may be used to deterrnine the inductance of the electrical power distribution structure L p .
  • the inductance of the electrical power distribution structure L p may be determined using:
  • the type of discrete electrical capacitor may be selected, wherein capacitors of the selected type have at least one substantially identical physical dimension (e.g., a length of the capacitor package between terminals) upon which the mounted inductance of the capacitors is dependent.
  • the physical dimension may be used to deterrnine the mounted inductance L m of the representative capacitor.
  • a second method for achieving a target electrical impedance Z, in an electrical power distribution structure hicluding a pair of parallel planar conductors separated by a dielectric layer may be useful where the bypass capacitors will be used to suppress plane resonances. In this situation, at least a portion of the bypass capacitors will be electrically coupled between the planar conductors along an outer edge of the planar conductors.
  • the second method includes deterrrrining a first required number ⁇ i ⁇ of discrete electrical capacitors dependent upon an inductance of the electrical power distribution structure L p and a mounted inductance L m of each of the discrete electrical capacitors when electrically coupled between the planar conductors, where iii ⁇ l.
  • the first required number n ⁇ of the discrete electrical capacitors may be determined using:
  • a second required number n 2 of the discrete electrical capacitors is determined dependent upon a distance d p around an outer perimeter of the electrical power distribution structure (i.e., the parallel planar conductors) and a spacing distance S between adjacent discrete electrical capacitors, where n 2 ⁇ 2.
  • the second required number ⁇ 2 of the discrete electrical capacitors may be dete ⁇ nined using:
  • Spacing distance S may be less than or equal to a maximum spacing distance S max between adjacent electrical capacitors.
  • the electrical power distribution structure may be, for example, part of an electrical interconnecting apparatus, and electrical signals may be conveyed within the electrical interconnecting apparatus.
  • the electrical signals may have an associated frequency range, and maximum spacing distance S ma may be a fraction of a wavelength of a maximum frequency f max of the frequency range of the electrical signals.
  • Maximum spacing distance S max may be given by:
  • n 2 » ⁇ the following steps may be performed.
  • a required value of mounted resistance R m ., m may be determined for n 2 of the discrete electrical capacitors dependent upon the target electrical impedance Z,. The required value of mounted resistance R m .
  • re g for the n 2 capacitors may be detemiined using:
  • the number n 2 of the discrete electrical capacitors may be selected wherein each of the n 2 capacitors has an equivalent series resistance (ESR) which is less than the required value of mounted resistance R m . reg .
  • the mounted resistance R m of a representative one of the 7z 2 capacitors may be determined when the representative capacitor is coupled between the pair of parallel planar conductors and when the electrical resistance of a corresponding electrical resistance element is zero.
  • the electrical resistance of each of n 2 electrical resistance elements may be determined by subtracting the mounted resistance R m of the representative capacitor from the required value of mounted resistance R m . reg .
  • the n 2 discrete electrical capacitors and the n 2 electrical resistance elements maybe electrically coupled between the planar conductors along the outer perimeter of the parallel planar conductors such that each of the n 2 discrete electrical capacitors is coupled in series with a corresponding one of the n 2 electrical resistance elements.
  • the second method may also include the detei-mining of a separation distance h between the parallel planar conductors required to achieve the target electrical impedance Z t as described above.
  • a thickness t for the dielectric layer may be selected such that the thickness t is less than or equal to the required separation distance h. Thickness t maybe used to determine the inductance of the electrical power distribution structure L p as described above.
  • the type of discrete electrical capacitor may be selected, wherein capacitors of the selected type have at least one substantially identical physical dimension (e.g., a length of the capacitor package between te ⁇ riinals) upon which the mounted inductance of the capacitors is dependent.
  • the physical dimension may be used to determine the mounted inductance L m of the representative capacitor.
  • the target electrical impedance Z may be used to deterrnine a required value of mounted resistance R m . req for ti ⁇ of the discrete electrical capacitors.
  • the required value of mounted resistance R m . reg for the ri ⁇ capacitors may be dete ⁇ nined using:
  • the number . ⁇ of the discrete electrical capacitors may be selected, wherein each of the ?z ⁇ capacitors has an equivalent series resistance (ESR) which is less than the required value of mounted resistance R m . req .
  • the mounted resistance R m of a representative one of the n ⁇ capacitors may be determined when the representative capacitor is coupled between the pair of parallel planar conductors and when the electrical resistance of a corresponding electrical resistance element is zero.
  • the electrical resistance of each of 72 1 electrical resistance elements may be detemiined by subtracting the mounted resistance R m of the representative capacitor from the required value of mounted resistance Renfin,. req .
  • the discrete electrical capacitors and the 7. 1 electrical resistance elements maybe electrically coupled between the planar conductors such that: (i) each of the 7.
  • the electrical power distribution structure may have, for example, four sides arranged as two pairs of opposite sides. The sides forming one of the pairs of opposite sides may have equal lengths x, and the other two opposite sides may have equal lengths y. In this situation, the distance d p around the outer perimeter of the electrical power distribution structure is equal to 2 • (x + v).
  • Fig. 1 is a diagram of an electrical model of a capacitor (e.g., a bypass capacitor) valid over a range of frequencies including a resonant frequency/,,, of the capacitor, wherein the electrical model includes an ideal capacitor, an ideal resistor, and an ideal inductor in series between two terminals of the capacitor, and wherein the ideal capacitor has a value C equal to a capacitance of the capacitor, and wherein the ideal resistor has a value equal to an equivalent series resistance (ESR) of the capacitor, and wherein the ideal inductor has a value equal to an equivalent series inductance (ESL) of the capacitor;
  • ESR equivalent series resistance
  • ESL equivalent series inductance
  • Fig. 2 is a graph of the logarithm of the magnitude of the electrical impedance (Z) between the te ⁇ rrinals of the electrical model of Fig. 1 versus the logarithm of frequency/
  • Fig. 3 is a perspective view of a structure including a pair of 10 in. x 10 in. square conductive planes separated by a dielectric layer having a dimension or height h between the conductive planes;
  • Fig. 4 is a graph of the simulated magnitude of electrical impedance (Z) of the structure of Fig. 3 between the pair of rectangular conductive planes versus frequency;
  • Fig. 5 is a top plan view of a model used to model the structure of Fig. 3, wherein the model is a two- dimensional network of multiple lossy transmission line segments;
  • Fig. 6 is a top plan view of the structure of Fig. 3 illustrating the positions of multiple dissipative edge termination (DET) networks used to reduce or completely eliminate electrical resonances in the structure at relatively high frequencies due to open boundaries, wherein the DET networks are coupled between the planes about outer edges of the structure, and wherein each DET network includes a 1 nF capacitor in series with a 1.06 ohm resistor;
  • DET dissipative edge termination
  • Fig. 7 is a top plan view of the structure of Fig. 3 illustrating the positions of multiple capacitors coupled between the planes about outer edges of the structure as part of a distributed matched bypassing system, wherein all of the capacitors have substantially identical electrical characteristics, and wherein adjacent capacitors are separated by substantially equal spacing distances;
  • Fig. 8 is a graph of the simulated magnitude of the electrical impedance (Z) of the composite structure of Figs. 3, 6, and 7 (i.e., the structure of Fig. 3 with the DET networks of Fig. 6 and the capacitors of Fig. 7) versus frequency for several different ESL values of the capacitors of Fig. 7, wherein the capacitors of Fig. 7 have a capacitance C of 10 ⁇ F and an ESR of 0.106 ohms;
  • Fig. 9 is a graph of the simulated magnitude of the electrical impedance (Z) of the composite structure of Figs. 3, 6, and 7 (i.e., the structure of Fig. 3 with the DET networks of Fig. 6 and the capacitors of Fig. 7) versus frequency for several different ESL values of the capacitors of Fig. 7, wherein the capacitors of Fig. 7 have a capacitance C of 10 ⁇ F and an ESR of 0.0106 ohms;
  • Fig. 10 is a graph of the simulated magnitude of the electrical impedance (Z) of the composite structure of Figs. 3, 6, and 7 (i.e., the structure of Fig. 3 with the DET networks of Fig. 6 and the capacitors of Fig.
  • Fig. 11 is a cross sectional view of a portion of an electrical power distribution structure wherein a capacitor (e.g., a multilayer ceramic capacitor) is electrically coupled between a planar power conductor (i.e., a power plane) and a planar ground conductor (i.e., a ground plane) of an interconnecting apparatus, wherein terminals of the capacitor are coupled to solder lands formed within a signal plane of the interconnecting apparatus, and wherein the signal plane is adjacent to the ground plane, and wherein the solder lands are coupled to the power plane and the ground plane by vias;
  • a capacitor e.g., a multilayer ceramic capacitor
  • Fig, 12 is an electrical model used to estimate an electrical inductance L c of the capacitor of Fig. 11, wherein the electrical inductance Lc is the inductance between the signal plane and the ground plane between the vias due to a length of the capacitor body or package;
  • Fig. 13 is a diagram of an electrical model of a bypass capacitor coupled between parallel power planes, wherein the electrical model includes an ideal capacitor, an ideal resistor, and an ideal inductor in series between two terminals of the bypass capacitor, and wherein the ideal capacitor has a value C equal to a capacitance of the bypass capacitor, and wherein the ideal resistor has a value equal to a mounted resistance R m of the bypass capacitor, and wherein the ideal inductor has a value equal to a mounted inductance L m of the bypass capacitor;
  • Fig. 14 is a graph of the logarithm of the magnitude of the electrical impedance (2) between the terminals of the electrical model of Fig. 13 versus the logarithm of frequency/;
  • Fig. 15 is a top plan view of an exemplary electrical interconnecting apparatus including a pair of parallel planar conductors, wherein multiple discrete bypass capacitors are located upon, and distributed about, an upper surface of the interconnecting apparatus, and wherein each of the bypass capacitors is coupled between the planar conductors;
  • Fig. 16 is. a top plan view of the interconnecting apparatus of Fig. 15, wherein the multiple discrete bypass capacitors are electrically coupled between the planar conductors along corresponding outer edges of the planar conductors, and wherein adjacent bypass capacitors are separated by a spacing distance S;
  • Fig. 17 is a cross sectional view of a portion of one embodiment of an electrical interconnecting apparatus including a power distribution structure having two different pairs of conductive power planes, wherein the intercorr ⁇ ectfng apparatus includes two signal planes between the pairs of power planes;
  • Fig. 18 is a cross sectional view of a portion of one embodiment of an electrical interconnecting apparatus including a power distribution structure having three different pairs of conductive power planes, wherein the interconnecting apparatus includes two signal planes between a first and a second of the three pairs of power planes, and two more signal planes between the second and the third of the three pairs of power planes;
  • Fig. 19 is a perspective view of a portion of an electrical power distribution structure including a capacitor
  • an interdigitated capacitor mounted upon an upper surface of an interconnecting apparatus and electrically coupled between an electrical power (i.e., power) conductor layer and an electrical ground (i.e., ground) conductor layer of the interconnecting apparatus;
  • Fig. 20 is a top plan view of one embodiment of the power conductor layer of Fig. 19 following a process (e.g., an etch process) during which a portion of an electrically conductive material (e.g., a metal) fo ⁇ ning the power conductor layer is removed from an isolation region, thereby forming an island electrically isolated from a remainder of the power conductor layer;
  • a process e.g., an etch process
  • Fig. 21 is a top plan view of the embodiment of the power conductor layer of Fig. 20 following a process during which two resistive stripes are formed between the island and the remainder of the power conductor layer on opposite sides of the island, wherein the capacitor of Fig. 19 and an electrical resistance offered by the two resistive stripes of Fig. 21 are coupled in series between the power conductor layer and the ground conductor layer of the intercomiecting apparatus of Fig. 19;
  • Fig. 22 is a cross sectional view of a portion of an electrical power distribution structure wherein vias with relatively high electrical resistances are used to electrically couple a capacitor (e.g., a multilayer ceramic capacitor) between a planar power conductor (i.e., a power plane) and a planar ground conductor (i.e., a ground plane) of an interconnecting apparatus;
  • a capacitor e.g., a multilayer ceramic capacitor
  • Fig. 23 is a cross sectional view of a portion of an electrical power distribution structure wherein an electrically resistive adhesive material is used to electrically couple a capacitor between a power plane and a ground plane of an interconnecting apparatus
  • Fig. 24 is a cross sectional view of a portion of an electrical power distribution structure wherein a resistive coupon is positioned between a capacitor and an interconnecting apparatus, and wherein an electrical resistance offered by the resistive coupon is electrically coupled in series with the capacitor between a power plane and a ground plane of the interconnecting apparatus;
  • Fig. 25 A is a cross sectional view of a portion of an electrical power distribution structure wherein a capacitor is electrically coupled between a power plane and a ground plane of an interconnecting apparatus, and wherein the capacitor includes a single electrical resistance element in series with a capacitance element;
  • Fig. 25B is a cross sectional view of the portion of the electrical power distribution structure of Fig. 25A wherein the capacitor includes two separate electrical resistance elements on either side of, and in series with, the capacitance element;
  • Fig. 25C is a cross sectional view of the portion of the electrical power distribution structure of Fig. 25A wherein the capacitor includes a horizontal resistive layer electrically coupled in series with the capacitance element;
  • Figs. 26A-26C in combination form a flow chart of one embodiment of a first method for achieving a target electrical impedance Z t in an electrical power distribution structure including a pair of parallel planar conductors separated by a dielectric layer; and Figs. 27A-27F in combination form a flow chart of one embodiment of a second method for achieving a target electrical impedance Z, in an electrical power distribution structure including a pair of parallel planar conductors separated by a dielectric layer.
  • Fig. 3 is a perspective view of a structure 20 including a pair of 10 in. x 10 in. square conductive planes 22 separated by a fiberglass-epoxy composite dielectric layer 24 having a height h.
  • Each conductive plane 22 is made of copper and is about 0.0014 in. thick.
  • Dielectric layer 24 is made of FR4 dielectric material having a dielectric constant of about 4.0, and height h is approximately 0.002 in.
  • Fig. 4 is a graph of the simulated magnitude of electrical impedance (Z) of structure 20 of Fig. 3 between the pair of rectangular conductive planes 22 versus frequency.
  • the graph was created by modeling each half-inch square of the pair of conductive planes 22 as a matrix of transmission lines.
  • the impedance value was computed by simulating the application of a 1 ampere constant current between the centers of planes 22, varying the frequency of the current, and detern ⁇ ing the magnitude of the steady state voltage between the centers of planes 22.
  • Conductive planes 22 of Fig. 3 varies widely at frequencies above about 500 MHz
  • Conductive planes 22 exhibit multiple electrical resonances at frequencies between about 150 MHz and 1 GHz, resulting in alternating high and low impedance values.
  • Conductive planes 22 would be poor candidates for power and ground planes of an electrical interconnecting apparatus (e.g., a PCB) conveying signals having significant frequency content above 500 MHz as the high impedance values of conductive planes 22 at frequencies above 500 MHz would cause relatively large power supply voltage perturbations.
  • an electrical interconnecting apparatus e.g., a PCB
  • Fig. 5 is a top plan view of a model 30 used to model structure 20 of Fig. 3.
  • Model 30 is a two- dimensional network of multiple lossy transmission line segments 32 interconnected to form a 0.5 in. grid pattern. Lossy transmission line segments 32 account for resistive and skin losses in conductors and dielectric losses in dielectric layer 24.
  • Fig. 6 is a top plan view of structure 20 of Fig. 3 illustrating the positions of multiple dissipative edge termination (DET) networks 40 coupled between planes 22 about outer edges of structure 20.
  • Each DET network 40 includes a 1 nF capacitor in series with a 1.06 ohm resistor. Adjacent DET networks 40 are separated by spacing distances of approximately 0.5 in. about outer edges of structure 20. It is noted that DET networks 40 are used only to reduce or completely eliminate electrical resonances in structure 20 at relatively high frequencies due to open boundaries, and are not considered part of a distributed matched bypassing system and method described herein.
  • Fig. 7 is a top plan view of structure 20 of Fig. 3 illustrating the positions of multiple capacitors 50 coupled between planes 22 about outer edges of structure 20 as part of a distributed matched bypassing system. All capacitors 50 have substantially the same values of capacitance, ESR, and ESL. Adjacent capacitors 50 are separated by spacing distances of approximately 5.0 in. about outer edges of structure 20 as indicated in Fig. 7.
  • Fig. 8 is a graph of the simulated magnitude of the electrical impedance (Z) of the composite structure 20 of Figs. 3, 6, and 7 (structure 20 of Fig. 3 with DET networks 40 of Fig. 6 and capacitors 50 of Fig. 7) versus frequency for capacitors 50 having several different values of ESL, wherein the capacitance C of all capacitors 50 is 10 ⁇ F, and wherein the ESR values of all capacitors 50 is 0.106 ohms.
  • the impedance values were computed by simulating the application of a 1 ampere constant current between the centers of planes 22, varying the frequency of the current, and determining the magnitude of the steady state voltage between the centers of planes 22.
  • the graph of Fig. 8 shows that for the 8 capacitors 50 having ESL values of 30 pH and 100 pH, the magnitude of Z is approximately equal to ESR/8 or 0.013 ohms over a relatively wide range of frequencies, and the impedance curves are relatively smooth in comparison to the other impedance curves.
  • the impedance curves for capacitors 50 having ESL values greater than 100 pH show increasing amounts of ripple.
  • Fig. 9 is a graph of the simulated magnitude of the electrical impedance (Z) of tire composite structure 20 of Figs. 3, 6, and 7 (structure 20 of Fig. 3 with DET networks 40 of Fig. 6 and capacitors 50 of Fig. 7) versus frequency for capacitors 50 having several different values of ESL, wherein the capacitance C of all capacitors 50 is 10 ⁇ F, and wherein the ESR values of all capacitors 50 is 0.0106 ohms.
  • the impedance values were computed by simulating the application of a 1 ampere constant current between the centers of planes 22, varying the frequency of the current, and detern-dning the magnitude of the steady state voltage between the centers of planes 22.
  • the graph of Fig. 9 shows that for capacitors 50 with relatively low ESR (i.e., high Q), there is significant ripple in the impedance curve for even the lowest ESL value of 30 pH.
  • the ripple increases the magnitude of Z above about 150 MHz.
  • Fig. 10 is a graph of the simulated magnitude of the electrical impedance (Z) of the composite structure 20 of Figs. 3, 6, and 7 (structure 20 of Fig. 3 with DET networks 40 of Fig. 6 and capacitors 50 of Fig. 7) versus frequency for capacitors 50 having several different values of ESR, wherein the capacitance C of all capacitors 50 is 10 ⁇ F, and wherein the ESL of all capacitors 50 is 100 pH.
  • the lx impedance curve was generated using an ESR value of lx a nominal ESR value of 0.106 ohms.
  • the impedance values were computed by simulating the application of a 1 ampere constant current between the centers of planes 22, varying the frequency of the current, and dete ⁇ rrining the magnitude of the steady state voltage between the centers of planes 22.
  • the graph of Fig. 10 shows that for capacitors 50 with ESR values below the lx (0.106 ohm) optimum, the magnitude of Z decreases with increasing frequency and reaches a minimum at series resonant frequencies around 2 MHz. In addition, a peak develops at about 100 MHz at a higher than optimum magnitude of Z.
  • the optimum, the smoothest impedance curve, is achieved when the parallel resultant of the ESR values of all 8 capacitors 50 (ESR/8) equals the characteristic impedance of structure 20.
  • each capacitor 50 coupled between parallel planar conductors 22 was assumed to have an equivalent series resistance ESR and an equivalent series inductance ESL in series with a capacitance.
  • the ESR value used in the simulation represents a mounted resistance R, although of the capacitors including, in addition to the ESR, the electrical resistances of all conductors used to couple the capacitors to the power planes of the PCB.
  • the ESL value used in the simulation represents a mounted inductance L m resulting from the coupling of the capacitor structures between the parallel power planes of the PCB. It is noted that for reasons described below, the mounted inductance Long, of a multiplayer ceramic capacitor may actually be less than the ESL of the capacitor measured in isolation and reported by the manufacturer.
  • Fig. 11 is a cross sectional view of a portion 60 of an electrical power distribution structure wherein a capacitor 62 (e.g., a multilayer ceramic capacitor) is electrically coupled between a planar power conductor (i.e., a power plane) 64 and a planar ground conductor (i.e., a ground plane) 66 of an interconnecting apparatus 63.
  • Capacitor 62 may be, for example, a bypass capacitor.
  • Interconnecting apparatus 63 may be, for example, a PCB, a component of a semiconductor device package, or formed upon a surface of an integrated circuit substrate.
  • Interconnecting apparatus 63 includes multiple layers of planar electrical conductors separated by dielectric layers.
  • capacitor 62 has two terminals 70 and 72 on opposite ends of a body or package.
  • Terminal 70 is electrically connected to a first solder land 74 by a solder fillet 76.
  • Solder land 74 is electrically coupled to ground plane 66 by a via 78.
  • Terminal 72 is electrically connected to a second solder land 80 by a solder fillet 82.
  • Solder land 80 is electrically coupled to power plane 64 by a via 84.
  • Solder lands 74 and 80 are formed within a signal plane 68 of interconnecting apparatus 63.
  • Signal plane 68 includes multiple signal lines (i.e., interconnects or traces) used to convey signals witrrin interconnecting apparatus 63.
  • power plane 64 is connected to a power terminal of an electrical power supply at a power entry point of interconnecting apparatus 63, and ground plane 66 is connected to a ground terminal of the power supply at the power entry point.
  • Power plane 64 and ground plane 66 provide electrical power to electronic devices connected between power plane 64 and ground plane 66.
  • L m LLANDI + Lyi i + L + LyiA2 + L-LAND2
  • L LAND] is the inductance of solder land 74
  • L vw is the inductance of via 78
  • L c is the inductance of the combination of signal plane 68 and ground plane 66 between via 78 and via 84 due to a length of the capacitor 62 package
  • L VJAI is the inductance of via 84
  • LI N D I is t e inductance of solder land 80.
  • Mounted resistance R m of capacitor 62 is given by:
  • R m ESR + RiANDl + R-vw + Re + RviA2 + RLAND2
  • ESR is the equivalent series resistance of capacitor 62
  • RLANDI is the resistance of solder land 74
  • R mj is the resistance of via 78
  • R c is the resistance power plane 64 between via 78 and via 84 due to the length of the capacitor 62 package
  • Ryi A 2 is the resistance of via 84
  • RLA N D 2 is the resistance of solder land 80.
  • Fig, 12 is an electrical model 90 used to estimate electrical inductance Lc, the inductance of the combination of signal plane 68 and ground plane 66 between via 78 and via 84 due to a length of the capacitor 62 package.
  • Lj represents the self inductance of signal plane 68 between via 78 and via 84
  • L 2 represents the self inductance of ground plane 66 between via 78 and via 84.
  • Signal plane 68 and ground plane 66 in close proximity to one another, are magnetically coupled to one another, producing a mutual inductance M, where Mis given by:
  • M k ⁇ L x L 2 and k is the coefficient of magnetic coupling between signal plane 68 and ground plane 66.
  • L c 2L(l - k) where k is the coefficient of magnetic coupling between signal plane 68 and ground plane 66.
  • I c multilayer ceramic
  • Fig. 13 is a diagram of an electrical model 100 of a bypass capacitor coupled between parallel power planes. Electrical model 100 is valid over a range of frequencies including a resonant frequency f res of the bypass capacitor.
  • the electrical model includes an ideal capacitor, an ideal resistor, and an ideal inductor in series between two terniinals of the bypass capacitor.
  • the ideal capacitor has a value C equal to a capacitance of the bypass capacitor.
  • the ideal resistor has a value equal to a mounted resistance R réelle, of the bypass capacitor.
  • the mounted resistance R m of the bypass capacitor is the sum of the ESR of the bypass capacitor and the electrical resistances of all conductors coupling the bypass capacitor to the parallel power planes.
  • the ideal inductor of the electrical model has a value equal to a mounted inductance L m of the bypass capacitor.
  • the mounted inductance L m of the bypass capacitor is the electrical inductance resulting from the coupling of the bypass capacitor between the parallel power planes of the PCB.
  • the series combination of the capacitance C and the mounted inductance L m of the bypass capacitor results in series resonance and a mounted resonant frequency f m . res given by:
  • Fig. 14 is a graph of the logarithm of the magnitude of the electrical impedance (Z) between the te ⁇ riinals of electrical model 100 versus the logarithm of frequency/ .
  • Z the electrical impedance
  • the impedance of electrical model 100 is dominated by the capacitance, and the magnitude of Z decreases with increasing frequency/
  • the resonant frequency , /,-, ⁇ of the capacitor the magnitude of Zis a rrrierimum and equal to the mounted resistance R m of the capacitor.
  • the resonant frequency f m Within a range of frequencies centered about resonant frequency f m .
  • the impedance of electrical model 100 is dominated by the mounted resistance R m , and the magnitude of Zis substantially equal to the mounted resistance R legi, of the capacitor.
  • the impedance of electrical model 100 is dominated by the mounted inductance L m , and the magnitude of Z increases with increasing frequency/
  • bypass capacitor mounted resistance R m Bypass capacitor mounted resistance R m will first be considered.
  • the 8 capacitors 50 each having the same series resistance value and coupled between conductive planes 22 of structure 20 (Fig. 7), produced an impedance between conductive planes 22 having a magnitude approximately equal to the series resistance value of capacitors 50 divided by 8.
  • the impedance magnitude was substantially constant over a relatively wide range of frequencies, and the impedance curve was relatively smooth in comparison to tire other impedance curves.
  • a number of bypass capacitors n (ti ⁇ 2) should be selected having a mounted resistance R m such that:
  • ⁇ o is the permeability of free space. It is noted that this equation is still true when the conductive planes are separated by a dielectric layer as dielectric materials used to form dielectric layers are typically non-magnetic, and thus the relative permeability ⁇ . of such a dielectric layer is assumed to be unity.
  • Figs. 8 and 9 can be used to show that smooth impedance curves result when the equivalent inductance of 8 capacitors 50 coupled in parallel between conductive planes 22 (Intended,/8) is much less than the inductance L p of conductive planes 22.
  • the n bypass capacitors should be selected having a mounted inductance L m such that:
  • the required number of bypass capacitors n will now be considered.
  • the required number of bypass capacitors n may depend upon whether or not the bypass capacitors will be used to suppress plane resonances.
  • a first value for the required number of bypass capacitors n ⁇ may be calculated by: (i) deterrnining the mounted inductance L m of each of the bypass capacitors, and (ii) substituting the mounted inductance L m in the following equation:
  • n, .
  • bypass capacitors are not intended for suppression of plane resonances, the required number of bypass capacitors n is equal to the first value ⁇ i ⁇ .
  • the n bypass capacitors maybe dispersed across a surface of one or both of the planar conductors and electrically coupled between the planar conductors.
  • bypass capacitors will be used to suppress plane resonances, at least a portion of the bypass capacitors will be electrically coupled between the planar conductors along an outer edge of the planar conductors. In this situation, it is necessary to calculate a second value for the required number of bypass capacitors n 2 .
  • adjacent bypass capacitors coupled along an outer edge of the planar conductors should be separated by a spacing distance much less than a wavelength of a highest frequency of interest.
  • the planar conductors may be part of an electrical power distribution structure of an electrical interconnecting apparatus (e.g., a PCB). Electrical signals conveyed within the electrical interconnecting apparatus have an associated frequency range and a maximum frequency /, makeup of the frequency range. The wavelength of maximum frequency /, reinstate is the velocity divided by the frequency. If the dielectric layer between the planar conductors has a relative pennittivity of ⁇ r , the velocity is the speed of light c (about 3.0 10 m sec) divided by the square root of ⁇ r .
  • Adjacent bypass capacitors coupled along the outer edge of the planar conductors may be separated by a spacing distance less than or equal to a maximum spacing distance S max may be given by:
  • Fig. 15 is a top plan view of an exemplary electrical interconnectrng apparatus 110 including a pair of parallel planar conductors, wherein multiple discrete bypass capacitors 112 are located upon, and distributed about, a surface of the one of the planar conductors, and wherein each of the bypass capacitors 112 is electrically coupled between the planar conductors.
  • the arrangement of bypass capacitors 112 in Fig. 15 may be adopted when bypass capacitors 112 are not to be used to suppress resonances of the planar conductors. It is noted that the bypass capacitors 112 may be located upon, and distributed about, surfaces of both of the planar conductors.
  • Fig. 16 is a top plan view of the exemplary interconnecting apparatus 110 of Fig.
  • bypass capacitors 112 are electrically coupled between the planar conductors along corresponding outer edges of the planar conductors.
  • adjacent bypass capacitors are separated by a spacing distance S, where S ⁇ S max .
  • S spacing distance
  • the arrangement of bypass capacitors 112 in Fig. 16 may be adopted when bypass capacitors 112 are to be used to suppress resonances of the planar conductors. It is noted that the bypass capacitors 112 may be positioned along a portion of the corresponding outer edges of the planar conductors.
  • interconnecting apparatus 60 includes a planar power conductor (i.e., a power plane) 64 parallel to a planar ground conductor (i.e., a ground plane) 66.
  • Power plane 64 and ground plane 66 are separated by a dielectric layer having a vertical height h.
  • An empirical formula for the electrical impedance Zp between a stracture including a pair of parallel conductive planes separated by a dielectric layer is:
  • ⁇ r is the relative permittivity of the dielectric layer
  • d p is the distance around the outer edges (e.g., an outer perimeter) of the structure in inches.
  • h is an equivalent distance (e.g., a height) between a representative single pair of planes in mils.
  • FIG. 17 is a cross sectional view of a portion of one embodiment of an electrical interconnecting apparatus 120 including a power distribution structure having two different pairs of conductive power planes.
  • Interconnecting apparatus 120 includes a GROUNDl plane 122 and a POWERl plane 124 forming one of the pairs of conductive power planes, a SIGNAL1 plane 126, a SIGNAL2 plane 128, and a POWER2 plane 130 and a GROUND2 plane 132 forming the other pair of conductive power planes.
  • POWERl plane 124 and POWER2 plane 130 are coupled by a via 134
  • GROUNDl plane 122 and GROUND2 plane 132 are coupled by a via 136.
  • SIGNAL1 plane 126 and SIGNAL2 plane 128 are used to convey electrical signals within interconnecting apparatus 120.
  • GROUNDl plane 122 and POWERl plane 124 are separated by a height h and
  • POWER2 plane 130 and GROUND2 plane 132 are separated by a height h 2 .
  • Fig. 18 is a cross sectional view of a portion of one embodiment of an electrical interconnecting apparatus
  • Interconnecting apparatus 140 includes a GROUNDl plane 142 and a POWERl plane 144 forming a first of the three pairs of conductive power planes, a SIGNAL1 plane 146, a SIGNAL2 plane 148, a GROUND2 plane 150 and a POWER2 plane 152 foimrng a second of three pairs of conductive power planes, a SIGNAL3 plane 154, a SIGNAL4 plane 156, and a GROUND3 plane 158 and a POWER3 plane 160 forming the third pair of conductive power planes.
  • POWERl plane 144, POWER2 plane 152, and POWER3 plane 160 are coupled by a via 162
  • GROUNDl plane 142, GROUND2 plane 150, and GROUND3 plane 158 are coupled by a via 164.
  • SIGNALl plane 146, SIGNAL2 plane 148, SIGNAL3 plane 154, and SIGNAL4 plane 156 are used to convey electrical signals within interconnecting apparatus 140. As shown in Fig. 18, GROUND 1 plane 142 and POWERl plane 144 are separated by a height h 3 ,
  • POWER2 plane 152 and GROUND2 plane 150 are separated by a height h 4
  • POWERS plane 160 and GROUND3 plane 158 are separated by a height h 5 .
  • the smoothest impedance curve for a pair of parallel conductive planes separated by a dielectric layer is achieved when the parallel resultant of the ESR values of all n bypass capacitors (ESR/n) coupled between the pair of parallel conductive planes is equal to the characteristic impedance of the pair of parallel conductive planes.
  • a separation distance h between the parallel conductive planes may be determined in order to achieve a target electrical impedance Z,.
  • the target electrical impedance Z may then be used to determine a required value of mounted resistance R, rev.
  • n discrete electrical capacitors e.g., bypass capacitors
  • - ng n ' Z r
  • the n discrete electrical capacitors may be selected such that the n capacitors each have an equivalent series resistance (ESR) which is less than or equal to the required value of mounted resistance R, reconsider. req .
  • ESR equivalent series resistance
  • an electrical resistance element may be placed in series with each of the 7z capacitors.
  • the mounted resistance R m of a given one of the n capacitors may include the ESR of the capacitor, an electrical resistance of a corresponding electrical resistance element in series with the capacitor, and the electrical resistances of all conductors coupling the capacitor between the pair of parallel conductive planes.
  • the electrical resistance value for each of the 7Z electrical resistance elements may be selected such that the mounted resistance R, makeup of each of the n capacitors is equal to the required value of mounted resistance R m , reg . This may be accomplished by determining the mounted resistance R m of a representative one of the n capacitors when coupled between the planar conductors and when the electrical resistance of the corresponding electrical resistance element is zero. In this situation; the mounted resistance R m of the representative capacitor may be equal to the sum of the ESR of the representative capacitor and the electrical resistances of all conductors coupling the capacitor between the planar conductors. The electrical resistance of each of the n electrical resistance elements may be determined by subtracting the mounted resistance R m of the representative capacitor from the required value of mounted resistance R m . req .
  • Figs. 19-25 will now be used to illustrate several embodiments of an electrical power distribution structure including an electrical resistance element coupled in series with a capacitor between a pair of parallel conductive planes separated by a dielectric layer (e.g., between a power plane and a ground plane).
  • electrical resistance elements are incorporated in ways which do not appreciably increase physical dimensions of current loops coupling the capacitor between the pair of parallel conductive planes.
  • the mounted inductance L m of the capacitor is not changed substantially over a corresponding conventional structure.
  • Fig. 19 is a perspective view of aportion 170 of an electrical power distribution structure including a capacitor 172 (e.g., an interdigitated capacitor) mounted upon an upper surface of an interconnecting apparatus 174.
  • Interconnecting apparatus 174 may be, for example, a PCB, a component of a semiconductor device package, or formed upon a surface of an integrated circuit substrate.
  • Interconnecting apparatus 174 includes a signal conductor layer 176, an electrical ground (i.e., ground) conductor layer 178, and an electrical power (i.e., power) conductor layer 180.
  • Capacitor 172 has a body and multiple power and ground terminals positioned along opposite side surfaces of the body. The power and ground terminals alternate along the sides of the body. A total of 8 vias are used to couple capacitor 172 between power conductor layer 180 and ground conductor layer 178. Vias 182A and 182B of Fig. 1 are used to connect corresponding power terminals of capacitor 172 to a portion of power conductor layer 180. Vias 184A and 184B of Fig.
  • capacitor 1 are connected corresponding ground temiinals of capacitor 172 to ground conductor layer 178.
  • Two other vias on a side of capacitor 172 opposite vias 182A, 182B, 184A, and 184B are used to couple corresponding power terminals of capacitor 172 to power conductor layer 180.
  • An additional two vias on the opposite side of capacitor 172 are used to connect corresponding ground terminals of capacitor 172 to ground conductor layer 178.
  • the multiple parallel current paths formed between power conductor layer 180 and ground conductor layer 178 through capacitor 172 reduce a mounted inductance of capacitor 172.
  • Fig. 20 is a top plan view of one embodiment of power conductor layer 180 of Fig. 19 following a process (e.g., an etch process) during which a portion of an electrically conductive material (e.g., a metal) forming power conductor layer 180 is removed from an isolation region 190, thereby forming an island 192 electrically isolated from a remainder 194 of power conductor layer 180.
  • a process e.g., an etch process
  • Fig. 21 is a top plan view of the embodiment of power conductor layer 180 of Fig. 20 following a process during which two resistive stripes 196A and 196B are formed between island 192 and remainder 194 of power conductor layer 180.
  • resistive stripes 196A and 196B are formed in portions of isolation region 190 on opposite sides of island 192.
  • interconnecting apparatus 174 During use of interconnecting apparatus 174 (Fig. 19), an electrical power supply voltage is impressed between remainder 194 of power conductor layer 180 and ground conductor layer 178. Connected between island 192 and ground conductor layer 178 by the 8 vias, capacitor 172 presents an electrical capacitance between island 192 and ground conductor layer 178. Resistive stripes 196A and 196B resistively couple island 192. to remainder 194 of power conductor layer 180. Resistive stripes 196A and 196B, electrically in parallel between island 192 and remainder 194 of power conductor layer 180, present a single value of resistance between island 192 and remainder 194 of power conductor layer 180.
  • resistive stripes 196A and 196B and the electrical capacitance of capacitor 172 are coupled in series between remainder 194 of power conductor layer 180 and ground conductor layer 178, forming a series resistance-capacitance (RC) network between remainder 194 of power conductor layer 180 and ground conductor layer 178.
  • RC resistance-capacitance
  • Resistive stripes 196A and 196B are formed from electrically resistive materials (e.g., resistive inks). Resistive stripes 196A and 196B each present an electrical resistance between island 192 and remainder 194 of power conductor layer 180. The magnitudes of the resistances presented by resistive stripes 196A and 196B depend upon the physical dimensions of respective resistive stripes 196A and 196B. The magnitudes of the resistances presented by resistive stripes 196A and 196B are also dependent upon the electrical resistivities of the electrically resistive materials used to form respective resistive stripes 196A and 196B.
  • electrically resistive materials e.g., resistive inks
  • anchor regions 198 exist in power conductor layer 180 along perimeters of remainder 194 and island 192 adjacent to the portions of isolation region 190 where resistive stripes 196A and 196B are formed.
  • Each anchor region includes a protrusion extending outwardly from a perimeter of remainder 194 toward island 192 and a correspondingly-shaped recess in an adjacent perimeter of island 192.
  • Anchor regions 198 help keep resistive stripes 196A and 196B in place despite any lateral shear forces which may be exerted upon resistive stripes 196A and 196B during assembly of interconnecting apparatus 174.
  • resistive stripes 196A and 196B are formed from a material having an electrical resistivity higher than that of the electrically conductive material (e.g., a metal) removed from power conductor layer 180 to form isolation region 190.
  • a mounted resistance R m of capacitor 172 is increased over a corresponding conventional structure. It is noted that a mounted inductance L, constitu of capacitor 172 would not be expected to change substantially over the corresponding conventional structure as the physical dimensions of the current path through capacitor 172 are substantially unchanged over the corresponding conventional structure.
  • Capacitor 172 may be, for example, one fn capacitors coupled between power conductor layer 180 and ground conductor layer 178 to stabilize the electrical impedance of the electrical distribution structure including power conductor layer 180 and ground conductor layer 178.
  • a target electrical impedance Z may be used to determine a required value of mounted resistance Renfin M . e!] for the n capacitors according to:
  • Capacitor 172 may have an ESR which is less than the required value of mounted resistance i-, makeup- ray .
  • the electrical resistance value offered by resistive stripes 1 6A and 196B in parallel may be selected such that the mounted resistance R m of capacitor 172 is equal to the required value of mounted resistance R m . req . This may be accomplished by deterrnining the mounted resistance Renfin, of capacitor 172 when the electrical resistance value offered by resistive stripes 196A and 196B in parallel is zero.
  • the mounted resistance R personally, of capacitor 172 when the electrical resistance value offered by resistive stripes 196A and 196B in parallel is zero may be equal to the sum of the ESR of capacitor 172 and the electrical resistances of all conductors coupling capacitor 172 between the planar conductors.
  • the electrical resistance value offered by resistive stripes 196A and 196B in parallel may be detemiined by subtracting the mounted resistance R m of capacitor 172 when the electrical resistance value offered by resistive stripes 196A and 196B in parallel is zero from the required value of mounted resistance R m . req .
  • Fig. 22 is a cross sectional view of a portion 200 of an electrical power distribution structure wherein vias with relatively high electrical resistances are used to electrically couple a capacitor 202 (e.g., a multilayer ceramic capacitor) between a planar power conductor (i.e., a power plane) 204 and a planar ground conductor (i.e., a ground plane) 206 of an interconnecting apparatus 203.
  • Capacitor 202 may be, for example, a bypass capacitor.
  • Interconnecting apparatus 203 may be, for example, a PCB, a component of a semiconductor device package, or formed upon a surface of an integrated circuit substrate.
  • Interconnecting apparatus 203 includes multiple layers of planar electrical conductors separated by dielectric layers.
  • capacitor 202 has two terminals 210 and 212 on opposite ends of a body or package.
  • Terminal 210 is electrically connected to a first solder land 214 by a solder fillet 216.
  • Solder land 214 is electrically coupled to ground plane 206 by a via 218.
  • Terminal 212 is electrically connected to a second solder land 220 by a solder fillet 222.
  • Solder land 220 is electrically coupled to power plane 204 by a via 224.
  • Solder lands 214 and 220 are formed within a signal plane 208 of interconnecting apparatus 203.
  • Signal plane 208 includes multiple signal lines (i.e., interconnects or traces) used to convey signals within interconnecting apparatus 203.
  • power plane 204 is connected to a power terminal of an electrical power supply at a power entry point of interconnecting apparatus 203
  • ground plane 206 is connected to a ground terminal of the power supply at the power entry point.
  • Power plane 204 and ground plane 206 provide electrical power to electronic devices connected between power plane 204 and ground plane 206.
  • vias 218 and 224 are formed from a material having an electrical resistivity higher than that of conventional via-forming materials in order to increase a mounted resistance R m of capacitor 202. It is noted that the mounted inductance L justify, of capacitor 202 would not be expected to change substantially over a corresponding conventional structure as only vias 218 and 224 are modified, and the physical dimensions of the current loop coupling capacitor 202 between power plane 204 and ground plane 206 are not increased substantially over the corresponding conventional structure.
  • Capacitor 202 may be, for example, one of ?z capacitors coupled between power plane 204 and ground plane 206 to stabilize the electrical impedance of the electrical distribution structure including power plane 204 and ground plane 206.
  • Capacitor 202 may have an ESR which is less than the required value of mounted resistance R m - req . In this situation, the combined electrical resistance values of vias 218 and 224 may be selected such that tire mounted resistance R, chorus of capacitor 202 is equal to the required value of mounted resistance R m . re .
  • the mounted resistance R, originate of capacitor 202 when the electrical resistances of vias 218 and 224 are both zero may be equal to the sum of the ESR of capacitor 202 and the electrical resistances of all conductors coupling the capacitor between the planar conductors (e.g., the electrical resistances of solder lands 214 and 220, and power plane 204 between via 218 and via 224 due to the length of the capacitor 202 package).
  • Fig. 23 is a cross sectional view of a portion 230 of an electrical power distribution structure wherein an electrically resistive adhesive material is used to electrically couple capacitor 202 between power plane 204 and ground plane 206 of interconnecting apparatus 203. Components of the electrical power distribution structure shown in Fig. 22 and described above are labeled similarly in Fig. 23.
  • terminal 210 of capacitor 202 is electrically connected to first solder land 214 by a first amount of an electrically resistive adhesive material 232.
  • Solder land 214 is electrically coupled to ground plane 206 by a via 234.
  • Terminal 212 is electrically connected to a second solder land 220 by a second amount of the electrically resistive adhesive material 236.
  • Solder land 220 is electrically coupled to power plane 204 by a via 238.
  • the first amount of the electrically resistive adhesive material 232 and the second amount of the electrically resistive adhesive material 236 have electrical resistivities higher than that of conventional solder fillets in order to increase mounted resistance R m of capacitor 202. It is noted that the mounted inductance L m of capacitor 202 would not be expected to change substantially over a corresponding conventional structure as only the mechanisms for attaching te ⁇ ninals 210 and 212 of capacitor 202 to respective solder lands 214 and 220 are modified, and the physical dimensions of the current loop coupling capacitor 202 between power plane 204 and ground plane 206 are not increased substantially over the corresponding conventional structure.
  • capacitor 202 may be one of n capacitors coupled between power plane 204 and ground plane 206 to stabilize the electrical impedance of the electrical distribution structure including power plane 204 and ground plane 206.
  • Capacitor 202 may have an ESR which is less man the required value of mounted resistance R m . req .
  • the combined electrical resistance values of the first amount of the electrically resistive adhesive material 232 and the second amount of the electrically resistive adhesive material 236 may be selected such that the mounted resistance R m of capacitor 202 is equal to the required value of mounted resistance R m . req . This may be accomplished by determining the mounted resistance R m of capacitor 202 when the electrical resistances of the first amount of the electrically resistive adhesive material 232 and the second amount of the electrically resistive adhesive material 236 are both zero.
  • the mounted resistance R,tient of capacitor 202 when the electrical resistances of the first amount of the electrically resistive adhesive material 232 and the second amount of the electrically resistive adhesive material 236 are both zero may be equal to the sum of the ESR of capacitor 202 and the electrical resistances of all conductors coupling tire capacitor between t ire planar conductors (e.g., the electrical resistances of, solder lands 214 and 220, and power plane 204 between via 234 and via 238 due to the length of the capacitor 202 package).
  • the combined electrical resistances of the first amount of the electrically resistive adhesive material 232 and the second amount of the electrically resistive adhesive material 236 may be determined by subtracting the mounted resistance R m of capacitor 202 when the electrical resistances of the first amount of the electrically resistive adhesive material 232 and the second amount of the electrically resistive adhesive material 236 are both zero from fire required value of mounted resistance R m . req .
  • Fig. 24 is a cross sectional view of a portion 240 of an electrical power distribution structure wherein a resistive coupon 242 is positioned between capacitor 202 and interconnecting apparatus 203, and wherein an electrical resistance offered by resistive coupon 242 is electrically coupled in series with capacitor 202 between power plane 204 and ground plane 206 of interconnecting apparatus 203.
  • Components of the electrical power distribution structure shown in Figs. 22-23 and described above are labeled similarly in Fig. 24.
  • terminal 210 of capacitor 202 is electrically connected to a solder land 244 on an upper surface of resistive coupon 242 by a solder fillet 246.
  • Solder land 244 is electrically coupled to a side terminal 248 on a side surface of resistive coupon 242 via a first resistive region 250 of resistive coupon 242.
  • Side terminal 248 of resistive coupon 242 is electrically connected to a solder land 252 of interconnecting apparatus 203 by a solder fillet 254.
  • Solder land 252 of interconnecting apparatus 203 is electrically connected to ground plane 206 by a via 256.
  • Terminal 212 of capacitor 202 is electrically connected to a solder land 258 on the upper surface of resistive coupon 242 by a solder fillet 260.
  • Solder land 258 is electrically coupled to a side te ⁇ ninal 262, on a side surface of resistive coupon 242 opposite side terminal 248, via a second resistive region 264 of resistive coupon 242.
  • Side terminal 262 of resistive coupon 242 is electrically connected to a solder land 266 of interconnecting apparatus 203 by a solder fillet 268.
  • Solder land 266 of interconnecting apparatus 203 is electrically connected to power plane 204 by a via 270.
  • the first resistive region 250 and the second resistive region 264 of resistive coupon 242 have electrical resistivities higher than that of conventional solder fillets in order to increase mounted resistance R m of capacitor 202. It is noted that the mounted inductance L m of capacitor 202 would not be expected to change substantially over a corresponding conventional structure as physical dimensions of resistive coupon 242 may be relatively small, and thus the physical dimensions of the current loop coupling capacitor 202 between power plane 204 and ground plane 206 may not be increased substantially over the corresponding conventional structure.
  • capacitor 202 may be one of n capacitors coupled between power plane 204 and ground plane 206 to stabilize the electrical impedance of the electrical distribution structure including power plane 204 and ground plane 206.
  • a target electrical impedance Z may be used to deteimine a required value of mounted resistance R m . reg for the 7z capacitors according to:
  • Capacitor 202 may have an ESR which is less than the required value of mounted resistance R m . . n this situation, the combined electrical resistance values of the first resistive region 250 and the second resistive region 264 of resistive coupon 242 may be selected such that the mounted resistance R m of capacitor 202 is equal to the required value of mounted resistance R m . req . This may be accomplished by determining the mounted resistance R, reinforce of capacitor 202 when the electiical resistances of the first resistive region 250 and the second resistive region 264 are both zero.
  • the mounted resistance R m of capacitor 202 when the electrical resistances of the first resistive region 250 and the second resistive region 264 are both zero may be equal to the sum of the ESR of capacitor 202 and the electrical resistances of all conductors coupling the capacitor between the planar conductors (e.g., the electrical resistances of solder lands 252 and 266, and power plane 204 between via 256 and via 270 due to the length of the capacitor 202 package).
  • the combined electrical resistances of the first resistive region 250 and the second resistive region 264 may be determined by subtracting the mounted resistance R tannin, of capacitor 202 when the electrical resistances of the first resistive region 250 and the second resistive region 264 are both zero from the required value of mounted resistance R m . req .
  • Fig. 25A is a cross sectional view of a portion 280 of an electrical power distribution structure wherein capacitor 202 is electrically coupled between power plane 204 and ground plane 206 of interconnecting apparatus 203, and wherein capacitor 202 includes an electrical resistance element 282 in series with a capacitance element.
  • Components of the electrical power distribution structure shown in Figs. 22-24 and described above are labeled similarly in Fig. 25A.
  • capacitor 202 in addition to terminals 210 and 212, capacitor 202 includes two interleaved sets of conductive plates arranged in parallel and separated by a dielectric. One of the two sets of conductive plates is electrically connected to terminal 212. The other set of conductive plates is electrically coupled to terminal 210 via internal electrical resistance element 282.
  • Terminal 210 is electrically connected to first solder land 214 by solder fillet 216.
  • Solder land 214 is electrically coupled to ground plane 206 by a via 284.
  • Terminal 212 is electrically connected to second solder land 220 by solder fillet 222.
  • Solder land 220 is electrically coupled to power plane 204 by a via 286.
  • electrical resistance element 282 is formed from a material having a relatively high electrical resistivity (e.g., higher than that of a metal conductor) in order to increase mounted resistance R m of capacitor 202. It is noted that the mounted inductance L m of capacitor 202 would not be expected to change substantially over a corresponding conventional structure as the physical the length of the capacitor 202 package may not be increased significantly. Accordingly, the physical dimensions of the current loop coupling capacitor 202 between power plane 204 and ground plane 206 may not be increased substantially over the corresponding conventional structure.
  • Capacitor 202 may be one of TZ capacitors coupled between power plane 204 and ground plane 206 to stabilize the electrical impedance of the electrical distribution structure including power plane 204 and ground plane 206.
  • a target electrical impedance Z t may be used to dete ⁇ nine a required value of mounted resistance R m . req for the n capacitors according to:
  • Capacitor 202 may have an ESR which is less than the required value of mounted resistance R m . m .
  • the electrical resistance of electrical resistance element 282 may be selected such that the mounted resistance R, chief of capacitor 202 is equal to the required value of mounted resistance R m . req . This may be accomplished by determining the mounted resistance R m of capacitor 202 when the electrical resistance of electiical resistance element 282 is zero.
  • the mounted resistance R,sure of capacitor 202 when the electrical resistance of electrical resistance element 282 is zero may be equal to the sum of the ESR of capacitor 202 and the electrical resistances of all conductors coupling the capacitor between the planar conductors (e.g., the electrical resistances of solder lands 214 and 220, and power plane 204 between via 284 and via 286 due to the length of the capacitor 202 package).
  • the electiical resistance of electrical resistance element 282 may be determined by subtracting the mounted resistance R réelle, of capacitor 202 when the electrical resistance of electrical resistance element 282 is zero from the required value of mounted resistance R réelle,. re .
  • the 72 capacitors may then be selected having internal electrical resistance elements 282 with electrical resistances substantially equal to the detei-mined value of electrical resistance.
  • Fig. 25B is a cross sectional view of the portion 280 of the electrical power distribution structure of Fig.
  • capacitor 202 includes two separate electrical resistance elements 282A and 282B on either side of, and in series with, the capacitance element.
  • Components of the electrical power distribution structure shown in Figs. 22-24 and 25A, and described above, are labeled similarly in Fig. 25B.
  • Fig. 25C is a cross sectional view of the portion 280 of the electrical power distribution structure of Fig. 25A wherein capacitor 202 includes a horizontal resistive layer 288 electrically coupled in series with the capacitance element.
  • Components of the electrical power distribution structure shown in Figs. 22-24 and 25A, and described above, are labeled similarly in Fig. 25B.
  • a bottom edge of a side terminal and a bottom plate of the capacitance element are in contact with horizontal resistive layer 288.
  • Te ⁇ ninal 212 of capacitor 202 is also in contact with horizontal resistive layer 288.
  • horizontal resistive layer 288 is electrically coupled in series with the capacitance element between terminals 210 and 212 of capacitor 202.
  • Figs. 26A-26C in combination form a flow chart of one embodiment of a first method 300 for achieving a target electrical impedance Z, in an electrical power distribution structure including a pair of parallel planar conductors separated by a dielectric layer.
  • a distance d p around the outer edges (i.e., the outer perimeter) of the electrical power distribution structure is determined (e.g., measured) as described above.
  • a separation distance h between the parallel planar conductors required to achieve the target electrical impedance Z is determined during a step 304 using distance d p and the relative dielectric constant ⁇ r of the dielectric layer.
  • the following equation, based on the above empirical formula for the electrical impedance Zp, may be used to dete ⁇ nine separation distance h:
  • a thickness t is selected for the dielectric layer, where t ⁇ h.
  • Step 306 reflects the fact that thicknesses of dielectric layers between electrically conductive layers (e.g., copper sheets) of commercially available multi-layer printed circuit boards are typically selected from a range of available thicknesses. It is very likely that the above empirical formula for h will yield a required separation distance which lies between two available thickness within the range of available thicknesses. Assume, for example, that the above empirical formula for h yields a required separation distance which lies between a first available thickness and second available thickness, where the first available thickness is greater than the second available thickness. In this situation, selected thickness t may be the second available thickness such that t ⁇ h.
  • the selected dielectric layer thickness t is used to determine the inductance L p of the electrical power distribution structure.
  • the following equation may be used to calculate mductance L p :
  • a type of discrete electrical capacitor is selected during a step 310, wherein capacitors of the selected type have at least one substantially identical physical dimension (e.g., a length of the capacitor package between te ⁇ ninals) upon which a mounted inductance of the capacitors is dependent.
  • the at least one substantially identical physical dimension is used to determine a mounted inductance L m of a representative one of the selected type of discrete electrical capacitor when the representative capacitor is electrically coupled between the planar conductors.
  • the mounted inductance L m of the representative discrete electrical capacitor is the electrical inductance resulting from the coupling of the capacitor between the planar conductors.
  • a required number 7z of the selected type of discrete electrical capacitor is determined dependent upon the inductance of the electrical power distribution stracture L p and the mounted inductance L m , wherein n ⁇ 2.
  • the required number n of the selected type of discrete electrical capacitor may be determined using:
  • the target electrical impedance Z t is used during a step 316 to dete ⁇ nine a required value of mounted resistance R m . req for the n discrete electrical capacitors.
  • the required number 72 of the selected type of discrete electrical capacitor are selected, wherein each of the 72 capacitors has an equivalent series resistance (ESR) which is less than the required value of mounted resistance R m . reg .
  • ESR equivalent series resistance
  • a mounted resistance R m of a representative one of the 72 discrete electrical capacitors is determined when an electrical resistance of a corresponding electrical resistance element is zero.
  • each of 72 electrical resistance elements is determined during a step 322 by subtracting the mounted resistance R m of the representative capacitor from the required value of mounted resistance R m - re ⁇
  • the 72 discrete electrical capacitors and the 72 electrical resistance elements are electrically coupled between the planar conductors such that each of the 72 discrete electrical capacitors is coupled in series with a corresponding one of the 72 electrical resistance elements. It is noted that during step 306, it is possible that the above empirical formula for h will yield a required separation distance which is less than a rninimum available thickness. For example, a minimum thickness of dielectric layers for manufactured printed circuit boards may be 2 mils.
  • r is the thickness of the dielectric layer between the z ' thpair of the 72 pairs.
  • the thickness of the dielectric layer between the 7z pairs of parallel planar conductors may be selected from the range of available thicknesses such that the resulting value oft is less than or equal to h.
  • Figs. 27A-27F in combination form a flow chart of one embodiment of a second method 330 for achieving a target electiical impedance Z, in an electrical power distribution stracture including a pair of parallel planar conductors separated by a dielectric layer.
  • a distance d p around the outer edges (i.e., the outer perimeter) of the electrical power distribution structure is determined (e.g., measured) as described above.
  • a separation distance h between the parallel planar conductors required to achieve the target electrical impedance Z is determined during a step 334 using distance d p and the relative dielectric constant ⁇ r of the dielectric layer.
  • the following equation, based on the above empirical formula for electrical impedance Zp, may be used to determine separation distance h:
  • impedance Z is in ohms and distance d p is in inches.
  • a thickness t is selected for the dielectric layer, where t ⁇ h.
  • Step 336 reflects the fact that thicknesses of dielectric layers between electrically conductive layers (e.g., copper sheets) of commercially available multi-layer printed circuit boards are typically selected from a range of available thicknesses. As described above, where the empirical formula for h above yields a required separation distance which lies between a first available thickness and second available thickness, and the first available thickness is greater than the second available thickness, selected thickness t may be the second available thickness such that t ⁇ h.
  • the selected dielectric layer thickness t is used to determine the inductance L p of the electrical power distribution stracture.
  • a type of discrete electrical capacitor is selected during a step 340, wherein capacitors of the selected type have at least one substantially identical physical dimension (e.g., a length of the capacitor package between terminals) upon which a mounted inductance of the capacitors is dependent.
  • the at least one substantially identical physical dimension is used to determine a mounted inductance Long, of a representative one of the selected type of discrete electrical capacitors when the representative capacitor is electrically coupled between the planar conductors.
  • the mounted inductance L m of the representative discrete electrical capacitor is the electrical inductance resulting from the coupling of the capacitor between the planar conductors.
  • a first required number n ⁇ of discrete electiical capacitors is determined dependent upon the inductance of the electrical power distribution structure L p and the mounted inductance L,sky of the selected type of discrete electrical capacitor when electrically coupled between the planar conductors, wherein 7? ⁇ > 2.
  • the first required number n i may be determined using:
  • a second required number n of the selected type of discrete electrical capacitor is determined during a step 346 dependent upon distance d p and a spacing distance S between adjacent discrete electrical capacitors, wherein n 2 > 2.
  • the second required number 7? 2 may be determined using: d ,
  • the electrical power distribution structure may be part of an electrical interconnecth ⁇ g apparatus (e.g., a printed circuit board).
  • spacing distance S may be less than or equal to a maximum spacing distance S max , where S max is a fraction of a wavelength of a maximum frequency / ] ⁇ of a frequency range of electrical signals conveyed within the electrical interconnecting apparatus.
  • step 348 the first and second required numbers 72 ⁇ and 72 2 are compared. If 7Z 2 ⁇ n , step 350 is performed next. On the other hand, if 72 1 > 72 2j step 360 is performed next.
  • the target electrical impedance Z is used to deterrnine a required value of mounted resistance R m . reg for n 2 of the discrete electrical capacitors.
  • the required value of mounted resistance Renfin,. req for the n 2 capacitors may be determined using:
  • the number n 2 of the discrete electrical capacitors are selected during step 352, wherein each of the n 2 capacitors has an equivalent series resistance (ESR) which is less than the value of required mounted resistance R m . req .
  • ESR equivalent series resistance
  • a mounted resistance R réelle, of a representative one of the n 2 capacitors is determined when the representative capacitor is coupled between the pair of parallel planar conductors and when an electrical resistance of a corresponding electrical resistance element is zero.
  • the electrical resistance of each of n 2 electrical resistance elements is determined during a step 356 by subtracting the mounted resistance Renfin, of the representative capacitor from the required value of mounted resistance R m . reg .
  • the n 2 discrete electrical capacitors and the 7Z 2 electrical resistance elements are electrically coupled between the planar conductors along an outer perimeter of the parallel planar conductors such that each of the n 2 discrete electrical capacitors is coupled in series with a corresponding one of the n 2 electrical resistance elements.
  • the target electrical impedance Z is used to determine a required value of mounted resistance Renfin,. re for 72 1 of the discrete electrical capacitors dependent upon.
  • the required value of mounted resistance R m . req for the 72 1 capacitors may be determined using:
  • each of the 72 1 capacitors has an equivalent series resistance (ESR) which is greater than the required value of mounted resistance R- m - req -
  • ESR equivalent series resistance
  • a mounted resistance R m of a representative one of the Z ⁇ capacitors is determined when the representative capacitor is coupled between the pair of parallel planar conductors and when an electrical resistance of a corresponding electrical resistance element is zero.
  • the electrical resistance of each of « ⁇ electrical resistance elements is determined during a step 366 by subtracting the mounted resistance R, reinforce of the representative capacitor from the required value of mounted resistance R, reconsider. req .
  • the 72 ! discrete electrical capacitors and the 7Z] electrical resistance elements are electrically coupled between the planar conductors such that: (i) each of the ⁇ i ⁇ discrete electrical capacitors is coupled in series with a corresponding one of the n electrical resistance elements, (ii) 77 2 of the discrete electrical capacitors and the corresponding electrical resistance elements are positioned along an outer perimeter of the planar conductors, and (iii) the remaining (72 1 - 72 2 ) capacitors and the corresponding electiical resistance elements are dispersed across a surface of at least one of the planar conductors.
  • step 336 it is possible that the above empirical formula for h will yield a required separation distance which is less than a n-inimum available thickness.
  • a minimum thickness of dielectric layers for manufactured printed circuit boards may be 2 mils. If tire above empirical formula for h yields a required separation distance which is less titan 2 mils, it is possible to add additional pairs of parallel planar conductors to the electiical power distribution structure such that an equivalent thickness t between a representative single pair of parallel planar conductors is achieved.
  • a minimum thickness of dielectric layers for manufactured printed circuit boards may be 2 mils.
  • t t is the thickness of the dielectric layer between the z ' th pair of the n pairs.
  • the thickness of the dielectric layer between the n pairs of parallel planar conductors may be selected from the range of available thicknesses such that the resulting value of t is less than or equal to h.
PCT/US2001/043553 2000-11-17 2001-11-14 Adding electrical resistance in series with bypass capacitors to achieve a desired value of electrical impedance between conductors of an electrical power distribution structure WO2002041673A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002225683A AU2002225683A1 (en) 2000-11-17 2001-11-14 Adding electrical resistance in series with bypass capacitors to achieve a desired value of electrical impedance between conductors of an electrical power distribution structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/715,723 US6525622B1 (en) 2000-11-17 2000-11-17 Adding electrical resistance in series with bypass capacitors to achieve a desired value of electrical impedance between conducts of an electrical power distribution structure
US09/715,723 2000-11-17

Publications (2)

Publication Number Publication Date
WO2002041673A2 true WO2002041673A2 (en) 2002-05-23
WO2002041673A3 WO2002041673A3 (en) 2002-10-10

Family

ID=24875218

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/043553 WO2002041673A2 (en) 2000-11-17 2001-11-14 Adding electrical resistance in series with bypass capacitors to achieve a desired value of electrical impedance between conductors of an electrical power distribution structure

Country Status (3)

Country Link
US (2) US6525622B1 (US06525622-20030225-M00005.png)
AU (1) AU2002225683A1 (US06525622-20030225-M00005.png)
WO (1) WO2002041673A2 (US06525622-20030225-M00005.png)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004073367A1 (de) * 2003-02-11 2004-08-26 Robert Bosch Gmbh Vorrichtung und verfahren zur dämpfung von hohlraumresonanzen in einer mehrschichtigen trägereinrichtung
WO2007046776A1 (en) * 2005-10-18 2007-04-26 Agency For Science, Technology And Research Capacitor interconnection
CN109076697A (zh) * 2016-05-02 2018-12-21 Lg伊诺特有限公司 印刷电路板及包括该印刷电路板的电子元件封装

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525622B1 (en) * 2000-11-17 2003-02-25 Sun Microsystems, Inc. Adding electrical resistance in series with bypass capacitors to achieve a desired value of electrical impedance between conducts of an electrical power distribution structure
US6606012B2 (en) * 2001-04-03 2003-08-12 Sun Microsystems, Inc. Wideband bypass capacitor methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure
US6704669B2 (en) * 2001-04-25 2004-03-09 International Business Machines Corporation Method for determining voltage, current, and/or power distributions in a resistive structure using a rectangular grid algorithm modified for non-rectangular holes and contacts
US7239524B2 (en) * 2001-10-12 2007-07-03 Intel Corporation Resistive element apparatus and method
US6727780B2 (en) * 2001-10-24 2004-04-27 Sun Microsystems, Inc. Adding electrical resistance in series with bypass capacitors using annular resistors
US7017086B2 (en) 2002-06-18 2006-03-21 Sun Microsystems, Inc. Round-robin updating for high speed I/O parallel interfaces
US7062688B2 (en) 2002-07-16 2006-06-13 Sun Microsystems, Inc. Updating high speed parallel I/O interfaces based on counters
US7043379B2 (en) * 2002-10-22 2006-05-09 Sun Microsystems, Inc. Method for quantifying I/O chip/package resonance
US7117459B2 (en) * 2002-11-26 2006-10-03 Matsushita Electric Industrial Co., Ltd. Layout check system
US7043683B2 (en) 2003-02-07 2006-05-09 Sun Microsystems, Inc. Data transmission update technique in low power modes
US7249337B2 (en) * 2003-03-06 2007-07-24 Sanmina-Sci Corporation Method for optimizing high frequency performance of via structures
US7310243B2 (en) * 2004-06-10 2007-12-18 International Business Machines Corporation Method and components for implementing EMC shielded resonance damping
JP4615962B2 (ja) * 2004-10-22 2011-01-19 ルネサスエレクトロニクス株式会社 半導体装置
FR2878091B1 (fr) * 2004-11-18 2007-12-14 Eric Brandizi Amelioration de la qualite des appareils analogiques a large bande
JP2006261213A (ja) * 2005-03-15 2006-09-28 Fujitsu Ltd 電子回路
US8144142B2 (en) 2005-04-21 2012-03-27 Panasonic Corporation Drive circuit and display device
US20070279882A1 (en) * 2006-06-06 2007-12-06 Samtec, Inc. Power distribution system for integrated circuits
US7773390B2 (en) * 2006-06-06 2010-08-10 Teraspeed Consulting Group Llc Power distribution system for integrated circuits
US7886431B2 (en) * 2006-06-06 2011-02-15 Teraspeed Consulting Group Llc Power distribution system for integrated circuits
JP2013507040A (ja) 2009-10-01 2013-02-28 ラムバス・インコーポレーテッド 供給ノイズおよび終端ノイズの低減方法およびシステム
US20120325537A1 (en) * 2010-03-08 2012-12-27 Nec Corporation Circuit board, electronic apparatus, and noise blocking method
JP2012156184A (ja) * 2011-01-24 2012-08-16 Nec Corp 実装基板及びその製造方法
CN104112048B (zh) * 2014-07-15 2017-02-15 西安电子科技大学 基于最大反谐振点的电源分配网络去耦电容器选择方法
TWI596985B (zh) * 2015-07-22 2017-08-21 億光電子工業股份有限公司 發光裝置
US10785867B2 (en) * 2018-09-25 2020-09-22 International Business Machines Corporation Automatic determination of power plane shape in printed circuit board
GB2618320A (en) * 2022-04-28 2023-11-08 Energy Res Lab Ltd Electronic device with an embedded HFAC power distribution bus

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5708400A (en) * 1996-10-30 1998-01-13 Hewlett-Packard Company AC coupled termination of a printed circuit board power plane in its characteristic impedance
EP0873046A1 (en) * 1996-10-07 1998-10-21 Fuji Xerox Co., Ltd. Printed wiring board device
US5844762A (en) * 1992-10-20 1998-12-01 Hitachi, Ltd. Electronic circuit device having a function of inhibiting resonance in power wiring
US5898576A (en) * 1996-11-12 1999-04-27 Bay Networks Inc. Printed circuit board including a terminated power plane and method of manufacturing the same
DE19911731A1 (de) * 1998-03-16 1999-10-07 Nec Corp Gedruckte Leiterplatte
US5966294A (en) * 1996-12-20 1999-10-12 Nec Corporation Printed circuit board for prevention of unintentional electromagnetic interference
WO1999060699A1 (en) * 1998-05-19 1999-11-25 Sun Microsystems, Inc. System and method for edge termination of parallel conductive planes in an electrical interconnecting apparatus
WO1999066555A1 (en) * 1998-06-18 1999-12-23 Sun Microsystems, Inc. Method for determining the desired decoupling components for power distribution systems

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3209284A (en) 1963-06-05 1965-09-28 Charles O Hast Termination for strip transmission lines
US3678417A (en) 1971-07-14 1972-07-18 Collins Radio Co Planar r. f. load resistor for microstrip or stripline
US4371746A (en) 1978-01-05 1983-02-01 Peptek, Incorporated Edge terminations for impedance planes
JPS60134440A (ja) 1983-12-23 1985-07-17 Hitachi Ltd 半導体集積回路装置
US5068631A (en) * 1990-08-09 1991-11-26 At&T Bell Laboratories Sub power plane to provide EMC filtering for VLSI devices
US5114912A (en) 1991-05-13 1992-05-19 The United States Of America As Represented By The Secretary Of Commerce Two-dimensional, Josephson-array, voltage-tunable, high-frequency oscillator
US5266036A (en) 1992-06-02 1993-11-30 Hewlett-Packard Company Reduction of radio frequency emissions through terminating geometrically induced transmission lines in computer products
JP3089443B2 (ja) 1992-07-24 2000-09-18 本田技研工業株式会社 非放射性誘電体線路
US5598131A (en) 1995-11-16 1997-01-28 Emc Technology, Inc. AC coupled termination
US5818315A (en) 1996-12-31 1998-10-06 Lucent Technologies Inc. Signal trace impedance control using a grid-like ground plane
US6058022A (en) * 1998-01-07 2000-05-02 Sun Microsystems, Inc. Upgradeable PCB with adaptable RFI suppression structures
US6104258A (en) 1998-05-19 2000-08-15 Sun Microsystems, Inc. System and method for edge termination of parallel conductive planes in an electrical interconnecting apparatus
US6215372B1 (en) * 1999-06-02 2001-04-10 Sun Microsystems, Inc. Method and apparatus for reducing electrical resonances in power and noise propagation in power distribution circuits employing plane conductors
US6525945B1 (en) * 1999-08-20 2003-02-25 International Business Machines Corporation Method and system for wide band decoupling of integrated circuits
US6525622B1 (en) * 2000-11-17 2003-02-25 Sun Microsystems, Inc. Adding electrical resistance in series with bypass capacitors to achieve a desired value of electrical impedance between conducts of an electrical power distribution structure

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844762A (en) * 1992-10-20 1998-12-01 Hitachi, Ltd. Electronic circuit device having a function of inhibiting resonance in power wiring
EP0873046A1 (en) * 1996-10-07 1998-10-21 Fuji Xerox Co., Ltd. Printed wiring board device
US5708400A (en) * 1996-10-30 1998-01-13 Hewlett-Packard Company AC coupled termination of a printed circuit board power plane in its characteristic impedance
US5898576A (en) * 1996-11-12 1999-04-27 Bay Networks Inc. Printed circuit board including a terminated power plane and method of manufacturing the same
US5966294A (en) * 1996-12-20 1999-10-12 Nec Corporation Printed circuit board for prevention of unintentional electromagnetic interference
DE19911731A1 (de) * 1998-03-16 1999-10-07 Nec Corp Gedruckte Leiterplatte
WO1999060699A1 (en) * 1998-05-19 1999-11-25 Sun Microsystems, Inc. System and method for edge termination of parallel conductive planes in an electrical interconnecting apparatus
WO1999066555A1 (en) * 1998-06-18 1999-12-23 Sun Microsystems, Inc. Method for determining the desired decoupling components for power distribution systems

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004073367A1 (de) * 2003-02-11 2004-08-26 Robert Bosch Gmbh Vorrichtung und verfahren zur dämpfung von hohlraumresonanzen in einer mehrschichtigen trägereinrichtung
US7643308B2 (en) 2003-02-11 2010-01-05 Robert Bosch Gmbh Device and method for damping cavity resonance in a multi-layer carrier module
WO2007046776A1 (en) * 2005-10-18 2007-04-26 Agency For Science, Technology And Research Capacitor interconnection
US7705691B2 (en) 2005-10-18 2010-04-27 Agency For Science, Technology & Research Capacitor interconnection
CN109076697A (zh) * 2016-05-02 2018-12-21 Lg伊诺特有限公司 印刷电路板及包括该印刷电路板的电子元件封装
CN109076697B (zh) * 2016-05-02 2021-08-03 Lg伊诺特有限公司 印刷电路板及包括该印刷电路板的电子元件封装

Also Published As

Publication number Publication date
US20030107452A1 (en) 2003-06-12
US6525622B1 (en) 2003-02-25
WO2002041673A3 (en) 2002-10-10
US6674338B2 (en) 2004-01-06
AU2002225683A1 (en) 2002-05-27

Similar Documents

Publication Publication Date Title
WO2002041673A2 (en) Adding electrical resistance in series with bypass capacitors to achieve a desired value of electrical impedance between conductors of an electrical power distribution structure
US6104258A (en) System and method for edge termination of parallel conductive planes in an electrical interconnecting apparatus
EP1078452B1 (en) System and method for edge termination of parallel conductive planes in an electrical interconnecting apparatus
US6215372B1 (en) Method and apparatus for reducing electrical resonances in power and noise propagation in power distribution circuits employing plane conductors
US5010641A (en) Method of making multilayer printed circuit board
US6441313B1 (en) Printed circuit board employing lossy power distribution network to reduce power plane resonances
US20080273311A1 (en) Enhanced Localized Distributive Capacitance for Circuit Boards
US9967969B2 (en) Multilayer printed circuit board with switching power supply capacitors, broad patterns, and TT-type filter
EP1295516B1 (en) Bypass capacitor methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure, and associated electrical power distribution structures
US6727780B2 (en) Adding electrical resistance in series with bypass capacitors using annular resistors
KR100769536B1 (ko) 공통 커플링 영역을 갖는 매립식 커패시터 장치
US7818704B1 (en) Capacitive decoupling method and module
US7035082B2 (en) Structure of multi-electrode capacitor and method for manufacturing process of the same
US6181571B1 (en) Printed-wiring board and electronic device having the same wiring board
JP3782577B2 (ja) 多層プリント配線板及び該配線板を備えた電子機器
US6559733B2 (en) Reducing effects of electrical impedance
JP3559706B2 (ja) 電子機器
US7626828B1 (en) Providing a resistive element between reference plane layers in a circuit board
JP2010114738A (ja) プリント基板実装部品
Cyr et al. ARIES: using annular ring embedded resistors to set capacitor ESR in power distribution networks
JP6421467B2 (ja) Ｅｍｉ対策用コンデンサの実装方法
US20120262829A1 (en) Protection device against electromagnetic interference
Davis PCB Planning for High–speed Systems
JPH1032388A (ja) 多層プリント基板
JPH07202374A (ja) プリント基板のパターン

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP