Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/69—Spread spectrum techniques
  • H04B1/707—Spread spectrum techniques using direct sequence modulation
  • H04B1/7073—Synchronisation aspects
  • H04B1/7075—Synchronisation aspects with code phase acquisition
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
  • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
  • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
  • H04B2201/70707—Efficiency-related aspects
  • H04B2201/7071—Efficiency-related aspects with dynamic control of receiver resources
  • H04B2201/70711—Efficiency-related aspects with dynamic control of receiver resources with modular structure

Definitions

• This invention refers to the electronic devices made for telecommunications systems in the form of integrated circuits, and in particular it relates to a receiver for code division radio interface.
• CDMA Code Division Multiple Access
• the CDMA radio terminals separate the communication channels using digital techniques, and not only frequency techniques. Several users, in fact, can share the same frequency by adjusting the powers of transmission in relation to their position to the radiobase station.
• the signal received from each terminal is converted into baseband, which obtains a group of digital signals that represent the sum of all the signals and codes relating to the users that are transmitting at that moment on the frequency band assigned to the service.
• the information destined for each user is extracted with a device that correlates the group of digital signals received with the user's code. This is done at time intervals corresponding to the delays introduced by the transmission channel, and the results obtained are subsequently combined to maximise the signal/noise relationship of the information received.
• This device is commonly known as "Rake receiver”.
• These receivers can be made in different ways, in particular, they may be the result of software by using a microprocessor and/or a DSP (Digital Signal Processor) or they may consist of a hybrid solution including a dedicated electronic circuit, which carries out most of the tasks.
• the software program carries out the operations of correlation and combination described previously in an autonomous fashion, in the latter case the same operations are mainly carried out by the electronic circuit, which is interfaced with a microprocessor and/or a DSP.
• the second method may be advantageous in many cases, both in terms of power dissipated by the receiver, due to the fact that less calculation capacity is required, and in terms of execution speed, due to the fact that the calculation capacity is exclusively dedicated to the extraction of information. It is a known fact that it is very important to keep the dissipated power to the minimum, especially if the receiver is part of a battery- run mobile terminal.
• the second method includes the solution described in the Technical Report N. 94/9 of May 1994 entitled "SHIVA.Correlator/Demodulator Chip for Direct-Sequence Spread- Spectrum RAKE-Receiver" by Reto Zimmermann and Matthias Neeracher.
• This document describes a circuit that permits the correlation of the signal received with the user code and the demodulation operations of a "rake receiver” for a CDMA-type radio interface. The correlation is performed by six arms, each of which is synchronised to a different signal delay of the received signal.
• the demodulation part performs the phase estimation and correction, and a weighted path recombination of the correlated data.
• the circuit can be interfaced with a processing system, which controls it and extracts data.
• This solution offers limited programmability, in that, for example, the number of bits of the input and output buses is fixed, as is the number of arms in the receiver, which makes it difficult to adapt it to different systems. Moreover, it does not allow for circuit sharing which would minimise the silicon area and the dissipated power, due to the fact that a specific multiplier for performing the correlation is dedicated to each signal arm. This means that 8 multipliers are needed (2 multipliers for 4 correlator arms), and consequently this takes up a considerable area and results in high power dissipation.
• the code division radio interface receiver described in this invention solves the aforesaid technical problems and difficulties. It can do this due to the fact that it can be designed as an integrated circuit library cell and as such has a high degree of flexibility that permits it to be integrated in different devices. The user can select both the number of arms and the number of input/output bus bits in relation to the preferred application.
• the specification parameters can be setup thanks to the use of high-level Hardware Description Languages (HDL) that permit subsequent automatic synthesis of the integrated circuit by dedicated programs.
• HDL Hardware Description Language
• Receiver power consumption is also low due to the use of a single shared multiplier and to the fact that parts of the circuit can be momentarily inhibited when not used.
• the object of this invention is a code division radio interface receiver as described in the characterising part of claim 1.
• Fig. 1 is a block diagram of the terminal's processing system in baseband
• - Fig. 2 is a block diagram of the receiver indicated with RR in Fig. 1 ;
• Fig. 3 is a block diagram of the block indicated with MX in Fig. 2;
• Fig. 1 illustrates a block diagram of the processing system in baseband of the signal received or transmitted by the telecommunications terminal.
• This system codes and decodes the signal, modulates and demodulates it and interfaces with the terminal peripherals (keyboard, viewer, etc.). It includes at least one control microprocessor MC and one or more data processing devices, such as DSP, one f which is illustrated in the figure and indicated with DP.
• DSP data processing devices
• the RR block is the receiver considered in this invention, which works as a hardware accelerator associated with the DSP, and it has the job of performing some of the critical functionalities relating to the timing and/or power dissipation.
• the RR receiver receives the user codes and data from a terminal interface (where the codes are generated locally and the data are received from the remote terminal) on connection 8.
• Connection 4 receives the weights, which are stored by the DP in the WM memory via connection 1 , to which the relative write command signals are also transferred.
• the weights, used as RR input data multipliers, are produced by DP according to the data received and the outputs of the RR.
• the WM can be read according to the signals generated by RR on connection 3.
• the data output from the receiver RR and the relative validity signal, present on connection 5 and wire 6 respectively, are sent to the data processing device, DP, which reconstructs the effective sequence of the bits transmitted, using special decision algorithms.
• each bit in a CDMA-type systems is coded with a precise binary sequence before it is transmitted.
• Receiver architecture is illustrated in the block diagram in Fig. 2.
• the block indicated with CC is the decoding unit in the CDMA structure.
• each bit transmitted is coded with a bit sequence called "chip", which lasts 1/n of the symbol time, where n is the spreading factor of the selected service.
• Chip bit sequence
• Each sequence is associated to a specific user code, and is therefore unique.
• Block CC consisting basically of a counter, counts the "chips" received on the input, as well as the CLK clock and the RSTN reset signals, a STARTCNT count start signal and a LDSTART load signal.
• the load signal allows the counter to load a predetermined value from which to start the count via the STARTVAL connection. This allows the counter to resynchronise itself to any progressive number of "chips".
• the counter outputs the count made, which is increased at each clock cycle, on the CHIPCNT connection, This timing information is used by the whole system.
• the number of wires for the STARTVAL input and the CHIPCNT output connections depends on the the counter module, which is a parameter defined at the project stage.
• the signals on wires STARTCNT, LDSTART and STARTVAL are supplied by the control microprocessor MC (Fig. 1 ) on connection 2.
• Block BB consists of a programmable number of sub-blocks, generally 1 to 8, making up the receiver correlation arms.
• Each arm inputs a clock signal via its CLKB connection wire, and a synchronism signal via its SYNCN connection wire.
• Each arm independently of the others, can inhibit the clock signal, in order to stop it functioning if it is not necessary, and thus reduce the amount of power dissipated.
• a single synchronism signal can also be inhibited so that each arm can start processing at different instants with respect to the other arms.
• a signal that makes the processing in the arms compatibile with the 2's complement input data can be set on the wire COMPLEMENT2, which is common to all the arms.
• connection SHIFT-SCALE-ARM which belongs to connection 2, in order to produce a result consisting of the same number of bits as the input data.
• the user codes to be applied to the input data for the phase and quadrature parts are to be found on connections PN1 and PN2, and are independent for each arm.
• the number of data bits input on IN-I and IN-Q, and of the individual weights PN1 and PN2, and therefore the number of wires for the relative connections, is a parameter that can be defined during the initial project, which may vary between 12 and 20 for the former and between 2 and 16 for the latter. These connections belong to connection 8, which has already been described.
• connections DE-I and DE-Q consisting of a number of wires equal to the number of data bits multiplied by the number of arms.
• Block CO generates specific time signals for each arm of the block BB according to the signals supplied by the control microprocessor MC (Fig. 1) on connection 2.
• connection SF The information relating to the "spreading factor", i.e. the number of "chips” used to code the transmission of the information unit, is to be found on connection SF.
• the maximum number of "chips” for the receiver discussed in this invention may be fixed at 512, which means the SF connection will consist of 9 wires.
• the value on SF is the maximum number that can be reached by the counter for a single processing operation.
• the clock and reset signals are to be found on the wires CLK and RSTN.
• connection ARMPOSINI belongs to connection 2 together with the SF.
• This connection consequently consists of a number of wires equal to 9 multiplied by the number of arms used in the specific receiver.
• a synchronism signal is made available on the output of block CO, which is sent via the SYNCN connection to each arm of block BB.
• Block CO consists basically of a counter and a comparator.
• the counter starts counting with the signal on the STARTCNT wire; when the value reaches the value on the connection ARMPOSINI for each arm, the comparator gives the synchronism signal on the connection SYNCN to start processing independently for each arm.
• Block MX inputs the information processed by the single arms in block BB and multiplies them by the weights given by the WM memory (Fig. 1), separately for the phase and quadrature components.
• MX outputs the result obtained from adding the partial products relating to each arm, scaled to give a number of bits that corresponds to that on the input.
• MX uses only one multiplier, which is appropriately timed to handle the products in each arm both for the phase component and the quadrature component.
• MX inputs a clock signal and a reset signal on wires CLK and RSTN.
• MX receives synchronisation information of each arm in the BB block on connection SYNCN and a signal that is the same as the one described for the BB block on the wire COMPLEMENT2.
• Another connection consisting of two wires and indicated with SHIFT-SCALE-MX belonging to connection 2, also exists and it bears a signal capable of scaling the result of the accumulation of a factor linked to the number of arms actually used.
• the data processed by block BB is sent to connections DE-I and DE-Q, and the output data, separated into phase and quadrature components, is sent to connections I and Q, belonging to connection 5.
• Another output 3 gives the WM addresses (Fig. 1) where the weights used as input data multipliers are picked up via connections WEIGHT-I and WEIGHT-Q of connection 4.
• a synchronism signal that is active when the output data on connections I and Q are valid is output on wire 6.
• Block MX is illustrated in greater detail in Fig. 3.
• the data on the connections DE-I and DE-Q and the respective weights on the connections WEIGHT-I and WEIGHT-Q are appropriately selected by the multiplexers MUX1 and MUX2 respectively, under the control of the synchronism signals of each arm, present on the SYNCN connection.
• Multiplication is performed using only one elementary multiplier PROD, on the output of which the phase or quadrature component of the product is forwarded by a demultiplexer DEMUX, controlled by the signal on connection SYNCN, to the accumulators ACC-I or ACC-Q respectively.
• Block CNT reveals the instant in which the processing cycle of all the arms is concluded by means of a simple count operation of the synchronism signal on the connection SYNCN, and then it communicates the instant in which the output data on I and Q are definitely valid and supplies the signals for addressing the WM memory (Fig. 1 ) on connection 3 by means of a signal on wire 6.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Mobile Radio Communication Systems (AREA)
• Circuits Of Receivers In General (AREA)
• Structure Of Receivers (AREA)

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Publications (1)

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Citations (3)

• 2000
  • 2000-11-14 IT IT2000TO001057A patent/IT1321057B1/it active
• 2001
  • 2001-11-09 WO PCT/IT2001/000566 patent/WO2002041514A1/it not_active Application Discontinuation
  • 2001-11-09 AU AU2002216360A patent/AU2002216360A1/en not_active Abandoned

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