WO2002035607A3 - Semiconductor assembly and method for producing semiconductor assemblies of this type - Google Patents
Semiconductor assembly and method for producing semiconductor assemblies of this type Download PDFInfo
- Publication number
- WO2002035607A3 WO2002035607A3 PCT/DE2001/003880 DE0103880W WO0235607A3 WO 2002035607 A3 WO2002035607 A3 WO 2002035607A3 DE 0103880 W DE0103880 W DE 0103880W WO 0235607 A3 WO0235607 A3 WO 0235607A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- interposer
- semiconductor
- assemblies
- type
- chip
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
An interposer (IP) comprised of an elastic dielectric is formed on the active surface of a semiconductor wafer, whereby electrically conductive connections (V) that are formed inside the interposer (IP) connect, in an electrically conductive manner, chip-side contacts (K) with terminals (A) on the top surface (OS) of the interposer (IP). The individual semiconductor assemblies (HA) subsequently result by dividing up the semiconductor wafer. The different thermal expansion behavior of the chip (C) and of the circuit support is largely compensated for by the elasticity of the interposer (IP) and by the preferably meandering design of the connections (V).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10052452.4 | 2000-10-23 | ||
DE2000152452 DE10052452A1 (en) | 2000-10-23 | 2000-10-23 | Semiconductor arrangement and method for producing such semiconductor arrangements |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002035607A2 WO2002035607A2 (en) | 2002-05-02 |
WO2002035607A3 true WO2002035607A3 (en) | 2002-10-03 |
Family
ID=7660718
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2001/003880 WO2002035607A2 (en) | 2000-10-23 | 2001-10-10 | Semiconductor assembly and method for producing semiconductor assemblies of this type |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE10052452A1 (en) |
WO (1) | WO2002035607A2 (en) |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5019673A (en) * | 1990-08-22 | 1991-05-28 | Motorola, Inc. | Flip-chip package for integrated circuits |
EP0465197A2 (en) * | 1990-07-02 | 1992-01-08 | General Electric Company | Multi-sublayer dielectric layers |
DE4228274A1 (en) * | 1992-08-26 | 1994-03-03 | Siemens Ag | Device contacting process for high density connections - esp. for contacting LEDs on common silicon@ chip without use of bonding techniques |
WO1998025298A1 (en) * | 1996-12-04 | 1998-06-11 | Seiko Epson Corporation | Semiconductor device, method for manufacture thereof, circuit board, and electronic equipment |
WO1999065075A1 (en) * | 1998-06-12 | 1999-12-16 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
WO2000003571A1 (en) * | 1998-07-10 | 2000-01-20 | Siemens S.A. | Method for producing interconnections with electrically conductive cross connections between the top and the bottom part of a substrate and interconnections having such cross connections |
WO2000004584A2 (en) * | 1998-07-14 | 2000-01-27 | Infineon Technologies Ag | Semiconductor component in a chip format and method for the production thereof |
EP0991119A1 (en) * | 1997-06-06 | 2000-04-05 | Matsushita Electronics Corporation | Semiconductor device and method for manufacturing the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3050807B2 (en) * | 1996-06-19 | 2000-06-12 | イビデン株式会社 | Multilayer printed wiring board |
JPH1174399A (en) * | 1997-08-28 | 1999-03-16 | Mitsubishi Electric Corp | Semiconductor device |
SG111958A1 (en) * | 1998-03-18 | 2005-06-29 | Hitachi Cable | Semiconductor device |
-
2000
- 2000-10-23 DE DE2000152452 patent/DE10052452A1/en not_active Withdrawn
-
2001
- 2001-10-10 WO PCT/DE2001/003880 patent/WO2002035607A2/en active Application Filing
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0465197A2 (en) * | 1990-07-02 | 1992-01-08 | General Electric Company | Multi-sublayer dielectric layers |
US5019673A (en) * | 1990-08-22 | 1991-05-28 | Motorola, Inc. | Flip-chip package for integrated circuits |
DE4228274A1 (en) * | 1992-08-26 | 1994-03-03 | Siemens Ag | Device contacting process for high density connections - esp. for contacting LEDs on common silicon@ chip without use of bonding techniques |
WO1998025298A1 (en) * | 1996-12-04 | 1998-06-11 | Seiko Epson Corporation | Semiconductor device, method for manufacture thereof, circuit board, and electronic equipment |
US6255737B1 (en) * | 1996-12-04 | 2001-07-03 | Seiko Epson Corporation | Semiconductor device and method of making the same, circuit board, and electronic instrument |
EP0991119A1 (en) * | 1997-06-06 | 2000-04-05 | Matsushita Electronics Corporation | Semiconductor device and method for manufacturing the same |
WO1999065075A1 (en) * | 1998-06-12 | 1999-12-16 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
EP1091399A1 (en) * | 1998-06-12 | 2001-04-11 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
WO2000003571A1 (en) * | 1998-07-10 | 2000-01-20 | Siemens S.A. | Method for producing interconnections with electrically conductive cross connections between the top and the bottom part of a substrate and interconnections having such cross connections |
WO2000004584A2 (en) * | 1998-07-14 | 2000-01-27 | Infineon Technologies Ag | Semiconductor component in a chip format and method for the production thereof |
Also Published As
Publication number | Publication date |
---|---|
WO2002035607A2 (en) | 2002-05-02 |
DE10052452A1 (en) | 2002-05-08 |
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Legal Events
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