JPH1174399A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase an area for providing a signal wiring and enable formation of a signal wiring having a thicker width, by a method wherein at least one second wiring connected to a power source and at least one third wiring connected to a ground are arranged adjacent to each other on a straight line in parallel to a setting direction of the first wiring. SOLUTION: A power source wiring 9a is connected to a power source wiring on an upper face of a second insulating layer through a via hole on a left side of a black circle. A ground wiring 9b is connected to a ground wiring on an upper face of the second wiring layer through a via hole formed on a right side of a black circle of the near power source wiring 9a. A most leftward signal line 9c among the signal lines 9c is drawn around toward the outside of a BGA substrate on an upper face of a first insulating layer 1a1 . The other signal wirings 9c are connected to a signal wiring on an upper face of the second insulating layer through a via hole on a right side of a black circle. As the power source wiring and the ground wiring are arranged adjacent to each other on a straight line in parallel to a setting direction of the signal wiring, it is possible to increase an area for providing the signal wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ball grid array (BGA) in which solder balls used for soldering when a semiconductor device is mounted on a product are arranged on the back surface of a substrate in a matrix.
The present invention relates to a package structure of a semiconductor device having a rid array structure.

[0002]

2. Description of the Related Art A conventional semiconductor device comprises a BGA substrate, a semiconductor chip disposed on the BGA substrate, a heat spreader for dissipating heat generated in the semiconductor chip to the outside, and a heat spreader between the BGA substrate and the heat spreader. And a ring for providing a predetermined interval and joining the two. The BGA substrate has a multilayer structure in which a plurality of insulating layers are stacked, and each insulating layer is provided with a plurality of wirings and via holes. The BGA substrate has predetermined wirings connected to each other via via holes when a plurality of substrates are stacked. The BGA substrate can three-dimensionally intersect a plurality of wirings via an insulating layer, and the semiconductor device has a small size. Can be realized.

FIG. 10 is a partially cutaway perspective view showing an example of a conventional semiconductor device. In FIG. 10, 1 is BG
A BGA substrate as an A substrate, 2 a semiconductor chip, 3 a heat spreader, 4 a ring, 6 a solder ball, and 8 a sealing member.

[0004] Each wiring (not shown) provided on the BGA substrate 1 is electrically connected to an external electrode (not shown) of the semiconductor device. The solder ball 6 is made of a solder material,
It is electrically connected to an external electrode of the semiconductor device. A plurality of electrodes (not shown) of the semiconductor chip 2 are electrically connected to predetermined wirings of the BGA substrate 1, respectively. The connection is realized, for example, by providing solder bumps in advance on the external electrode surfaces connected to the respective electrodes of the semiconductor chip 2 and the respective wiring surfaces of the BGA substrate 1, and soldering using the solder bumps. The sealing member 8 is made of a sealing resin, and is provided for bringing the semiconductor chip 2 into close contact with the BGA substrate 1. That is, the sealing member 8 is provided so as not to be broken at the connection portion between the wiring of the BGA substrate 1 and the electrode of the semiconductor chip 2 due to the warpage of the BGA substrate 1 or the like.

The ring 4 has a plate-like member provided with an opening at the center. The shape of the opening is determined according to the shape of the semiconductor chip 2. The shape of the heat spreader 3 is a thin plate similar to the shape of the BGA substrate 1.
Further, the semiconductor chip 2 and the heat spreader 3, B
The GA substrate 1 and the ring 4, and the heat spreader 3 and the ring 4 are bonded using an adhesive. The adhesive for bonding the semiconductor chip 2 and the heat spreader 3 is a silicone-based or epoxy-based adhesive having high heat dissipation. On the other hand, the adhesive for bonding the BGA substrate 1 and the ring 4 and the heat spreader and the ring 4 is, for example, an epoxy adhesive formed into a film.

Next, a method of manufacturing a semiconductor device will be described. 11 and 12 are process cross-sectional views showing an example of a conventional method for manufacturing a semiconductor device. 11 and 12
, The same parts as those in FIG. 10 are denoted by the same reference numerals. 5a is a first solder bump electrically connected to an electrode (not shown) included in the semiconductor chip 2;
“b” indicates a second solder bump electrically connected to one end (not shown) of the plurality of wirings provided on the BGA substrate 1. 7a is a first adhesive layer made of an adhesive bonding the BGA substrate 1 and the ring 4, and the heat spreader 3 and the ring 4, and 7b is a second adhesive layer made of an adhesive bonding the semiconductor chip 2 and the heat spreader 3.
3 shows an adhesive layer.

First, a first solder bump 5a is provided on an electrode included in a semiconductor chip 2, and a BGA substrate 1
A second solder bump 5b is provided on one end of the plurality of wirings (see FIG. 11A). Next, a flux material is applied to a region of the surface of the BGA substrate 1 where the second solder bump 5b is formed. Semiconductor chip 2 on BGA substrate 1
Is placed, and the BGA substrate 1 and the semiconductor chip 2 are put into a heat treatment furnace (a so-called reflow furnace) in a state where the first solder bumps 5a and the second solder bumps 5b are in contact with each other. As a result, the first solder bump 5a and the second
Is melted, and the first solder bump 5a and the second solder bump 5b that have been in contact with each other are integrated. In FIG. 11, the one in which the first solder bump and the second solder bump are integrated is shown as a solder bump 5. The electrodes included in the semiconductor chip 2 and a plurality of wirings of the BGA substrate 1 are electrically connected by the solder bumps 5 (see FIG. 11B). Further, after cleaning the flux material, the ring 4 is bonded to the BGA substrate 1 by the first bonding layer 7a (see FIG. 11C). Next, a sealing resin is injected into a gap between the BGA substrate 1 and the semiconductor chip 2 and then solidified to form a sealing member 8, and the semiconductor chip 2 is brought into close contact with the BGA substrate 1 via the sealing member 8. And fix it. Next, an adhesive is applied to the upper surface of the semiconductor chip 2 to provide a second adhesive layer 7b (see FIG. 12A), and an adhesive is applied to the upper surface of the ring 4 to provide a first adhesive layer 7a. After that, the heat spreader 3 is placed on the semiconductor chip 2 and the ring 4, and the heat spreader 3 is bonded to the semiconductor chip 2 and the ring 4 (see FIG. 12B). Finally, solder balls 6 are provided on the external electrodes of the semiconductor device connected to the other ends of the plurality of wirings of the BGA substrate 1 to obtain a semiconductor device (FIG. 12).
(C)).

[0008]

In a conventional semiconductor device, a BGA substrate includes a plurality of stacked insulating layers, a plurality of wirings provided on the upper surface of each of the plurality of insulating layers,
It comprises a plurality of via holes provided in the insulating layer for electrically connecting a plurality of wirings provided on different insulating layer upper surfaces. An example of a material for the insulating layer is a resin.

FIG. 13 is an explanatory sectional view showing an example of a conventional semiconductor device. 13, FIG. 11 and FIG.
The same parts as those described above are denoted by the same reference numerals. FIG. 13 shows only the BGA substrate, the semiconductor chip, the solder bumps, and the solder balls in the semiconductor device. Reference numeral 9 denotes a wiring included in the BGA substrate, and for explanation, particularly two wirings among the plurality of wirings 9 are indicated by reference numerals 9a and 9b. Further, for the sake of explanation, one solder ball of a plurality of solder bumps is shown as a solder bump connected to a power supply or a ground, particularly using reference numeral 5a, and one solder bump of the plurality of solder bumps is used as a signal line. The solder bumps connected to the wiring (not shown) are particularly indicated by reference numeral 5b.
Similarly, for the sake of clarity, one of the plurality of solder balls is designated as a solder ball connected to a power supply or a ground, particularly using reference numeral 6a, and one of the plurality of solder balls is designated as a solder ball. A solder ball connected to a wiring (not shown) as a signal line is particularly indicated by reference numeral 6b. The BGA substrate 1 is actually a multilayer structure, but in order to clearly show the wiring 9,
Shown as one layer. Note that FIG.
A build-up substrate is shown as an example of the substrate. The wiring 9a is connected to the wiring 9b via a via hole. One end of the wiring 9a is connected to a power supply or ground solder bump 5a (in the figure, the one end of the wiring 9a does not contact the solder bump 5a, but actually contacts it). The other end is in contact with the wiring 9b that connects the side surface of the via hole, and is further routed to the upper surface of the insulating layer that connects the side surface of the via hole. In addition, forming a wiring so as to be in such a state is referred to as taking over.

[0010] The build-up board is manufactured by laminating a fine wiring layer (called a build-up layer 1b) on both surfaces of a core layer 1a formed using a conventional printed wiring board technique. Since the core layer 1a has a lower wiring density than the build-up layer 1b, it is not efficient to route the wiring as a signal line, and the core layer 1a is used as a power supply plane or a ground plane. The signal lines are mainly routed in the build-up layer 1b on the semiconductor chip side, but the power supply or ground wires are connected to the wires on the surface of the core layer 1a with minimum routing. At this time, a via hole and a wiring formed for each insulating layer constituting the build-up layer are used to connect a power supply or ground solder bump to the wiring on the surface of the core layer 1a. However, there is a problem that the routing of the signal line is hindered. In addition, there is a problem in that finer wiring easily causes crosstalk noise.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a wiring structure capable of efficiently routing signal lines and having excellent electric characteristics.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a plurality of stacked insulating layers; a plurality of wirings provided on upper surfaces of the plurality of insulating layers; A BGA substrate comprising a plurality of via holes provided in an insulating layer for electrically connecting a plurality of wirings provided in the semiconductor chip, and a semiconductor chip having a plurality of electrodes respectively connected to the plurality of wirings. At least one second wiring connected to a power supply and a ground in an insulating layer of which a first wiring as a signal line of a semiconductor chip is routed on a surface of the plurality of insulating layers. At least one third wiring connected to (ground) is provided adjacent to a straight line parallel to the direction in which the first wiring is routed.

According to a second aspect of the present invention, in the semiconductor device, the insulating layer having a low wiring density among the plurality of insulating layers includes:
A second wiring and a third wiring are provided.

According to a third aspect of the present invention, in the semiconductor device, the first wiring among the plurality of wirings is surrounded by a plurality of second wirings and a third wiring.

In a semiconductor device according to a fourth aspect of the present invention, the cross section of the via hole parallel to the surface of the insulating layer has an elliptical shape.

According to a fifth aspect of the present invention, in the semiconductor device, one of the plurality of wirings is connected to another wiring through at least two via holes.

Further, in the semiconductor device according to a sixth aspect of the present invention, a mesh-like plain film made of metal is disposed on the upper surfaces of the plurality of insulating layers so as to avoid wiring and via holes.

According to a seventh aspect of the present invention, at least one multilayer capacitor is provided adjacent to the semiconductor chip.

Further, in the semiconductor device according to claim 8 of the present invention, a conductive film is provided on the upper surface of each of the plurality of insulating layers so as to avoid wiring and via holes, and a power supply or a ground is connected to the conductive film. , BGA substrate is provided with a capacitor.

According to a tenth aspect of the present invention, there is provided a semiconductor device comprising a plurality of laminated insulating layers, a plurality of wirings provided on respective upper surfaces of the plurality of insulating layers, and a plurality of different insulating layers. A semiconductor device comprising: a BGA substrate including a plurality of via holes provided in an insulating layer for electrically connecting a plurality of wirings; and a semiconductor chip having a plurality of electrodes respectively connected to the plurality of wirings. The plurality of wirings are provided radially around a semiconductor chip and do not cross each other.

[0021]

Next, embodiments of the semiconductor device according to the present invention will be described.

Embodiment 1 Embodiment 1 of the semiconductor device of the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory view showing an example of a semiconductor chip in one embodiment of the semiconductor device of the present invention. In FIG. 1, reference numeral 2 denotes a semiconductor chip, and reference numeral 5a denotes a first solder bump provided on each electrode of the semiconductor chip 2. FIG. 1 is a diagram showing the upper surface of a semiconductor chip, and FIG.
Is provided on the lower surface of the semiconductor chip 2, so that the first solder bump 5a is not actually visible.
In FIG. 1, the first solder bumps 5a are illustrated to clearly show the arrangement of the first solder bumps 5a.

In this embodiment, a power supply is connected to the outermost electrode provided along the outer periphery of the semiconductor chip. The solder bumps provided on the power supply electrode
Of the solder bump 5a. Next, a ground is connected to an electrode provided outside. The solder bump provided on the ground electrode is referred to as a second solder bump 5b. The other electrodes are used as signal electrodes. A third solder bump provided on the signal electrode
Solder bump 5c. Note that the even-numbered solder bumps from the outside of the semiconductor chip are provided in a staggered manner with respect to the odd-numbered solder bumps from the outside of the semiconductor chip.

FIG. 2 is a partially enlarged explanatory view showing one example of a BGA substrate in one embodiment of the semiconductor device of the present invention. FIG. 2 shows only a portion of the BGA substrate facing the region A in FIG. 1 during assembly. Further, B
Three layers from a semiconductor chip side among a plurality of insulating films constituting the GA substrate are shown. The three layers are shown in FIG. 2 (a), FIG. 2 (b) and FIG.
The first insulating layer, the second insulating layer, and the third insulating layer are shown in FIG. In FIG. 2, 1 _a1 is the first
_1a2 is a second insulating layer, _1a3 is a third insulating layer,
1b is a via hole formed in each insulating layer, 9a is a second wiring (hereinafter simply referred to as “power wiring”) connected to a power supply, and 9b is a third wiring (hereinafter simply referred to as “ground”) connected to the ground. Reference numerals 9c and 1c denote first wirings (hereinafter, simply referred to as "signal wirings") as signal lines of the semiconductor chip. In each wiring, a portion indicated by a black circle (hereinafter, simply referred to as a “black circle”) indicates that the wiring is
A portion connected to a wiring formed in an insulating layer above the insulating layer in which the wiring is formed is shown. On the other hand, in the portion indicated by a white circle (hereinafter simply referred to as “white circle”),
This is a place connected to a wiring formed in an insulating layer below the insulating layer in which the wiring is formed, and a place where a via hole is formed in the insulating layer. Note that a portion indicated by a black circle in the first insulating layer indicates a portion connected to an electrode of a semiconductor chip via a solder bump.

First, the wiring shown in FIG. 2A will be described. In FIG. 2A, the leftmost black circle indicates one end of the power supply wiring 9a, the leftmost black circle indicates one end of the ground wiring 9b, and the other black circles indicate one end of the signal wiring 9c. Indicates a part. The power supply line 9a is connected to a power supply line provided on the upper surface of the second insulating layer via a via hole provided on the left side of the black circle. Ground wiring 9b
Is connected to the ground wiring provided on the upper surface of the second insulating layer via a via hole formed on the right side of the black circle of the power supply wiring 9a adjacent to the power supply wiring 9a. Also, the left most signal wire 9c of the signal wiring. 9c, BG in the first insulating layer 1 _a1 top
It is routed toward the outside (left side in FIG. 2) of the A substrate. The other signal wiring 9c is connected to a signal wiring provided on the upper surface of the second insulating layer via a via hole provided on the right side of the black circle.

Next, the wiring shown in FIG. 2B will be described. First from the left among the signal wiring 9c, 2 and third signal line 9c is drawn toward the outside of the BGA substrate with a second insulating layer 1 _a2 top. Other signal wiring 9c, power supply wiring 9a and ground wiring 9b
Are connected to signal wiring, power supply wiring or ground wiring provided on the upper surface of the third insulating layer via via holes provided on the left side of the black circle of each wiring.

Next, the wiring shown in FIG. 2C will be described. Signal wiring 9c is drawn toward the outside of the BGA substrate in the third insulating layer 1 _a3 top. Power supply wiring 9a
The ground wiring 9b is connected to a power supply wiring or a ground wiring provided on the upper surface of the fourth insulating layer via a via hole provided on the right side of a black circle of each wiring.

Further, although not shown, the power supply wiring and the ground wiring are connected to wirings provided on the upper surface of a predetermined insulating layer after all the signal wirings are routed toward the outside of the BGA substrate.

In the present embodiment, the number of signal electrodes adjacent in the left-right direction is four or three, but is not limited to this. If the number is increased, it can be dealt with by increasing the number of insulating layers.

In this embodiment, of the plurality of insulating layers, the power supply wiring and the ground wiring are arranged on a straight line parallel to the direction in which the signal wiring is routed in the insulating layer in which the signal wiring is routed on the surface. Since they are arranged adjacent to each other, a region where a signal wiring can be provided can be widened, and a wider signal wiring (or more signal wirings on one insulating layer) can be formed. In addition, since the power supply wiring and the ground wiring are routed in an insulating layer below the insulating layer in which the signal wiring is routed, the power wiring and the ground wiring can be provided in an insulating layer with low wiring density. Therefore, the widths of the power supply wiring and the ground wiring can be increased.

Embodiment 2 FIG. Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings.

In the present embodiment, the case where two or more wirings constitute one set of wirings and the one set of wirings are provided between the same two electrodes will be described. FIG. 3 is an explanatory diagram showing an example of a BGA substrate according to still another embodiment of the semiconductor device of the present invention. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals. FIG. 3 is a diagram showing the upper surface of the semiconductor chip. Since the first solder bumps 5a are provided on the lower surface of the semiconductor chip 2, the first solder bumps 5a are not actually visible. FIG. 3 illustrates the first solder bump 5a in order to clearly show the arrangement of the first solder bump 5a.

In the present embodiment, the plurality of first solder bumps 5a are arranged in a matrix at the periphery of the semiconductor chip. Among the plurality of first solder bumps 5a, the first solder bump 5a provided on the outermost side along the outer periphery of the semiconductor chip.
Is used as a solder bump provided on an electrode connected to a power supply, and a first solder bump 5a provided on the outside is used as a solder bump provided on an electrode connected to ground, and the other solder bumps are used. One solder bump 5a is a solder bump provided on the signal electrode.

FIG. 4 is a partially enlarged explanatory view showing an example of a BGA substrate according to still another embodiment of the semiconductor device of the present invention. 4, the same parts as those in FIG. 2 are denoted by the same reference numerals. FIG. 4 shows only a portion of the BGA substrate facing the region B in FIG. 3 during assembly. Further, three layers from the semiconductor chip side among a plurality of insulating films constituting the BGA substrate are shown. The three layers are respectively shown in FIG. 4A, FIG.
As shown in FIG. 4B and FIG. 4C, a first insulating layer, a second insulating layer, and a third insulating layer are provided, respectively.

First, the wiring shown in FIG. 4A will be described. In FIG. 4A, the leftmost black circle indicates one end of the power supply wiring 9a, the leftmost black circle indicates one end of the ground wiring 9b, and the other black circles indicate one end of the signal wiring 9c. Indicates a part. The power supply wiring 9a is a set of two power supply wirings 9a that are vertically adjacent to each other on the paper. The power supply wiring 9a is adjacent to each pair in the left and right direction.
Through two via holes, it is connected to a power supply wiring provided on the upper surface of the second insulating layer. The ground wiring 9b is a set of two ground wirings 9b adjacent vertically. The ground wiring 9b is connected to a power wiring provided on the upper surface of the second insulating layer via two via holes adjacent to each other in each pair in the left-right direction. Also, the left most signal wire 9c of the signal wiring 9c is drawn toward the outside of the BGA substrate with a first insulating layer 1 _a1 upper surface (the left side in FIG. 4). The other signal wiring 9c is connected to a signal wiring provided on the upper surface of the second insulating layer via a via hole provided on the left side of the black circle.

Next, the wiring shown in FIG. 4B will be described. 3 from the left of the signal wiring 9c
The signal wirings 9c up to the Nth are located on the upper surface of the second insulating layer _1a2.
It is routed toward the outside of the GA substrate. The other signal lines 9c are connected to signal lines provided on the upper surface of the third insulating layer via via holes provided on the left side of the black circles of the respective lines. The power supply wiring 9a is connected to the third via via holes provided on the left side of two black circles for each set.
Is connected to the power supply wiring provided on the upper surface of the insulating layer. Further, the ground wiring 9b is connected to a ground wiring provided on the upper surface of the third insulating layer via two via holes provided on the right side of two black circles for each set.

Next, the wiring shown in FIG. 4C will be described. Signal wiring 9c is drawn toward the outside of the BGA substrate in the third insulating layer 1 _a3 top. Power supply wiring 9a
Are connected to power supply wiring provided on the upper surface of the fourth insulating layer via two via holes provided on the right side of two black circles for each set. The ground wiring 9b is connected to the ground wiring provided on the upper surface of the fourth insulating layer via two via holes provided on the left side of two black circles for each set.

Further, although not shown, the power supply wiring and the ground wiring are connected to the wiring provided on the upper surface of a predetermined insulating layer after all the signal wirings are routed toward the outside of the BGA substrate.

In the present embodiment, the number of signal electrodes adjacent in the left-right direction is seven, but the number is not limited to seven. If the number is increased, it can be dealt with by increasing the number of insulating layers.

In this embodiment, in the insulating layer of the plurality of insulating layers where the signal wiring is routed on the surface, one set of power supply wiring and one set of ground wiring are arranged in the direction in which the signal wiring is routed. Are arranged adjacent to each other on a straight line parallel to the line, so that the area where the signal wiring can be provided can be wider than in the case of the first embodiment, and the wider signal wiring (or 1
More signal wirings) can be formed on one insulating layer. Further, since the power supply wiring and the ground wiring are connected to the wiring provided on the upper surface of the insulating layer below the insulating layer from which the signal wiring is routed, it is possible to provide the power wiring and the ground wiring on the insulating layer with low wiring density. it can.

Embodiment 3 Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is an explanatory view showing a part of a plurality of wirings in a BGA substrate according to still another embodiment of the semiconductor device of the present invention. FIG. 5A is an explanatory cross-sectional view showing a plurality of wirings formed on the upper surface of three insulating layers (not shown). FIG. 5B is an explanatory diagram showing a plurality of wirings viewed from the direction indicated by the arrow C in FIG. FIG.
(B) shows a plurality of wirings formed on the upper surface of the second insulating layer from the top among the three insulating layers. In FIG. 5, 9
_a1 is a power supply wiring formed on the upper surface of the first insulating layer from above, 9 _a2 is a power supply wiring formed on the upper surface of the second insulating layer from above, and 9 _a3 is formed on the upper surface of the third insulating layer from above. Reference numeral 9c denotes a signal wiring formed on the upper surface of the second insulating layer from the top. In FIG. 5 (b), the area indicated by D is a portion for connecting the upper one of the power supply wiring 9 _a2 3-th to the power supply line 9 _a3 formed in the insulating layer upper surface through a via hole, represented by E region is a portion to be connected to the power supply line 9 _a1 from upper one is formed in the first insulating layer upper surface of the power supply wiring 9 _a2 through the via hole.

As shown in FIG. 5, the signal wiring 9c is
It is surrounded by power supply wiring _9a1 , power supply wiring _9a2 and power supply wiring _9a3 . Therefore, it is possible to prevent noise from occurring in an electric signal input to one signal wiring due to an influence of an electric signal input to another signal wiring adjacent to the one signal wiring. The same effect can be obtained by using a ground line instead of the power line, and the same effect can be obtained by surrounding the signal line with the power line and the ground line.

Embodiment 4 Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to the drawings.

In the present embodiment, another example of a place where one wiring is connected to another wiring will be described. FIG. 6 is an explanatory view showing a part of a plurality of wirings in a BGA substrate according to still another embodiment of the semiconductor device of the present invention. FIG. 6A and FIG. 6C are cross-sectional explanatory diagrams showing wirings formed on the upper surfaces of three insulating layers (not shown). FIG. 6B is an explanatory diagram showing the wiring viewed from the direction indicated by the arrow F in FIG. FIG. 6 (d)
FIG. 7 is an explanatory diagram showing wiring viewed from a direction indicated by an arrow G in FIG. FIGS. 6B and 6D show wirings formed on the upper surface of the second insulating layer from the top among the three insulating layers. In FIG. 6, 9 ₁ is ₁ from the top.
Th insulating layer formed on the upper surface wiring, 9 ₂ wiring formed on the second insulating layer upper surface from above, 9 ₃ denotes a wiring formed in the third insulating layer top surface from above.

First, the wiring shown in FIGS. 6A and 6B will be described. 6 (a) and 6 (b)
As shown in, the second insulating layer upper surface to the formed wire 9 ₂ from above is formed on the third insulating layer upper surface from the first insulating layer formed on the upper surface wiring 9 ₁ and above the top the wiring 9 ₃ is coupled via two via holes. Therefore, the two wirings can be connected with a larger area, so that the inductance generated in the wiring at the connection portion can be reduced.

Next, the wiring shown in FIGS. 6C and 6D will be described. FIG. 6C and FIG.
As shown in (d), 2 th insulating layer wiring 9 ₂ formed on the upper surface from the top, the third insulating layer upper surface from the first insulating layer formed on the upper surface wiring 9 ₁ and above the top the wiring 9 ₃ formed, in each cross-sectional shape oval (herein, oval and circle divided by the diameter, the category includes a circle connecting the semicircular each other with a straight line of the same length )
Are connected via a via hole. Therefore, 2
The two wirings can be connected in a wider area, and the inductance generated in the wiring at the connection portion can be reduced.

Note that the connection portion of the wiring of the semiconductor device described in Embodiment 3 may be formed like the connection portion of the wiring of the semiconductor device described in Embodiment 3.

Embodiment 5 Next, a semiconductor device according to a fifth embodiment of the present invention will be described with reference to the drawings.

In the present embodiment, a mesh-like plain film is provided on the upper surface of the insulating layer constituting the BGA substrate, avoiding the wiring and the via hole. The mesh-like plain film is made of metal. The plane film is formed in a mesh shape by providing a plurality of openings in the metal film. FIG.
FIG. 11 is an explanatory view showing an example of a plane film provided on an upper surface of an insulating layer in still another embodiment of the semiconductor device of the present invention. In FIG. 7, reference numeral 10 denotes a plane film. The region H is a region below and around the semiconductor chip.

In a portion corresponding to the region H of the BGA substrate, the number of wirings to be formed is large, so that it is necessary to reduce the width of the wiring. In other regions, the width of the wiring can be increased. However, when the width of the wiring changes depending on the region, the characteristic impedance of the wiring changes depending on the region, and the waveform of the electric signal changes. In the present embodiment, the plane film 10 in which the density of the opening 10a is changed depending on the region is provided on the surface of the insulating layer. Therefore, it is possible to cancel the change in the characteristic impedance of the wiring, which changes depending on the width of the wiring.

Embodiment 6 FIG. Next, a sixth embodiment of the semiconductor device of the present invention will be described with reference to the drawings.

In this embodiment, at least one multilayer capacitor is provided on the upper surface of the BGA substrate so as to be adjacent to the semiconductor chip. FIG. 8 is a partial cross-sectional explanatory view showing Embodiment 6 of the semiconductor device of the present invention. 8, the same parts as those in FIG. 13 are indicated by the same reference numerals. Further, reference numeral 11 denotes a multilayer capacitor.

As shown in FIG. 8, the multilayer capacitor 11 is disposed on the upper surface of the BGA substrate 1 so as to be adjacent to the semiconductor chip 2.
Is provided, it is possible to prevent noise from occurring in the power supply and ground potentials connected to the semiconductor device.

A similar effect can be obtained by forming a film made of a conductor (hereinafter simply referred to as a "conductor film") in a region of the surface of the insulating layer where no wiring or via hole is formed. A power supply voltage (Vdd) or a ground voltage (Vss) is alternately supplied to each conductor film in a direction perpendicular to the surface of the insulating layer.

Embodiment 7 FIG. Next, a semiconductor device according to a seventh embodiment of the present invention will be described with reference to the drawings.

In the present embodiment, of the wirings formed in the BGA substrate, the wirings provided between two via holes are provided radially around the semiconductor chip. FIG. 9 is an explanatory diagram illustrating an example of an insulating layer according to the seventh embodiment of the semiconductor device of the present invention. In FIG. 9, 1
a indicates one of the plurality of insulating layers constituting the BGA substrate, and 9 indicates a wiring provided on the insulating layer 1a.

As shown in the figure, wirings provided between two via holes (located at positions indicated by white circles in the figure) are provided radially as indicated by arrow I.

In the present embodiment, the wiring 9 is provided radially around the semiconductor chip between the two via holes. Therefore, the distance between the wirings can be widened and the wirings can be formed so as not to cross each other. As a result, crosstalk noise generated between the wirings can be reduced.

Although the present invention has been described using a semiconductor device that does not include a heat spreader and a ring as an example of a semiconductor device, the same effect can be obtained even when the semiconductor device is a semiconductor device that includes a heat spreader and a ring. available.

[0062]

According to the first aspect of the present invention, there is provided a semiconductor device comprising:
A plurality of stacked insulating layers, a plurality of wirings provided on the top surface of each of the plurality of insulating layers, and a plurality of wirings provided on the top surface of different insulating layers are provided on the insulating layer to electrically connect the plurality of wirings. A BGA substrate comprising a plurality of via holes,
A semiconductor chip having a plurality of electrodes respectively connected to the plurality of wirings, wherein a first wiring as a signal line of the semiconductor chip among the plurality of insulating layers is routed on a surface. In the insulating layer to be formed, at least one second wiring connected to the power supply and at least one third wiring connected to the ground are adjacent on a straight line parallel to the direction in which the first wiring is routed. Therefore, the area where the signal wiring can be provided can be widened, and a wider signal wiring can be formed.

In the semiconductor device according to the second aspect of the present invention, the insulating layer having a low wiring density among the plurality of insulating layers may include:
Since the second wiring and the third wiring are provided, the width of the power wiring and the ground wiring can be increased.

Further, in the semiconductor device according to the third aspect of the present invention, the first wiring of the plurality of wirings is surrounded by the plurality of second wirings and the third wiring, so that the signal wiring Noise can be prevented from being generated in the electric signal input to the input terminal.

In the semiconductor device according to the fourth aspect of the present invention, since the cross-sectional shape of the via hole parallel to the surface of the insulating layer is oval, it is possible to reduce the inductance generated in the wiring at the connection portion. it can.

In the semiconductor device according to a fifth aspect of the present invention, one of the plurality of wirings is connected to another wiring through at least two via holes. The inductance generated in the wiring in the portion can be reduced.

In a semiconductor device according to a sixth aspect of the present invention, a mesh-like plain film made of metal is disposed on the upper surfaces of the plurality of insulating layers so as to avoid wiring and via holes. Of the characteristic impedance of the wiring, which changes depending on the width of the wiring.

In the semiconductor device according to a seventh aspect of the present invention, at least one multilayer capacitor is provided so as to be adjacent to the semiconductor chip. It can be prevented from dropping before being supplied to the chip.

In a semiconductor device according to an eighth aspect of the present invention, a conductive film is provided on an upper surface of each of the plurality of insulating layers so as to avoid wiring and via holes, and a power supply or a ground is connected to the conductive film. Since the capacitor is provided in the BGA substrate, it is possible to prevent the voltage of the power supply connected to the semiconductor device from dropping before being supplied to the semiconductor chip.

In the semiconductor device according to the ninth aspect of the present invention, a plurality of laminated insulating layers, a plurality of wirings provided on the upper surfaces of the plurality of insulating layers, and a different insulating layer are provided on the upper surfaces. A semiconductor device comprising: a BGA substrate including a plurality of via holes provided in an insulating layer for electrically connecting a plurality of wirings; and a semiconductor chip having a plurality of electrodes respectively connected to the plurality of wirings. Since the plurality of wirings are provided radially around the semiconductor chip and do not cross each other, crosstalk noise generated between the wirings can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating an example of a semiconductor chip in one embodiment of a semiconductor device of the present invention.

FIG. 2 is a partially enlarged explanatory view showing an example of a BGA substrate in one embodiment of the semiconductor device of the present invention.

FIG. 3 is an explanatory view showing an example of a BGA substrate in still another embodiment of the semiconductor device of the present invention.

FIG. 4 is a partially enlarged explanatory view showing an example of a BGA substrate according to still another embodiment of the semiconductor device of the present invention.

FIG. 5 is an explanatory view showing a part of a plurality of wirings in a BGA substrate in still another embodiment of the semiconductor device of the present invention.

FIG. 6 is an explanatory view showing a part of a plurality of wirings in a BGA substrate in still another embodiment of the semiconductor device of the present invention.

FIG. 7 is an explanatory view showing an example of a plane film provided on an upper surface of an insulating layer in still another embodiment of the semiconductor device of the present invention.

FIG. 8 is a partial cross-sectional explanatory view showing still another embodiment of the semiconductor device of the present invention.

FIG. 9 is an explanatory diagram showing an example of an insulating layer in still another embodiment of the semiconductor device of the present invention.

FIG. 10 is a partially cutaway perspective view showing an example of a conventional semiconductor device.

FIG. 11 is a process cross-sectional view illustrating an example of a conventional method for manufacturing a semiconductor device.

FIG. 12 is a process cross-sectional view showing an example of a conventional method for manufacturing a semiconductor device.

FIG. 13 is an explanatory sectional view showing an example of a conventional semiconductor device.

[Explanation of symbols]

1 BGA substrate, 2 semiconductor chip, 3 heat spreader, 4 ring, 5 solder bump, 6 solder ball, 8 sealing member, 9 wiring, 10 plane film, 1
1 Multilayer capacitors.

Claims (9)

[Claims] 1. An insulating layer for electrically connecting a plurality of stacked insulating layers, a plurality of wirings provided on upper surfaces of the plurality of insulating layers, and a plurality of wirings provided on upper surfaces of different insulating layers. A semiconductor device comprising: a BGA substrate including a plurality of via holes provided in a layer; and a semiconductor chip having a plurality of electrodes connected to the plurality of wirings, respectively, wherein the semiconductor chip includes a plurality of insulating layers. In an insulating layer in which a first wiring as a signal line is routed on the surface, at least one second wiring connected to the power supply and at least one third wiring connected to the ground are the first wirings. A semiconductor device disposed adjacent to and on a straight line parallel to a direction in which wiring is routed. 2. The semiconductor device according to claim 1, wherein a second wiring and a third wiring are provided on an insulating layer having a low wiring density among the plurality of insulating layers. 3. The semiconductor device according to claim 1, wherein a first wiring of said plurality of wirings is surrounded by a plurality of second wirings and a plurality of third wirings. 4. The semiconductor device according to claim 1, wherein a cross section of the via hole parallel to the surface of the insulating layer has an elliptical shape. 5. The semiconductor device according to claim 1, wherein one of the plurality of wirings is connected to another wiring through at least two via holes. 6. The semiconductor device according to claim 1, wherein a mesh-like plain film made of metal is disposed on the upper surfaces of the plurality of insulating layers so as to avoid wiring and via holes. 7. The semiconductor device according to claim 1, wherein at least one multilayer capacitor is provided adjacent to said semiconductor chip. 8. A conductive film is provided on an upper surface of each of the plurality of insulating layers so as to avoid wiring and via holes, a power supply or a ground is connected to the conductive film, and a capacitor is provided in a BGA substrate. 13. The semiconductor device according to claim 1. 9. An insulating layer for electrically connecting a plurality of stacked insulating layers, a plurality of wirings provided on respective upper surfaces of the plurality of insulating layers, and a plurality of wirings provided on upper surfaces of different insulating layers. A semiconductor device comprising: a BGA substrate including a plurality of via holes provided in a layer; and a semiconductor chip having a plurality of electrodes respectively connected to the plurality of wirings, wherein a wiring provided between the two via holes is provided. ,
A semiconductor device provided radially around a semiconductor chip and not intersecting with each other.