WO2002023203A1 - Prise de vérification pour dispositifs électroniques - Google Patents

Prise de vérification pour dispositifs électroniques Download PDF

Info

Publication number
WO2002023203A1
WO2002023203A1 PCT/US2001/041451 US0141451W WO0223203A1 WO 2002023203 A1 WO2002023203 A1 WO 2002023203A1 US 0141451 W US0141451 W US 0141451W WO 0223203 A1 WO0223203 A1 WO 0223203A1
Authority
WO
WIPO (PCT)
Prior art keywords
test socket
lcc
cavity
test
electronic device
Prior art date
Application number
PCT/US2001/041451
Other languages
English (en)
Inventor
Mark S. Lewis
Simon Wood
Ron Burke
Original Assignee
Raytheon Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Company filed Critical Raytheon Company
Publication of WO2002023203A1 publication Critical patent/WO2002023203A1/fr

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433Sockets for IC's or transistors
    • G01R1/0441Details
    • G01R1/0466Details concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding

Abstract

L'invention concerne une prise de vérification pour dispositifs électroniques, laquelle comprend un plancher, un certain nombre de parois se dressant à partir de ce plancher et définissant une cavité surdimensionnée qui sépare lesdites parois, de sorte que les ébarbures formées sur le dispositif tiennent à l'intérieur de la cavité surdimensionnée, et un certain nombre de touches d'emboîtement qui font saillie à partir d'une paroi vers l'intérieur de façon qu'elles se logent dans des entailles du dispositif afin d'emboîter ce dernier avec la cavité surdimensionnée.
PCT/US2001/041451 2000-09-14 2001-07-27 Prise de vérification pour dispositifs électroniques WO2002023203A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66188600A 2000-09-14 2000-09-14
US09/661,886 2000-09-14

Publications (1)

Publication Number Publication Date
WO2002023203A1 true WO2002023203A1 (fr) 2002-03-21

Family

ID=24655507

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/041451 WO2002023203A1 (fr) 2000-09-14 2001-07-27 Prise de vérification pour dispositifs électroniques

Country Status (1)

Country Link
WO (1) WO2002023203A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009067238A1 (fr) * 2007-11-25 2009-05-28 Advanced Micro Devices, Inc. Connecteur de boîtier à multiples dimensions
CN111834817A (zh) * 2019-04-18 2020-10-27 泰克元有限公司 电子部件测试用分选机的插入件

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5221209A (en) * 1991-08-22 1993-06-22 Augat Inc. Modular pad array interface
DE19513275A1 (de) * 1994-06-27 1996-01-11 Hewlett Packard Co Sondenadapter zum Testen von IC-Bausteinen
US6002266A (en) * 1995-05-23 1999-12-14 Digital Equipment Corporation Socket including centrally distributed test tips for testing unpackaged singulated die

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5221209A (en) * 1991-08-22 1993-06-22 Augat Inc. Modular pad array interface
DE19513275A1 (de) * 1994-06-27 1996-01-11 Hewlett Packard Co Sondenadapter zum Testen von IC-Bausteinen
US6002266A (en) * 1995-05-23 1999-12-14 Digital Equipment Corporation Socket including centrally distributed test tips for testing unpackaged singulated die

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009067238A1 (fr) * 2007-11-25 2009-05-28 Advanced Micro Devices, Inc. Connecteur de boîtier à multiples dimensions
GB2467473A (en) * 2007-11-25 2010-08-04 Global Foundries Inc Multiple size package socket
US7955892B2 (en) 2007-11-25 2011-06-07 Globalfoundries Inc. Multiple size package socket
KR101193230B1 (ko) * 2007-11-25 2012-10-19 글로벌파운드리즈 인크. 다중 사이즈 패키지 소켓
CN101919321B (zh) * 2007-11-25 2013-06-05 格罗方德半导体公司 多尺寸封装件插座
CN111834817A (zh) * 2019-04-18 2020-10-27 泰克元有限公司 电子部件测试用分选机的插入件

Similar Documents

Publication Publication Date Title
US6449156B1 (en) Heat sink provided with coupling means, memory module attached with the heat sink and manufacturing method thereof
US5378981A (en) Method for testing a semiconductor device on a universal test circuit substrate
US6407566B1 (en) Test module for multi-chip module simulation testing of integrated circuit packages
US5315241A (en) Method for testing integrated circuits
KR100661254B1 (ko) 반도체 검사용 프로브 카드
KR100393316B1 (ko) 반도체디바이스시험장치
TW202202851A (zh) 垂直型探針以及具備其的探針卡
US6091079A (en) Semiconductor wafer
JPH0777556A (ja) テストソケット及びそれを用いたkgdの製造方法
US20010026152A1 (en) Semiconductor package testing equipment including loader having package guider and method of loading a semiconductor package onto a test socket as aligned therewith
JP2010530973A (ja) パッケージ化された半導体デバイスを試験するよう構成された高温セラミックソケット
JPH0955399A (ja) 半導体パッケージ及びその実装方法
US5414372A (en) Reusable test apparatus for integrated circuit chips
US6595794B2 (en) Electrical contact method and apparatus in semiconductor device inspection equipment
EP0305951A1 (fr) Contrôle de circuits intégrés sur une plaque de circuit intégré pourvue de composants
US6876216B2 (en) Integrated circuit probe card
WO1999054932A1 (fr) Boitier sans conducteur, a barrettes
WO2002023203A1 (fr) Prise de vérification pour dispositifs électroniques
EP1081757B1 (fr) Procédé d'empaquetage d'un module multipuce avec déverminage en vue de l'obtention de puces reconnues bonnes ("known good die")
KR950013605B1 (ko) 번인 테스트용 칩 홀딩장치 및 그 제조방법
US20110156740A1 (en) Probe card
US6182829B1 (en) I.C. carrier insert
US5455518A (en) Test apparatus for integrated circuit die
WO2007023884A1 (fr) Plaque de guidage pour carte de controle et son procede de traitement
KR0182506B1 (ko) 동시에 절단된 반도체 칩을 이용한 고밀도 실장형 패키지 및 그 제조 방법

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP