Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/80—FETs having rectifying junction gate electrodes
  • H10D30/801—FETs having heterojunction gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
  • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
  • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Definitions

• the present invention pertains to low power and high speed integrated circuits in the compound semiconductor field utilizing field effect transistors and more specifically complementary field effect transistors used in concert including enhancement mode self- aligned metal-oxide-compound semiconductor transistors and depletion mode self-aligned metal-oxide-compound semiconductor transistors and methods of materials growth and fabrication of said structures and the ultra large scale integration of said transistors.
• the gallium arsenide and indium phosphide integrated circuit industry has been limited without a technology that simultaneously allows the integration of complementary field effect transistor devices and transistors with low gate leakage currents.
• CMOS complementary metal oxide semiconductor
• FETs Field effect transistor
• III-V semiconductor industry employ metal gates and Schottky gate contacts that are have quiescent-state leakage currents exceeding many microamps.
• the use of metal gates in compound semiconductor technology further results in individual transistors and integrated circuits that have excessively high power dissipation, reduced transconductance, reduced logic swing and the inability to operate on a single power supply, and generally limited performance characteristics.
• CMOS complementary metal-oxide-semiconductor
• FIG. 1 is simplified cross sectional view of a self-aligned enhancement mode compound semiconductor MOSFET in accordance with a preferred embodiment of the present invention
• FIG. 2 is a simplified flow chart illustrating a method of manufacturing a self-aligned enhancement mode compound semiconductor MOSFET in accordance with a preferred embodiment of the present invention.
• the exemplification set out herein illustrates a preferred embodiment of the invention in one form thereof, and such exemplification is not intended to be construed as limiting in any manner.
• the present invention provides, among other things, a self-aligned enhancement mode metal-oxide-compound semiconductor FET.
• the FET includes a gallium oxygen insulating structure that is composed of at least two distinct layers.
• the first layer is most preferably more that 10 angstroms thick but less that 25 angstroms in thickness and composed substantially of gallium oxygen compounds including but not limited to stoichiometric Ga 2 O 3 and Ga 2 O, and possibly a lesser fraction of other gallium oxygen compounds.
• the upper insulating layer in the gallium oxide insulating structure is composed of an insulator that does not intermix with the underlying gallium oxygen insulating structure.
• This upper layer must possess excellent insulating qualities, and is most typically composed of gallium oxygen and a third rare earth element that together form a ternary insulating material. Therefore the entire gallium oxide rare earth gate insulator structure is composed of at least two layers and may contain a third intermediate graded layers that consists of a mixture of the upper insulating material and the gallium oxygen compounds that compose the initial layer. Together the initial gallium oxygen layer, any intermediate graded layer and the top insulating region form both a gallium oxide insulating structure and the gate insulator region of a metal-oxide- compound semiconductor field effect transistor.
• the initial substantially gallium oxygen layer forms an atomically abrupt interface with the top layer of the compound semiconductor wafer structure, and does not introduce midgap surface states into the compound semiconductor material.
• a refractory metal gate electrode is preferably positioned on the upper surface of the gate insulator structure layer.
• the refractory metal is stable on the gate insulator structure layer at elevated temperature.
• Self-aligned source and drain areas, and source and drain contacts are positioned on the source and drain areas.
• the metal-oxide-compound semiconductor transistor includes multilayer gate insulator structure including an initial gallium oxygen layer, intermediate transition layer, and upper insulating layer of 30-250 angstroms in thickness positioned on upper surface of a compound semiconductor heterostructure that form the gate insulator structure.
• the preferred embodiment also comprises a compound semiconductor heterostructure including a GaAs, Al x Ga ⁇ -x As and In y Ga ⁇ -y As layers with or wothout n-type and/or p-type charge supplying layers which are grown on a compound semiconductor substrate, a refractory metal gate of W, WN, or WSi, self aligned donor (n-channel FET) or acceptor (p- channel FET) implants, and source and drain ohmic contacts.
• the compound semiconductor heterostructure comprises an friyGaj.
• y As, ALIn ⁇ x As, and InP compound semiconductor heterostructure and n-type and/or p-type charge supplying layers which are grown on an InP substrate, and a refractory metal gate of W, WN, or WSi, self aligned donor (n-channel FET) or acceptor (p-channel FET) implants, and source and drain ohmic contacts.
• FIG. 1 is simplified cross sectional view of a self-aligned enhancement mode compound semiconductor MOSFET in accordance with a preferred embodiment of the present invention.
• Device 10 includes a compound semiconductor material, such as any III-V material employed in any semiconductor device, represented herein by a III-V semiconductor substrate 11 and a compound semiconductor epitaxial layer structure 12.
• a compound semiconductor wafer structure which in FIG. 1 is designated 13.
• Methods of fabricating semiconductor wafer structure 13 include, but are not limited to, molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD).
• Device H) further comprises a gate insulator structures (30) that includes at least two or more layers.
• the first layer of the gate insulator structure (31) is composed entirely of gallium oxide compounds and is directly adjacent to and deposited upon the compound semiconductor structure.
• the second layer of the gate insulator structure (32) is composed of a compound of gallium, oxygen, and one or more rare earth elements from the periodic table.
• the initial gallium oxygen layer (31) forms an atomically abrupt interface 14 with the upper surface of top layer 15, the top layer of the compound semiconductor structure.
• a refractory metal gate electrode 17 which is stable in the presence of top insulating material at elevated temperature is positioned on upper surface 18 of the gate insulator structure.
• Dielectric spacers 26 are positioned to cover the sidewalls of metal gate electrode 17.
• Source and drain contacts 19 and 20 are deposited on self-aligned source and drain areas 21 and 22, respectively.
• the compound semiconductor epitaxial layer structure consists of a ⁇ 11 angstrom GaAs top layer (15), a ⁇ 101 angstrom Al x Ga 1-x As spacer layer (23), a ⁇ 251 angstrom In y Ga 1-y As channel layer (24), and a GaAs buffer layer (25) grown on a GaAs substrate (11).
• Top GaAs layer (15) is used to form an atomically abrupt layer with the gate insulator structure with an abrupt interface with low defect density.
• a III-V compound semiconductor wafer structure 13 with an atomically ordered and chemically clean upper surface of top layer 15 is prepared in an ultra-high vacuum semiconductor growth chamber and transferred via a ultra high vacuum transfer chamber to a second ultra high vacuum oxide and insulator deposition chamber.
• the initial gallium oxygen layer (31) is deposited on upper compound semiconductor surface layer 15 using thermal evaporation from a high purity Ga 2 O 3 source or from crystalline gadolinium gallium garnet, Ga 3 Gd 5 O ⁇ 2 .
• This initial gallium oxygen layer is deposited while holding the substrate temperature of the compound semiconductor structure at ⁇ 580°C, and most preferably at a substrate temperature ⁇ 495°C.
• deposition of the second insulator layer is initiated.
• the deposition of the -second insulator layer starts by directing the flux from a low power oxygen plasma source into the ultra high vacuum system such that the oxygen plasma effluent and species are largely directed toward and impinging upon said compound semiconductor structure with initial gallium oxygen layer.
• the flux from the oxygen plasma source should be directed at the surface for between 2-5 seconds, subsequently followed by the co-evaporation of gallium oxygen compounds from Ga 2 O 3 and a second thermal evaporation source that contains a rare-earth element.
• the flux beams from the oxygen source, Ga 2 O 3 and rare-earth evaporation source thermal evaporation sources are carefully balanced to provide a ternary insulator layer on top of the initial gallium oxygen layer on said compound semiconductor structure.
• the substrate temperature is simultaneously adjusted to provide an optimized substrate temperature for the deposition of this layer.
• the substrate temperature required to deposit the gallium+oxygen+rare earth layer is ⁇ 530°C.
• this second insulator layer proceeds until the total insulator thickness of 200-250 angstroms is achieved.
• Shutters and valves are utilized to stop the deposition of the ternary gallium+oxygen+rare earth layer upon the deposition of the required thickness of the insulator layer.
• the substrate temperature is cooled in-vacuum to approximately 200°C, and the deposition of a refractory metal which is stable and does not interdiffuse with on the top layer of the gate insulator structure at elevated temperature such as WSi or WN is deposited on upper surface 18 of oxide layer 32 and subsequently patterned using standard lithography.
• the refractory metal layer is etched until oxide layer 31 is exposed using a refractory metal etching technique such as a fluorine based dry etching process.
• the refractory metal etching procedure does not etch the oxide layer 31, thus, oxide layer 31 functions as an etch stop layer such that upper surface of top layer 15 remains protected by oxide layer 31. All processing steps are performed using low damage plasma processing.
• Self-aligned source and drain areas 21 and 22, respectively are realized by ion implantation of Si (n-channel device) and Be/F or C/F (p-channel device) using the refractory metal gate electrode 17 and the dielectric spacers 26 as implantation masks.
• Such ion implantation schemes are compatible with standard processing of complementary compound semiconductor heterostructure FET technologies and are well known to those skilled in the art.
• the implants are activated at 700-900°C using rapid thermal annealing in an ultra high vacuum environment such that degradation of the interface 16 established between top layer 15 and oxide layer 31 is completely excluded.
• ohmic source and drain contacts 19 and 20 are deposited on the self-aligned source and drain areas 21 and 22, respectively.
• the devices may then be interconnected using the standard methods to those skilled in the art of integrated microelectronics and integrated circuit manufacture.
• FIG. 2 is a simplified flow chart illustrating a method of manufacturing a self-aligned enhancement mode compound semiconductor MOSFET in accordance with a preferred embodiment of the present invention.
• a compound semiconductor wafer structure is produced using standard epitaxial growth methods in the art.
• a layer consisting of gallium oxygen compounds including but not limited to Ga 2 O 3 and Ga 2 O is deposited on upper surface of said compound semiconductor wafer structure.
• an insulating layer of gallium oxygen and one or more rare earth elements is deposited on the upper surface of the initial gallium oxygen compound layer.
• the gallium oxide gate insulator structure is formed in steps 104 and 105.
• a stable refractory gate metal is positioned on upper surface of said gate insulator structure.
• source and drain ion implants are provided self-aligned to the gate electrode.
• source and drain ohmic contacts are positioned on ion implanted source and drain areas.
• step 100 provides a compound semiconductor substrate such as GaAs or InP.
• Step 102 includes the preparation and epitaxial growth of an atomically ordered and chemically clean upper surface of the compound semiconductor wafer structure.
• Step 103 preferably comprises thermal evaporation from a purified and crystalline gadolinium gallium garnet or Ga 2 O 3 source on an atomically ordered and chemically clean upper surface of the compound semiconductor wafer structure.
• Step 104 comprises the formation of a gallium+oxygen+rare earth elemental insulating layer formed through the simultaneous vacuum evaporation of gallium oxygen species and at least one rare earth element such as Gadolinium with the simultaneous oxidation using the effluent of an oxygen gas plasma source directed in simultaneous combination with other thermal evaporation sources toward substrate 100.
• the initial gallium oxygen compound layer of the gate insulator structure preferably functions as an etch stop layer such that the upper surface of the compound semiconductor wafer structure remains protected by the gate oxide during and after gate metal etching.
• the refractory gate metal desirably does not react with or diffuse into the gate oxide layer during high temperature annealing of the self-aligned source and drain ion implants.
• the quality of the interface formed by the gate oxide layer and the upper surface of the compound semiconductor structure is desirably preserved during high temperature annealing of the self-aligned source and drain ion implants.
• the self-aligned source and drain implants are desirably annealed at approximately 700°C in an ultra high vacuum environment.
• the self-aligned source and drain implants are desirably realized by positioning dielectric spacers on the sidewalls of the refractory gate metal.
• new and improved compound semiconductor devices and methods of fabrication are disclosed.
• the new and improved self-aligned enhancement mode metal- oxide-compound semiconductor heterostructure field effect transistors enable stable and reliable device operation, provide optimum compound semiconductor device performance for low power/high performance complementary circuits and architectures, keep interconnection delay in ULSI under control, and provide optimum efficiency and output power for RF and microwave applications as well as for digital integrated circuits that require very high integration densities.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Thin Film Transistor (AREA)
• Formation Of Insulating Films (AREA)

Priority Applications (4)

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Publications (2)

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• 2001
  • 2001-08-10 AU AU2001288239A patent/AU2001288239A1/en not_active Abandoned
  • 2001-08-10 KR KR10-2003-7001947A patent/KR20030027017A/ko not_active Ceased
  • 2001-08-10 WO PCT/US2001/025150 patent/WO2002015233A2/en not_active Ceased
  • 2001-08-10 EP EP01967960A patent/EP1312122A4/en not_active Withdrawn
  • 2001-08-10 JP JP2002520272A patent/JP2004507081A/ja active Pending

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