WO2002013262A2 - Gate technology for strained surface channel and strained buried channel mosfet devices - Google Patents

Gate technology for strained surface channel and strained buried channel mosfet devices Download PDF

Info

Publication number
WO2002013262A2
WO2002013262A2 PCT/US2001/024614 US0124614W WO0213262A2 WO 2002013262 A2 WO2002013262 A2 WO 2002013262A2 US 0124614 W US0124614 W US 0124614W WO 0213262 A2 WO0213262 A2 WO 0213262A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
sacrificial
siι
strained
dielectric
Prior art date
Application number
PCT/US2001/024614
Other languages
French (fr)
Other versions
WO2002013262A3 (en
Inventor
Eugene A. Fitzgerald
Richard Hammond
Matthew Currie
Original Assignee
Amberwave Systems Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amberwave Systems Corporation filed Critical Amberwave Systems Corporation
Priority to EP01961913A priority Critical patent/EP1307917A2/en
Priority to JP2002518522A priority patent/JP2004519090A/en
Priority to AU2001283138A priority patent/AU2001283138A1/en
Publication of WO2002013262A2 publication Critical patent/WO2002013262A2/en
Publication of WO2002013262A3 publication Critical patent/WO2002013262A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/0245Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02502Layer structure consisting of two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/0251Graded layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28238Making the insulator with sacrificial oxide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to gate technology for strained surface channel and strained buried channel MOSFET devices.
  • FETs field effect transistors
  • the strain can be incorporated in the channel due to the lattice mismatch between the channel and the relaxed SiGe created by a change in the Ge concentration between the channel layer and the relaxed SiGe layer.
  • a Ge concentration of 20% Ge in the relaxed buffer is high enough such that a thin strained Si layer can exhibit electron mobilities as high aslOOO-2900 cm 2 /V-sec.
  • hole channel mobilities can be enhanced.
  • a relaxed buffer concentration of 60-70% Ge can compressively strain a Ge channel layer, creating potentially extremely high hole mobilities.
  • the devices based on metal- insulator-semiconductor (MIS) or metal-oxide-semiconductor (MOS) gate technology are the most interesting, since these devices can follow very closely the processes already used in Si VLSI manufacturing.
  • MIS metal- insulator-semiconductor
  • MOS metal-oxide-semiconductor
  • Two main types of devices are of particular interest: the surface channel device and the buried channel device, examples of which are shown in FIGs. 1A and IB.
  • FIG. 1 A is a cross section of a block diagram of a strained Si surface channel device 100, in which a thin strained Si layer 102 is grown atop a relaxed SiGe virtual substrate.
  • the SiGe virtual substrate can be relaxed SiGe 104 on a SiGe graded buffer 105 (as shown in Figure la), relaxed SiGe directly on a Si substrate 106, or relaxed
  • the device also includes a SiO 2 layer 108 and gate material 110.
  • FIG. IB is a cross section of a block diagram of a strained Si buried channel device 112, in which a SiGe layer 116 and a second strained Si layer 120 (used for gate oxidation) cap the strained Si channel layer 114.
  • the structure also includes a graded SiGe buffer layerl25 and a second relaxed SiGe layer 126.
  • a gate oxide 122 is grown or deposited and the gate material 124 is deposited to form the (MOS) structure.
  • FIGs. 1A and IB the invention is applicable to any heterostructure device fabricated on a relaxed SiGe platform.
  • the heterostructure strained channel could be Ge or SiGe of a different Ge content from that of the underlying SiGe virtual substrate.
  • the following description will focus on the applicability of the invention to the strained Si device variants illustrated in FIGs. lA and IB.
  • the SiGe would ideally be oxidized directly in the buried channel device, and the strained Si would be oxidized directly in the surface channel device.
  • the surface channel device Unfortunately, there are problems due to the nature of the Si/SiGe heterostructures in both cases that render the direct oxidation process unsatisfactory.
  • the interface state density at the resulting SiO 2 /Si interface is low, and an electrically high quality interface results.
  • all oxidation and cleaning processes during the device and circuit fabrication consume the Si material.
  • the top strained Si layer is typically less than 30 ⁇ A thick, and thus too much Si consumption during cleaning and oxidation steps will eliminate the high mobility channel.
  • One obvious solution is to simply deposit extra Si at the surface, planning for the removal of the Si that occurs during processing.
  • the channel strain which gives the channel its higher carrier mobility, limits the Si layer thickness.
  • the Si layer will begin to relax, introducing misfit dislocations at the Si/SiGe interface.
  • This process of dislocation introduction has two deleterious effects on device performance.
  • the strain in the Si is partially or completely relieved, potentially decreasing the carrier mobility enhancements.
  • dislocations can scatter carriers, decreasing carrier mobility. Dislocations can also affect device yield, reliability, and performance.
  • the buried channel case appears to be a better situation at first, since the Si layer thickness is buried. However, in this case, direct oxidation of SiGe creates a very high interface state density at the oxide/SiGe interface, leading to poor device performance.
  • a known solution in the field is to create a thin Si layer at the surface of the buried channel structure.
  • the surface layer is carefully oxidized to nearly consume the entire top Si layer.
  • a thin layer of un-oxidized Si is left so that the interface to the oxide is the superior SiO 2 /Si interface rather than the problematic oxide/SiGe interface.
  • this sacrificial surface Si layer solves the interface electronic property issue, the structure now has the same limits as the structure described above, i.e., the sacrificial Si layer will be slowly etched away during Si processing, possibly leading to exposure of the SiGe and degradation of the electrical properties of the interface as described.
  • a semiconductor structure including a relaxed Sii-xGex layer on a substrate, a strained channel layer on said relaxed Sii-xGex layer, and a sacrificial Si ⁇ - y Ge y layer.
  • the sacrificial Si ⁇ - y Ge y layer is removed before providing a dielectric layer.
  • the dielectric layer includes a gate dielectric of a MISFET.
  • the structure includes a Si ⁇ - y Ge spacer layer and a Si layer.
  • a method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Sii-xGex layer on a substrate, a strained channel layer on the relaxed Sii-xGex layer, and a Si ⁇ - y Ge y layer; removing the
  • the dielectric layer includes a gate dielectric of a MISFET.
  • the heterostructure includes a
  • SiGe spacer layer and a Si layer.
  • FIGs. 1A and IB are cross sections of block diagrams of strained Si surface and buried channel devices, respectively;
  • FIGs. 2 A and 2B are cross sections of block diagrams of starting heterostructures for surface channel and buried channel strained MOS, respectively, in accordance with the invention;
  • FIGs. 3A-3D are block diagrams showing the process sequence for a strained surface channel MOS device
  • FIGs. 4A-4D are block diagrams showing the process sequence utilizing the gate structure for a buried channel device
  • FIG. 5 is a graph of oxidation rates, under a wet oxidation ambient at 700 °C, of SiGe alloys, with Ge contents of 0.28 and 0.36, compared to the oxidation rate of bulk silicon;
  • FIG. 6 is a graph showing the oxide thickness of both a Sio.7Geo. 3 alloy and a Si/
  • FIG. 7 is a cross-sectional transmission electron micrograph (XTEM) of the Si/Sio. 7 Geo.3 heterostructure
  • FIG. 8 is a XTEM image of the identical Si/Sio.7Geo.3 heterostructure after wet oxidation followed by oxide removal via a wet etch;
  • FIG. 9 is a structure for a buried channel MOSFET using relaxed SiGe and strained Si in accordance with the invention.
  • FIG. 10 is a graph showing a plot of the middle SiGe layer thickness (h2) and the resulting misfit dislocation spacing.
  • FIG. 2A is a cross section of a block diagram of a starting heterostructure 200 for surface channel strained MOS in accordance with the invention.
  • the structure 200 includes a Si substrate 202, a SiGe graded buffer 204, a relaxed SiGe layer 206, and a strained-Si channel layer 208.
  • FIG. 2B is a cross section of a block diagram of a starting heterostructure 214 for buried channel strained Si MOS.
  • the structure 214 includes a Si substrate 216, a SiGe graded buffer 218, relaxed SiGe layers 220 and 230, a first strained-Si channel layer 222 and a second strained-Si layer 224 for the gate oxide.
  • SiGe capping layer 210, 226 is closely lattice-matched to the relaxed SiGe layer below the device layers, there is essentially no limit on the thickness of the SiGe layer.
  • This SiGe layer thickness can be tuned to the thickness of material removed before gate oxidation, so that the strained Si layer is exposed just before oxidation.
  • the SiGe can be thicker than the removal thickness and then can be selectively removed. In fact, as described below, SiGe can be selectively removed with respect to Si using a variety of conventional Si-based processes.
  • cleaning and oxidation steps can be performed during the Si device and circuit fabrication process with little worry of consuming the precious strained Si and/or the sacrificial strained Si.
  • An additional option can be to place yet another Si layer 212, 228 on top of the additional SiGe layer 210, 226.
  • the idea of SiGe on the surface, instead of Si is a factor for concern.
  • another Si layer can be deposited on top of the additional SiGe layer described above.
  • this optional Si capping layer need not be strained at all in this case and can serve as a protective sacrificial layer even if it is fully relaxed.
  • FIGs. 3A-3D are block diagrams showing the process sequence for a strained surface channel MOS device utilizing the gate structure described above (the process is shown for a structure without an optional strained surface layer).
  • FIG. 3 A shows the initial Si/SiGe heterostructure 200 shown in FIG. 2A.
  • FIG. 3B shows the structure after the completion of the initial steps of a Si VLSI process, which could include wet chemical cleans and oxidation steps.
  • the protective SiGe capping layer 210 has been reduced in thickness, as a portion of the layer has been consumed during processing.
  • the remainder of the protective SiGe capping layer 210 is selectively removed, leaving the underlying Si layer 208 intact and exposed.
  • a sacrificial oxidation step and oxide strip can also be performed at this point to improve the quality of the exposed Si surface.
  • FIG. 3C shows the final device structure after gate oxidation to form a gate oxide 300, a structure in which the minimum possible amount of Si was consumed prior to the gate oxidation step.
  • an alternate gate dielectric could be deposited on the exposed Si surface.
  • a pristine Si surface is just as important for a high quality interface with many deposited gate dielectrics as it is for a thermally grown SiO 2 gate dielectric.
  • FIGs. 4A-4D are block diagrams showing the process sequence utilizing the gate structure for a buried channel device (the process is shown for a structure without an optional strained surface layer) using the initial Si/SiGe heterostructure 214 shown in FIG. 2B.
  • the process steps are identical to those of FIGs. 3A-3D, but in the final heterostructure, the Si channel layer 222 is separated from the gate dielectric 400 by a
  • SiGe spacer layer 220 thus forming a buried channel.
  • Using selective processes to etch down to the buried Si channel or the top Si layer can use the starting heterostructure 214 in FIG. 4A to form a surface channel device.
  • Such a process can result in enhancement mode and depletion mode devices that can in turn be used to create E/D logic circuits as well as a plethora of analog circuits.
  • an exemplary sequence of steps is: 1. Pre-gate-oxidation cleaning steps and oxidation; 2. Selective etch or oxidation to remove residual protective SiGe layer; 3. Sacrificial oxide formation on Si; 4. Sacrificial oxide strip; 5. Gate oxidation.
  • steps 3 and 4 can be optional, depending on whether there may be a small amount of Ge left on the surface after the selective removal of the SiGe protection layer.
  • the SiGe/Si interface will not be infinitely abrupt, and therefore it is possible to have a small amount of Ge in the optimally pure Si layer.
  • a sacrificial oxide step can be employed to remove an additional small amount of the Si layer to ensure that pure Si is oxidized in the gate oxidation step, ensuring high quality gate oxide.
  • the second step can be accomplished in a variety of ways.
  • One convenient process is a wet oxidation step, preferably at 750°C or below. Under wet oxidation at these temperatures, SiGe is oxidized at rates that can be 100 times greater than rates oxidizing Si under the same conditions.
  • SiGe is oxidized at rates that can be 100 times greater than rates oxidizing Si under the same conditions.
  • the low temperature is not only important for the selectivity in the oxidation process, but also the low temperature is important to minimize or prevent the snow-plowing of Ge in front of the oxidation front, a known problem in the direct oxidation of SiGe.
  • FIG. 5 is a graph of oxidation rates, under a wet oxidation ambient at 700 °C, of SiGe alloys, with Ge contents of 0.28 and 0.36, compared to the oxidation rate of bulk silicon. It is evident from the graph that, under such conditions, the oxidation rate of SiGe increases as the Ge content of the film increases.
  • FIG. 6 is a similar graph, showing the oxide thickness of both a Sio.7Geo. 3 alloy and a Si/ Sio.7Geo.3 heterostructure. Again, the oxidation conditions were 700 °C in a wet ambient; however, FIG. 6 depicts very short oxidation durations compared to FIG.
  • the Si/ Sio.7Geo.3 heterostructure consists of a 5 ⁇ A strained Si buried layer, followed by a 30 A Sio.7Geo. 3 , a 20 A strained Si layer and finally a 5 ⁇ A Sio.7Geo. 3 capping layer.
  • a cross-sectional transmission electron micrograph (XTEM) of the Si/Sio.7Geo.3 heterostructure is shown in FIG. 7. It should be noted from FIG. 6 that the presence of strained Si layers in the heterostructure results in a dramatic retardation in the oxidation rate when compared to the oxidation rate of the uniform Sio.7Geo.3. This retardation of the oxidation rate forms the basis of the selective removal of SiGe alloys over strained Si epitaxial layers.
  • FIG. 8 is a XTEM image of the identical Si/Sio.7Geo. 3 heterostructure after wet oxidation at 700°C for 2 minutes followed by oxide removal via a wet etch. It is apparent that the thin strained Si layer is unaffected by the selective oxidation and remains fully intact. Based on the data shown in FIG. 5, an oxidation duration of 2 minutes far exceeds that required to fully oxidize the 5 ⁇ A Sio.7Geo. 3 capping layer of the heterostructure.
  • the very thin dark band which is apparent on the surface of the strained Si layer, is a snow-plowed high Ge content layer that occurs during oxidation.
  • Such a layer may be removed using a simple chemical clean or a sacrificial oxidation step, either or both of which typically occur prior to the formation of the gate oxide.
  • the protective SiGe capping layer can be removed via selective dry or wet chemical etching techniques. For example, at high pressures (>200mT) and low powers, CF 4 dry etch chemistries will etch relaxed SiGe films with high selectivity to Si. Mixtures of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH) will also selectively etch relaxed SiGe layers over Si at selectivities of 300:1 or more. Other potential selective wet chemical mixtures include HF, water (H2O), and either H2O2 or nitric acid (HNO 3 ).
  • the stability of the entire structure can be improved by increasing the Ge concentration in the intermediate SiGe layer, and also the top SiGe layer if desired.
  • energetic calculations are used to reveal a guide to creating semiconductor layer structures that increase stability with respect to misfit dislocation introduction.
  • the critical thickness for a buried channel MOSFET using relaxed SiGe and strained Si has been determined using the energy-balance formulation.
  • the structure considered is the one shown in FIG. 9.
  • the structure 900 includes a 30% SiGe virtual substrate 902 topped by a 8 ⁇ A strained Si layer 904, a SiGe layer with Ge concentration x2 and thickness h2 906, and an additional 3 ⁇ A of strained Si 908.
  • Additional stability would result from the addition of an additional SiGe cap layer as described previously.
  • the example of FIG. 9 considers only the increased stability created by increasing the Ge concentration (x2) or thickness (h2) of the SiGe intermediate layer. Additionally, since the SiGe cap layer is removed during processing, the stability of the heterostructure with the SiGe cap removed is or primary importance. In device processing, one must consider the critical thickness of the entire structure with respect to the relaxed virtual substrate. Individual layers that exceed the individual critical thicknesses are not explicitly ruled out, so one practicing the art would have to verify that none of the layers that are introduced into the desired structure exceed the individual layer critical thicknesses. In other words, in the following calculation it is assumed that each layer in the structure is below its critical thickness with respect to the relaxed buffer.
  • the dislocation array energy is the same expression regardless of the layer structure.
  • the elastic energy in the individual layers is changed because of ⁇ . In tensile layers, the strain is lowered by ⁇ . In compressive layers, the energy is raised by ⁇ .
  • the energy for a dislocation array (per unit area) inserted at the base of the composite is:
  • li ⁇ is the total thickness of the composite (hi +h2+h3)
  • is the angle between the dislocation line and the Burgers vector b
  • v is the Poisson ratio
  • D is the average shear modulus for a dislocation lying at the interface between the virtual substrate and the composite structure.
  • the total elastic energy (per unit area) in all the layers is:
  • the energy can now be minimized with respect to ⁇ (if the energy is lowest with no dislocations, then ⁇ will have a less than or equal to zero value).
  • the value of plastic deformation then is (for the 3 layer example):
  • FIG. 10 is a graph showing a plot of the middle SiGe layer thickness (h2) and the resulting misfit dislocation spacing.
  • the sharp upturn on the plots represents the critical thickness h2 of the middle SiGe layer when the entire composite structure destabilizes and introduces dislocations at the channel/virtual buffer interface.
  • the different curves are for the different compositions in the second layer h2.
  • Very small increases in Ge result in a large jump in stability of the device layers. This suggests that it is possible to stabilize the layer significantly but not have the band structure altered that much. Adding an extra 5-10% Ge into the h2 layer increases the stability drastically.
  • FIG. 10 indicates that over lOOA of 30% Ge is required to provide the stability of a 2 ⁇ A layer of 45 % Ge content.
  • Sacrificial SiGe capping layers provide an innovative method for the protection of thin strained device layers during processing. Such layers shield these critically important strained channel layers from process steps, such as wet chemical cleans and oxidations, which consume surface material. Before the growth or deposition of the gate dielectric, these protective SiGe layers can be selectively removed by standard processes such as oxidation or wet etching, revealing the intact strained device layer.
  • Compressively strained intermediate layers increase the stability of tensile channel layers, and also serve as a barrier for misfit dislocation introduction into the underlying layers.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A semiconductor structure including a relaxed Si1-xGex layer on a substrate, a strained channel layer on said relaxed Si1-xGex layer, and a sacrificial Si1-yGey layer. The sacrificial Si1-yGey layer is removed before providing a dielectric layer. The dielectric layer includes a gate dielectric of a MOSFET. In alternative embodiements, the structure includes a Si1-zGey spacer layer and a Si layer. In another embodiment of the invention there is provided a method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer.

Description

GATE TECHNOLOGY FOR STRAINED SURFACE CHANNEL AND STRAINED BURIED CHANNEL MOSFET DEVICES
PRIORITY INFORMATION
This application claims priority from provisional application Ser. No. 60/223,595 filed August 7, 2000.
BACKGROUND OF THE INVENTION
The invention relates to gate technology for strained surface channel and strained buried channel MOSFET devices.
The advent of high quality relaxed SiGe layers on Si has resulted in the demonstration of field effect transistors (FETs) with carrier channels enhanced via strain. The strain can be incorporated in the channel due to the lattice mismatch between the channel and the relaxed SiGe created by a change in the Ge concentration between the channel layer and the relaxed SiGe layer. For example, a Ge concentration of 20% Ge in the relaxed buffer is high enough such that a thin strained Si layer can exhibit electron mobilities as high aslOOO-2900 cm2/V-sec. Also, if the Ge concentration in the channel is greater than the concentration in the buffer, hole channel mobilities can be enhanced. For example, a relaxed buffer concentration of 60-70% Ge can compressively strain a Ge channel layer, creating potentially extremely high hole mobilities.
Although the exact physics of carrier scattering are not known inside short- channel FETs, one thing is clear: these enhanced mobilities translate into increased device performance, even at very short gate lengths. In addition to higher speed and a different power-delay product, the use of strained channels allows for the incorporation of new FET structures into Si-based circuits. Thus, it is anticipated that the high performance, new flexibility in device design, and economics of using a Si-based platform will lead to a plethora of new circuits and products.
With regards to these new circuits and products, the devices based on metal- insulator-semiconductor (MIS) or metal-oxide-semiconductor (MOS) gate technology are the most intriguing, since these devices can follow very closely the processes already used in Si VLSI manufacturing. Two main types of devices are of particular interest: the surface channel device and the buried channel device, examples of which are shown in FIGs. 1A and IB.
FIG. 1 A is a cross section of a block diagram of a strained Si surface channel device 100, in which a thin strained Si layer 102 is grown atop a relaxed SiGe virtual substrate. The SiGe virtual substrate can be relaxed SiGe 104 on a SiGe graded buffer 105 (as shown in Figure la), relaxed SiGe directly on a Si substrate 106, or relaxed
SiGe on an insulator such as SiO2. The device also includes a SiO2 layer 108 and gate material 110.
FIG. IB is a cross section of a block diagram of a strained Si buried channel device 112, in which a SiGe layer 116 and a second strained Si layer 120 (used for gate oxidation) cap the strained Si channel layer 114. The structure also includes a graded SiGe buffer layerl25 and a second relaxed SiGe layer 126. In both device configurations, a gate oxide 122 is grown or deposited and the gate material 124 is deposited to form the (MOS) structure. Although only devices with strained Si channels are shown in FIGs. 1A and IB, the invention is applicable to any heterostructure device fabricated on a relaxed SiGe platform. For example, the heterostructure strained channel could be Ge or SiGe of a different Ge content from that of the underlying SiGe virtual substrate. However, the following description will focus on the applicability of the invention to the strained Si device variants illustrated in FIGs. lA and IB. In order to form the MOS gate of the heterostructure device, the SiGe would ideally be oxidized directly in the buried channel device, and the strained Si would be oxidized directly in the surface channel device. Unfortunately, there are problems due to the nature of the Si/SiGe heterostructures in both cases that render the direct oxidation process unsatisfactory. First consider the surface channel device. Since Si is being oxidized, the interface state density at the resulting SiO2/Si interface is low, and an electrically high quality interface results. However, all oxidation and cleaning processes during the device and circuit fabrication consume the Si material. In conventional Si processing, there is generally little worry about Si consumption since so little material is consumed compared to any limiting vertical dimension early in the fabrication process. However, in the case of the strained surface channel FET described here, the top strained Si layer is typically less than 30θA thick, and thus too much Si consumption during cleaning and oxidation steps will eliminate the high mobility channel. One obvious solution is to simply deposit extra Si at the surface, planning for the removal of the Si that occurs during processing. However, the channel strain, which gives the channel its higher carrier mobility, limits the Si layer thickness. At a great enough thickness, the Si layer will begin to relax, introducing misfit dislocations at the Si/SiGe interface. This process of dislocation introduction has two deleterious effects on device performance. First, the strain in the Si is partially or completely relieved, potentially decreasing the carrier mobility enhancements. Second, dislocations can scatter carriers, decreasing carrier mobility. Dislocations can also affect device yield, reliability, and performance. The buried channel case appears to be a better situation at first, since the Si layer thickness is buried. However, in this case, direct oxidation of SiGe creates a very high interface state density at the oxide/SiGe interface, leading to poor device performance. A known solution in the field is to create a thin Si layer at the surface of the buried channel structure. In this structure, the surface layer is carefully oxidized to nearly consume the entire top Si layer. However, a thin layer of un-oxidized Si is left so that the interface to the oxide is the superior SiO2/Si interface rather than the problematic oxide/SiGe interface. Although this sacrificial surface Si layer solves the interface electronic property issue, the structure now has the same limits as the structure described above, i.e., the sacrificial Si layer will be slowly etched away during Si processing, possibly leading to exposure of the SiGe and degradation of the electrical properties of the interface as described.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the invention there is provided a semiconductor structure including a relaxed Sii-xGex layer on a substrate, a strained channel layer on said relaxed Sii-xGex layer, and a sacrificial Siι-yGey layer. In one aspect, the sacrificial Siι-yGey layer is removed before providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments the structure includes a Siι-yGe spacer layer and a Si layer. In accordance with another embodiment of the invention there is provided a method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Sii-xGex layer on a substrate, a strained channel layer on the relaxed Sii-xGex layer, and a Siι-yGey layer; removing the
Siι-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a
SiGe spacer layer and a Si layer.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGs. 1A and IB are cross sections of block diagrams of strained Si surface and buried channel devices, respectively; FIGs. 2 A and 2B are cross sections of block diagrams of starting heterostructures for surface channel and buried channel strained MOS, respectively, in accordance with the invention;
FIGs. 3A-3D are block diagrams showing the process sequence for a strained surface channel MOS device; FIGs. 4A-4D are block diagrams showing the process sequence utilizing the gate structure for a buried channel device;
FIG. 5 is a graph of oxidation rates, under a wet oxidation ambient at 700 °C, of SiGe alloys, with Ge contents of 0.28 and 0.36, compared to the oxidation rate of bulk silicon; FIG. 6 is a graph showing the oxide thickness of both a Sio.7Geo.3 alloy and a Si/
Sio.7Geo.3 heterostructure;
FIG. 7 is a cross-sectional transmission electron micrograph (XTEM) of the Si/Sio.7Geo.3 heterostructure;
FIG. 8 is a XTEM image of the identical Si/Sio.7Geo.3 heterostructure after wet oxidation followed by oxide removal via a wet etch;
FIG. 9 is a structure for a buried channel MOSFET using relaxed SiGe and strained Si in accordance with the invention; and
FIG. 10 is a graph showing a plot of the middle SiGe layer thickness (h2) and the resulting misfit dislocation spacing.
DETAILED DESCRIPTION OF THE INVENTION
To eliminate the issue of losing valuable surface Si, an innovative step that has not been previously considered can be employed. In fact, any interest in this area is dominated by discussions of how to change the Si device and circuit process to conserve Si consumption. Although these are certainly possibilities, such constraints severely limit process flexibility, alter the process further from the conventional Si process, and most likely will increase the cost of the fabrication process.
A solution for the buried channel and surface channel structures is to actually deposit another SiGe layer after the desired device structure (which, in the buried channel heterostructure, includes the sacrificial Si layer for oxidation). The structures are shown in FIGs. 2A and 2B. FIG. 2A is a cross section of a block diagram of a starting heterostructure 200 for surface channel strained MOS in accordance with the invention. The structure 200 includes a Si substrate 202, a SiGe graded buffer 204, a relaxed SiGe layer 206, and a strained-Si channel layer 208. FIG. 2B is a cross section of a block diagram of a starting heterostructure 214 for buried channel strained Si MOS. The structure 214 includes a Si substrate 216, a SiGe graded buffer 218, relaxed SiGe layers 220 and 230, a first strained-Si channel layer 222 and a second strained-Si layer 224 for the gate oxide.
These structures are identical to those depicted in FIGs. 1A and IB before the gate stack formation, except for the addition of a SiGe capping layer 210, 226 and an optional Si capping layer 212, 228. Since the SiGe layer 210, 226 is closely lattice-matched to the relaxed SiGe layer below the device layers, there is essentially no limit on the thickness of the SiGe layer. This SiGe layer thickness can be tuned to the thickness of material removed before gate oxidation, so that the strained Si layer is exposed just before oxidation. Alternatively, the SiGe can be thicker than the removal thickness and then can be selectively removed. In fact, as described below, SiGe can be selectively removed with respect to Si using a variety of conventional Si-based processes. Therefore, cleaning and oxidation steps can be performed during the Si device and circuit fabrication process with little worry of consuming the precious strained Si and/or the sacrificial strained Si. One only needs to create a SiGe thick enough such that it is not totally consumed before the critical gate oxidation step.
An additional option can be to place yet another Si layer 212, 228 on top of the additional SiGe layer 210, 226. In some processing facilities, the idea of SiGe on the surface, instead of Si, is a factor for concern. In this case, another Si layer can be deposited on top of the additional SiGe layer described above. By choosing the Ge concentration in the additional SiGe layer to be greater than that of the virtual buffer, a compressive layer can be created; thus, if this additional optional Si layer is greater than the critical thickness, there is no possibility of dislocations moving into the device layers. This phenomenon occurs since the Si layers are tensile, and therefore dislocations introduced into the top optional Si layer have a Burgers vector that will not allow them to glide favorably in the compressive layer below. The dislocations in the top optional Si layer (if the Si layer critical thickness is exceeded) will not penetrate into the layers beneath it, and therefore as much Si can be deposited as desired. In fact, this optional Si capping layer need not be strained at all in this case and can serve as a protective sacrificial layer even if it is fully relaxed.
FIGs. 3A-3D are block diagrams showing the process sequence for a strained surface channel MOS device utilizing the gate structure described above (the process is shown for a structure without an optional strained surface layer). FIG. 3 A shows the initial Si/SiGe heterostructure 200 shown in FIG. 2A. FIG. 3B shows the structure after the completion of the initial steps of a Si VLSI process, which could include wet chemical cleans and oxidation steps. Thus, in FIG. 3B, the protective SiGe capping layer 210 has been reduced in thickness, as a portion of the layer has been consumed during processing.
Next, the remainder of the protective SiGe capping layer 210 is selectively removed, leaving the underlying Si layer 208 intact and exposed. A sacrificial oxidation step and oxide strip can also be performed at this point to improve the quality of the exposed Si surface.
The resulting structure is shown in FIG. 3C. FIG. 3D shows the final device structure after gate oxidation to form a gate oxide 300, a structure in which the minimum possible amount of Si was consumed prior to the gate oxidation step. Alternatively, at this point an alternate gate dielectric could be deposited on the exposed Si surface. A pristine Si surface is just as important for a high quality interface with many deposited gate dielectrics as it is for a thermally grown SiO2 gate dielectric. FIGs. 4A-4D are block diagrams showing the process sequence utilizing the gate structure for a buried channel device (the process is shown for a structure without an optional strained surface layer) using the initial Si/SiGe heterostructure 214 shown in FIG. 2B. The process steps are identical to those of FIGs. 3A-3D, but in the final heterostructure, the Si channel layer 222 is separated from the gate dielectric 400 by a
SiGe spacer layer 220, thus forming a buried channel. Using selective processes to etch down to the buried Si channel or the top Si layer can use the starting heterostructure 214 in FIG. 4A to form a surface channel device. Such a process can result in enhancement mode and depletion mode devices that can in turn be used to create E/D logic circuits as well as a plethora of analog circuits.
In both sequences, an exemplary sequence of steps is: 1. Pre-gate-oxidation cleaning steps and oxidation; 2. Selective etch or oxidation to remove residual protective SiGe layer; 3. Sacrificial oxide formation on Si; 4. Sacrificial oxide strip; 5. Gate oxidation.
It will be appreciated that steps 3 and 4 can be optional, depending on whether there may be a small amount of Ge left on the surface after the selective removal of the SiGe protection layer. When the original heterostructure is grown, the SiGe/Si interface will not be infinitely abrupt, and therefore it is possible to have a small amount of Ge in the optimally pure Si layer. A sacrificial oxide step can be employed to remove an additional small amount of the Si layer to ensure that pure Si is oxidized in the gate oxidation step, ensuring high quality gate oxide.
The second step, the selective removal of the residual SiGe protective material, can be accomplished in a variety of ways. One convenient process is a wet oxidation step, preferably at 750°C or below. Under wet oxidation at these temperatures, SiGe is oxidized at rates that can be 100 times greater than rates oxidizing Si under the same conditions. Thus, in order to expose the Si for gate oxidation, one can simply do a wet oxidation of the SiGe layer and selectively stop at the Si layer. The oxidized SiGe can be stripped to expose the Si. It is important to note here that the low temperature is not only important for the selectivity in the oxidation process, but also the low temperature is important to minimize or prevent the snow-plowing of Ge in front of the oxidation front, a known problem in the direct oxidation of SiGe.
FIG. 5 is a graph of oxidation rates, under a wet oxidation ambient at 700 °C, of SiGe alloys, with Ge contents of 0.28 and 0.36, compared to the oxidation rate of bulk silicon. It is evident from the graph that, under such conditions, the oxidation rate of SiGe increases as the Ge content of the film increases.
FIG. 6 is a similar graph, showing the oxide thickness of both a Sio.7Geo.3 alloy and a Si/ Sio.7Geo.3 heterostructure. Again, the oxidation conditions were 700 °C in a wet ambient; however, FIG. 6 depicts very short oxidation durations compared to FIG.
5. The Si/ Sio.7Geo.3 heterostructure consists of a 5θA strained Si buried layer, followed by a 30 A Sio.7Geo.3, a 20 A strained Si layer and finally a 5θA Sio.7Geo.3 capping layer. A cross-sectional transmission electron micrograph (XTEM) of the Si/Sio.7Geo.3 heterostructure is shown in FIG. 7. It should be noted from FIG. 6 that the presence of strained Si layers in the heterostructure results in a dramatic retardation in the oxidation rate when compared to the oxidation rate of the uniform Sio.7Geo.3. This retardation of the oxidation rate forms the basis of the selective removal of SiGe alloys over strained Si epitaxial layers.
FIG. 8 is a XTEM image of the identical Si/Sio.7Geo.3 heterostructure after wet oxidation at 700°C for 2 minutes followed by oxide removal via a wet etch. It is apparent that the thin strained Si layer is unaffected by the selective oxidation and remains fully intact. Based on the data shown in FIG. 5, an oxidation duration of 2 minutes far exceeds that required to fully oxidize the 5θA Sio.7Geo.3 capping layer of the heterostructure. The very thin dark band, which is apparent on the surface of the strained Si layer, is a snow-plowed high Ge content layer that occurs during oxidation. Such a layer may be removed using a simple chemical clean or a sacrificial oxidation step, either or both of which typically occur prior to the formation of the gate oxide. Alternatively, the protective SiGe capping layer can be removed via selective dry or wet chemical etching techniques. For example, at high pressures (>200mT) and low powers, CF4 dry etch chemistries will etch relaxed SiGe films with high selectivity to Si. Mixtures of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH) will also selectively etch relaxed SiGe layers over Si at selectivities of 300:1 or more. Other potential selective wet chemical mixtures include HF, water (H2O), and either H2O2 or nitric acid (HNO3).
Additionally, the stability of the entire structure can be improved by increasing the Ge concentration in the intermediate SiGe layer, and also the top SiGe layer if desired. Below, energetic calculations are used to reveal a guide to creating semiconductor layer structures that increase stability with respect to misfit dislocation introduction.
The critical thickness for a buried channel MOSFET using relaxed SiGe and strained Si has been determined using the energy-balance formulation. The structure considered is the one shown in FIG. 9. The structure 900 includes a 30% SiGe virtual substrate 902 topped by a 8θA strained Si layer 904, a SiGe layer with Ge concentration x2 and thickness h2 906, and an additional 3θA of strained Si 908.
Additional stability would result from the addition of an additional SiGe cap layer as described previously. To simplify, the example of FIG. 9 considers only the increased stability created by increasing the Ge concentration (x2) or thickness (h2) of the SiGe intermediate layer. Additionally, since the SiGe cap layer is removed during processing, the stability of the heterostructure with the SiGe cap removed is or primary importance. In device processing, one must consider the critical thickness of the entire structure with respect to the relaxed virtual substrate. Individual layers that exceed the individual critical thicknesses are not explicitly ruled out, so one practicing the art would have to verify that none of the layers that are introduced into the desired structure exceed the individual layer critical thicknesses. In other words, in the following calculation it is assumed that each layer in the structure is below its critical thickness with respect to the relaxed buffer.
One key to the formulation is to realize that this calculation should be done with respect to the plastic deformation of the layer composite, δ. Then, the dislocation array energy is the same expression regardless of the layer structure. The elastic energy in the individual layers is changed because of δ. In tensile layers, the strain is lowered by δ. In compressive layers, the energy is raised by δ.
Thus, the energy for a dislocation array (per unit area) inserted at the base of the composite is:
Eδ=2δD(l-vcos α)[ln(hτ/b) + l]
where liτ is the total thickness of the composite (hi +h2+h3), α is the angle between the dislocation line and the Burgers vector b, v is the Poisson ratio, and D is the average shear modulus for a dislocation lying at the interface between the virtual substrate and the composite structure.
The total elastic energy (per unit area) in all the layers is:
Figure imgf000011_0001
where Y is the Young's modulus. Thus, the total energy of the system is: Eτ=Eδ + Eε.
The energy can now be minimized with respect to δ (if the energy is lowest with no dislocations, then δ will have a less than or equal to zero value). The value of plastic deformation then is (for the 3 layer example):
Figure imgf000012_0001
The examination of this solution reveals that a general formulation for any structure would be (for any structure of n layers):
Figure imgf000012_0002
where f has been assigned a negative value for compressive layers and positive value for tensile layers, and τ is the total thickness of the structure:
hT = ∑hl .
The amount of plastic deformation and resulting misfit dislocation spacing S was calculated for the structure depicted in FIG. 9 as follows:
Lower strained Si layer thickness hl = 8θA Upper strained Si layer thickness h3 = 3θA
Middle SiGe layer thickness h2 variable
Middle SiGe layer Ge concentration x2 variable
Virtual substrate Ge concentration: 30%
FIG. 10 is a graph showing a plot of the middle SiGe layer thickness (h2) and the resulting misfit dislocation spacing. The sharp upturn on the plots represents the critical thickness h2 of the middle SiGe layer when the entire composite structure destabilizes and introduces dislocations at the channel/virtual buffer interface. The different curves are for the different compositions in the second layer h2. Very small increases in Ge result in a large jump in stability of the device layers. This suggests that it is possible to stabilize the layer significantly but not have the band structure altered that much. Adding an extra 5-10% Ge into the h2 layer increases the stability drastically. For example, FIG. 10 indicates that over lOOA of 30% Ge is required to provide the stability of a 2θA layer of 45 % Ge content.
Increasing h2 even when the h2 layer is lattice-matched to the virtual buffer increases the stability of the multilayer structure. In the equations above, the effect can be seen to be much weaker than when a compressive strain in h2 is created. When f2 is zero due to lattice matching to the virtual buffer, the increased stability with increasing h2 comes from the fact that ht is increasing and therefore decreasing δ (and increasing S).
It will be appreciated that all the calculations are equilibrium calculations, and as usual, one might suspect that these numbers are somewhat conservative, although also consider that the layers possess many threading dislocations that can bend over at the critical thickness, so there are plenty of sources for misfit dislocation generation.
Sacrificial SiGe capping layers provide an innovative method for the protection of thin strained device layers during processing. Such layers shield these critically important strained channel layers from process steps, such as wet chemical cleans and oxidations, which consume surface material. Before the growth or deposition of the gate dielectric, these protective SiGe layers can be selectively removed by standard processes such as oxidation or wet etching, revealing the intact strained device layer.
Also presented is a guideline for engineering strained layer stacks such that relaxation via misfit dislocation is prevented. Compressively strained intermediate layers increase the stability of tensile channel layers, and also serve as a barrier for misfit dislocation introduction into the underlying layers.
Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.
What is claimed is:

Claims

CLAIMS 1. A semiconductor structure comprising: a relaxed Sii-xGex layer on a substrate; a strained channel layer on said relaxed Siι-xGeχ layer; and a sacrificial Siι-yGey layer.
2. The structure of claim 1, wherein said sacrificial Siι-yGey layer is removed before providing a dielectric layer.
3. The structure of claim 2, wherein said dielectric layer comprises a gate dielectric of a MISFET.
4. The structure of claim 3, wherein the gate dielectric comprises an oxide.
5. The structure of claim 3, wherein the gate dielectric is deposited.
6. The structure of claim 3, wherein the MISFET comprises a surface channel device.
7. The structure of claim 3, wherein the MISFET comprises a buried channel device.
8. The structure of claim 1, wherein the strained channel comprises Si.
9. The structure of claim 1, wherein x is approximately equal to y.
10. The structure of claim 9 further comprising a sacrificial Si layer on said sacrificial Siι-yGey layer.
11. The structure of claim 1 , wherein y > x.
12. The structure of claim 11 further comprising a sacrificial Si layer on said sacrificial Siι- Gey layer.
13. The structure of claim 12, wherein the thickness of the sacrificial Si layer is greater than the critical thickness.
14. The structure of claim 1, wherein the substrate comprises Si.
15. The structure of claim 1, wherein the substrate comprises Si with a layer of SiO2.
16. The structure of claim 1, wherein the substrate comprises a SiGe graded buffer layer on Si.
17. The structure of claim 1 further comprising a Siι-wGew spacer layer.
18. The structure of claim 17, wherein said sacrificial Siι-yGey layer is removed before providing a dielectric layer.
19. The structure of claim 18, wherein said dielectric layer comprises the gate dielectric of a MISFET.
20. The structure of claim 19, wherein the gate dielectric comprises an oxide.
21. The structure of claim 19, wherein the gate dielectric is deposited.
22. The structure of claim 19, wherein the MISFET comprises a buried channel device.
23. The structure of claim 17, wherein the strained channel comprises Si.
24. The structure of claim 17, wherein w is approximately equal to y.
25. The structure of claim 24 further comprising a sacrificial Si layer on said sacrificial Siι-yGey layer.
26. The structure of claim 17, wherein y > w.
27. The structure of claim 26 further comprising a sacrificial Si layer on said sacrificial Siι-yGey layer.
28. The structure of claim 27, wherein the thickness of the sacrificial Si layer is greater than the critical thickness.
29. The structure of claim 17, wherein the substrate comprises Si.
30. The structure of claim 17, wherein the substrate comprises Si with a layer
31. The structure of claim 17, wherein the substrate comprises a SiGe graded buffer layer on Si.
32. The structure of claim 1 further comprising a Sii-wGew spacer layer and a Si layer.
33. The structure of claim 32, wherein said sacrificial Siι-yGey layer is removed before providing a dielectric layer.
34. The structure of claim 33, wherein said dielectric layer comprises the gate dielectric of a MISFET .
35. The structure of claim 34, wherein the gate dielectric comprises an oxide provided by oxidizing said Si layer.
36. The structure of claim 1 , wherein y is made greater than x in order to enhance the stability of said semiconductor structure.
37. A method of fabricating a semiconductor device comprising: providing a semiconductor heterostructure, said heterostructure comprising a relaxed Sii-xGex layer on a substrate, a strained channel layer on said relaxed Sii-xGex layer, and a Siι-yGey layer; removing said Siι-yGey layer; and providing a dielectric layer.
38. The method of claim 37, wherein said Siι-yGey layer is removed by a selective technique.
39. The method of claim 38, wherein said selective technique is wet oxidation below 750°C.
40. The method of claim 38, wherein said selective technique is a wet or dry chemical etch.
41. The method of claim 37, wherein said dielectric layer comprises a gate dielectric of a MISFET.
42. The method of claim 41, wherein the gate dielectric comprises an oxide.
1 43. The method of claim 41, wherein the gate dielectric is deposited.
1 44. The method of claim 41, wherein the MISFET comprises a surface channel
2 device.
1 45. The method of claim 41 , wherein the MISFET comprises a buried channel
2 device.
1 46. The method of claim 37, wherein the strained channel layer comprises Si.
l 47. The method of claim 37, wherein x is approximately equal to y.
1 48. The method of claim 47 further comprising a sacrificial Si layer on said
2 sacrificial Siι-yGey layer.
1 49. The method of claim 37, wherein y > x.
1 50. The method of claim 49 further comprising a sacrificial Si layer on said
2 sacrificial Siι-yGey layer.
1 51. The method of claim 50, wherein the thickness of the sacrificial Si layer is
2 greater than the critical thickness.
l 52. The method of claim 37, wherein the substrate comprises Si.
1 53. The method of claim 37, wherein the substrate comprises Si with a layer of
2 SiO2.
1 54. The method of claim 37, wherein the substrate comprises a SiGe graded
2 buffer layer on Si.
1 55. The method of claim 37, wherein- the semiconductor device comprises a
2 MISFET.
1 56. The method of claim 37, wherein said Siι-yGe layer is removed to expose
2 said strained channel layer.
1 57. The method of claim 37, wherein said heterostructure further comprises a
2 Sii- Gew spacer layer.
1 58. The method of claim 57, wherein said dielectric layer comprises the gate
2 dielectric of a MISFET.
1 59. The method of claim 58, wherein the gate dielectric comprises an oxide.
1 60. The method of claim 58, wherein the gate dielectric is deposited.
1 61. The method of claim 58, wherein the MISFET comprises a buried channel
2 device.
l 62. The method of claim 57, wherein the strained channel comprises Si.
l
63. The method of claim 57, wherein y is approximately equal to w.
1 64. The method of claim 63 further comprising a sacrificial Si layer on said
2 sacrificial Siι-yGey layer.
l
65. The method of claim 57, wherein w > y.
1 66. The method of claim 65 further comprising a sacrificial Si layer on said
2 sacrificial Siι-yGey layer.
1 67. The method of claim 66, wherein the thickness of the sacrificial Si layer is
2 greater than the critical thickness.
1 68. The method of claim 57, wherein the substrate comprises Si.
1 69. The method of claim 57, wherein the substrate comprises Si with a layer of
1 70. The method of claim 57, wherein the substrate comprises a SiGe graded
2 buffer layer on Si.
1 71. The method of claim 57, wherein the semiconductor device comprises a
2 MISFET.
1 72. A method of fabricating a semiconductor device comprising:
2 providing a semiconductor heterostructure, said heterostructure comprising a
3 relaxed Sii-xGex layer on a substrate, a strained channel layer on said relaxed Sii-xGex layer, a Siι-yGey spacer layer, a Si layer, and a Siι-wGew layer; removing said Siι-wGew layer to expose said Si layer; and providing a dielectric layer.
73. A method of fabricating a semiconductor device comprising: providing a semiconductor heterostructure, said heterostructure comprising a relaxed Siι-xGex layer on a substrate, a strained channel layer on said relaxed Sii-xGex layer, a Siι-yGey spacer layer, a Si layer, and a Siι-wGe layer; removing said Siι-wGew layer to expose said Si layer; and oxidizing said Si layer.
74. The method of claim 73, wherein the semiconductor device comprises a MOSFET.
75. The method of claim 73, wherein the semiconductor device comprises a buried channel MOSFET.
PCT/US2001/024614 2000-08-07 2001-08-06 Gate technology for strained surface channel and strained buried channel mosfet devices WO2002013262A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP01961913A EP1307917A2 (en) 2000-08-07 2001-08-06 Gate technology for strained surface channel and strained buried channel mosfet devices
JP2002518522A JP2004519090A (en) 2000-08-07 2001-08-06 Gate technology for strained surface channel and strained buried channel MOSFET devices
AU2001283138A AU2001283138A1 (en) 2000-08-07 2001-08-06 Gate technology for strained surface channel and strained buried channel mosfet devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22359500P 2000-08-07 2000-08-07
US60/223,595 2000-08-07

Publications (2)

Publication Number Publication Date
WO2002013262A2 true WO2002013262A2 (en) 2002-02-14
WO2002013262A3 WO2002013262A3 (en) 2002-05-02

Family

ID=22837179

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/024614 WO2002013262A2 (en) 2000-08-07 2001-08-06 Gate technology for strained surface channel and strained buried channel mosfet devices

Country Status (5)

Country Link
US (5) US20020104993A1 (en)
EP (1) EP1307917A2 (en)
JP (1) JP2004519090A (en)
AU (1) AU2001283138A1 (en)
WO (1) WO2002013262A2 (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002071493A2 (en) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog
WO2002071488A1 (en) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits
US6593641B1 (en) 2001-03-02 2003-07-15 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6646322B2 (en) 2001-03-02 2003-11-11 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
WO2003105221A1 (en) * 2002-06-07 2003-12-18 Amberwave Systems Corporation Cmos transistors with differentially strained channels of different thickness
WO2004001825A1 (en) * 2002-06-25 2003-12-31 Amberwave Systems Corporation SiGe GATE ELECTRODES ON SiGe SUBSTRATES AND METHODS OF MAKING THE SAME
WO2004021420A2 (en) * 2002-08-29 2004-03-11 Massachusetts Institute Of Technology Fabrication method for a monocrystalline semiconductor layer on a substrate
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6730551B2 (en) 2001-08-06 2004-05-04 Massachusetts Institute Of Technology Formation of planar strained layers
WO2004019391A3 (en) * 2002-08-23 2004-12-02 Amberwave Systems Corp Semiconductor heterostructures having reduced dislocation pile-ups and related methods
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6900103B2 (en) 2001-03-02 2005-05-31 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6900094B2 (en) 2001-06-14 2005-05-31 Amberwave Systems Corporation Method of selective removal of SiGe alloys
US6916727B2 (en) 2001-06-21 2005-07-12 Massachusetts Institute Of Technology Enhancement of P-type metal-oxide-semiconductor field effect transistors
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US7138310B2 (en) 2002-06-07 2006-11-21 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US7709828B2 (en) 2001-09-24 2010-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2295069A1 (en) * 1997-06-24 1998-12-30 Eugene A. Fitzgerald Controlling threading dislocation densities in ge on si using graded gesi layers and planarization
US7227176B2 (en) * 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
JP2003520444A (en) * 2000-01-20 2003-07-02 アンバーウェーブ システムズ コーポレイション Low threading dislocation density lattice-mismatched epilayer that does not require high-temperature growth
JP2004519090A (en) * 2000-08-07 2004-06-24 アンバーウェーブ システムズ コーポレイション Gate technology for strained surface channel and strained buried channel MOSFET devices
US6573126B2 (en) 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
EP1421607A2 (en) 2001-02-12 2004-05-26 ASM America, Inc. Improved process for deposition of semiconductor films
US6723661B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6831292B2 (en) * 2001-09-21 2004-12-14 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
JP3970011B2 (en) * 2001-12-11 2007-09-05 シャープ株式会社 Semiconductor device and manufacturing method thereof
US7060632B2 (en) * 2002-03-14 2006-06-13 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US6680496B1 (en) * 2002-07-08 2004-01-20 Amberwave Systems Corp. Back-biasing to populate strained layer quantum wells
US6841457B2 (en) * 2002-07-16 2005-01-11 International Business Machines Corporation Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion
US7186630B2 (en) 2002-08-14 2007-03-06 Asm America, Inc. Deposition of amorphous silicon-containing films
US6646318B1 (en) * 2002-08-15 2003-11-11 National Semiconductor Corporation Bandgap tuned vertical color imager cell
US6878610B1 (en) * 2002-08-27 2005-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Relaxed silicon germanium substrate with low defect density
WO2004102635A2 (en) * 2002-10-30 2004-11-25 Amberwave Systems Corporation Methods for preserving strained semiconductor layers during oxide layer formation
US6730576B1 (en) * 2002-12-31 2004-05-04 Advanced Micro Devices, Inc. Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
US6963078B2 (en) * 2003-03-15 2005-11-08 International Business Machines Corporation Dual strain-state SiGe layers for microelectronics
US6982229B2 (en) * 2003-04-18 2006-01-03 Lsi Logic Corporation Ion recoil implantation and enhanced carrier mobility in CMOS device
US20040206951A1 (en) * 2003-04-18 2004-10-21 Mirabedini Mohammad R. Ion implantation in channel region of CMOS device for enhanced carrier mobility
KR100679737B1 (en) * 2003-05-19 2007-02-07 도시바세라믹스가부시키가이샤 A method for manufacturing a silicon substrate having a distorted layer
US7026249B2 (en) * 2003-05-30 2006-04-11 International Business Machines Corporation SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth
US7208362B2 (en) * 2003-06-25 2007-04-24 Texas Instruments Incorporated Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel
US7176041B2 (en) * 2003-07-01 2007-02-13 Samsung Electronics Co., Ltd. PAA-based etchant, methods of using same, and resultant structures
US7164182B2 (en) * 2003-07-07 2007-01-16 Micron Technology, Inc. Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
US6803240B1 (en) * 2003-09-03 2004-10-12 International Business Machines Corporation Method of measuring crystal defects in thin Si/SiGe bilayers
US6872641B1 (en) * 2003-09-23 2005-03-29 International Business Machines Corporation Strained silicon on relaxed sige film with uniform misfit dislocation density
TWI242237B (en) * 2003-10-16 2005-10-21 Ind Tech Res Inst A manufacturing method and structure for relation strained sige
US6955932B2 (en) * 2003-10-29 2005-10-18 International Business Machines Corporation Single and double-gate pseudo-FET devices for semiconductor materials evaluation
US7370787B2 (en) * 2003-12-15 2008-05-13 Pratt & Whitney Canada Corp. Compressor rotor and method for making
US7244654B2 (en) * 2003-12-31 2007-07-17 Texas Instruments Incorporated Drive current improvement from recessed SiGe incorporation close to gate
US7224007B1 (en) * 2004-01-12 2007-05-29 Advanced Micro Devices, Inc. Multi-channel transistor with tunable hot carrier effect
US7166522B2 (en) * 2004-01-23 2007-01-23 Chartered Semiconductor Manufacturing Ltd. Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch
US6995078B2 (en) * 2004-01-23 2006-02-07 Chartered Semiconductor Manufacturing Ltd. Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch
US7060539B2 (en) * 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
JP3884439B2 (en) * 2004-03-02 2007-02-21 株式会社東芝 Semiconductor device
US7018882B2 (en) * 2004-03-23 2006-03-28 Sharp Laboratories Of America, Inc. Method to form local “silicon-on-nothing” or “silicon-on-insulator” wafers with tensile-strained silicon
FR2872626B1 (en) * 2004-07-05 2008-05-02 Commissariat Energie Atomique METHOD FOR CONTRAINDING A THIN PATTERN
US7060579B2 (en) * 2004-07-29 2006-06-13 Texas Instruments Incorporated Increased drive current by isotropic recess etch
CA2570324C (en) * 2004-08-03 2014-07-22 Transtech Pharma, Inc. Rage fusion proteins and methods of use
US20060105559A1 (en) * 2004-11-15 2006-05-18 International Business Machines Corporation Ultrathin buried insulators in Si or Si-containing material
US7547605B2 (en) * 2004-11-22 2009-06-16 Taiwan Semiconductor Manufacturing Company Microelectronic device and a method for its manufacture
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7479431B2 (en) * 2004-12-17 2009-01-20 Intel Corporation Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain
US7687383B2 (en) * 2005-02-04 2010-03-30 Asm America, Inc. Methods of depositing electrically active doped crystalline Si-containing films
US20060234455A1 (en) * 2005-04-19 2006-10-19 Chien-Hao Chen Structures and methods for forming a locally strained transistor
JP2007036134A (en) * 2005-07-29 2007-02-08 Toshiba Corp Semiconductor wafer and method for manufacturing semiconductor device
US7348225B2 (en) * 2005-10-27 2008-03-25 International Business Machines Corporation Structure and method of fabricating FINFET with buried channel
US20070105516A1 (en) * 2005-11-10 2007-05-10 Hickman Barton T Automatic compensation of gain versus temperature
JP2009521801A (en) * 2005-12-22 2009-06-04 エーエスエム アメリカ インコーポレイテッド Epitaxial deposition of doped semiconductor materials.
US8900980B2 (en) * 2006-01-20 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Defect-free SiGe source/drain formation by epitaxy-free process
US8278176B2 (en) 2006-06-07 2012-10-02 Asm America, Inc. Selective epitaxial formation of semiconductor films
US9252981B2 (en) 2006-06-13 2016-02-02 At&T Intellectual Property I, L.P. Method and apparatus for processing a communication request from a roaming voice over IP terminal
US7989901B2 (en) 2007-04-27 2011-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with improved source/drain regions with SiGe
US7759199B2 (en) * 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
FR2921515B1 (en) * 2007-09-25 2010-07-30 Commissariat Energie Atomique METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURES USEFUL FOR PRODUCING SEMICONDUCTOR-OVER-INSULATING SUBSTRATES, AND APPLICATIONS THEREOF
US7939447B2 (en) * 2007-10-26 2011-05-10 Asm America, Inc. Inhibitors for selective deposition of silicon containing films
US7655543B2 (en) * 2007-12-21 2010-02-02 Asm America, Inc. Separate injection of reactive species in selective formation of films
US8453913B2 (en) 2009-02-06 2013-06-04 Covidien Lp Anvil for surgical stapler
US8486191B2 (en) * 2009-04-07 2013-07-16 Asm America, Inc. Substrate reactor with adjustable injectors for mixing gases within reaction chamber
US8367528B2 (en) 2009-11-17 2013-02-05 Asm America, Inc. Cyclical epitaxial deposition and etch
US8809170B2 (en) 2011-05-19 2014-08-19 Asm America Inc. High throughput cyclical epitaxial deposition and etch process
US9059321B2 (en) 2012-05-14 2015-06-16 International Business Machines Corporation Buried channel field-effect transistors
US9041062B2 (en) 2013-09-19 2015-05-26 International Business Machines Corporation Silicon-on-nothing FinFETs
CN103940885B (en) * 2014-03-18 2017-11-28 复旦大学 Ion-sensitive field effect transistor and its preparation technology
US20160141360A1 (en) * 2014-11-19 2016-05-19 International Business Machines Corporation Iii-v semiconductor devices with selective oxidation
US9899274B2 (en) 2015-03-16 2018-02-20 International Business Machines Corporation Low-cost SOI FinFET technology
US9443953B1 (en) 2015-08-24 2016-09-13 International Business Machines Corporation Sacrificial silicon germanium channel for inversion oxide thickness scaling with mitigated work function roll-off and improved negative bias temperature instability
US10529738B2 (en) * 2016-04-28 2020-01-07 Globalfoundries Singapore Pte. Ltd. Integrated circuits with selectively strained device regions and methods for fabricating same
KR102710507B1 (en) 2016-12-14 2024-09-25 삼성전자주식회사 Etching composition and method for fabricating semiconductor device by using the same
CN110494961B (en) * 2017-04-11 2023-06-13 恩特格里斯公司 Formulations for selectively etching silicon-germanium relative to silicon
KR102480348B1 (en) 2018-03-15 2022-12-23 삼성전자주식회사 Pre-treatment composition before etching SiGe and method of fabricating a semiconductor device
CN109950153B (en) * 2019-03-08 2022-03-04 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0587520A1 (en) * 1992-08-10 1994-03-16 International Business Machines Corporation A SiGe thin film or SOI MOSFET and method for making the same
EP0683522A2 (en) * 1994-05-20 1995-11-22 International Business Machines Corporation CMOS with strained Si/SiGe layers
JP2000031491A (en) * 1998-07-14 2000-01-28 Hitachi Ltd Semiconductor device, its manufacture, semiconductor substrate and its manufacture

Family Cites Families (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3542482A1 (en) * 1985-11-30 1987-06-04 Licentia Gmbh MODULATION-Doped FIELD EFFECT TRANSISTOR
US4920076A (en) * 1988-04-15 1990-04-24 The United States Of America As Represented By The United States Department Of Energy Method for enhancing growth of SiO2 in Si by the implantation of germanium
DE3816358A1 (en) * 1988-05-13 1989-11-23 Eurosil Electronic Gmbh NON-VOLATILE STORAGE CELL AND METHOD FOR THE PRODUCTION THEREOF
US4958318A (en) * 1988-07-08 1990-09-18 Eliyahou Harari Sidewall capacitor DRAM cell
US5241197A (en) * 1989-01-25 1993-08-31 Hitachi, Ltd. Transistor provided with strained germanium layer
US5312766A (en) * 1991-03-06 1994-05-17 National Semiconductor Corporation Method of providing lower contact resistance in MOS transistors
US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US5166084A (en) * 1991-09-03 1992-11-24 Motorola, Inc. Process for fabricating a silicon on insulator field effect transistor
US5291439A (en) * 1991-09-12 1994-03-01 International Business Machines Corporation Semiconductor memory cell and memory array with inversion layer
JPH05121317A (en) * 1991-10-24 1993-05-18 Rohm Co Ltd Method for forming soi structure
US5467305A (en) * 1992-03-12 1995-11-14 International Business Machines Corporation Three-dimensional direct-write EEPROM arrays and fabrication methods
US5212110A (en) * 1992-05-26 1993-05-18 Motorola, Inc. Method for forming isolation regions in a semiconductor device
US5386132A (en) * 1992-11-02 1995-01-31 Wong; Chun C. D. Multimedia storage system with highly compact memory device
US5418743A (en) * 1992-12-07 1995-05-23 Nippon Steel Corporation Method of writing into non-volatile semiconductor memory
US5523592A (en) * 1993-02-03 1996-06-04 Hitachi, Ltd. Semiconductor optical device, manufacturing method for the same, and opto-electronic integrated circuit using the same
US5792679A (en) * 1993-08-30 1998-08-11 Sharp Microelectronics Technology, Inc. Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant
US5461243A (en) * 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US6218677B1 (en) * 1994-08-15 2001-04-17 Texas Instruments Incorporated III-V nitride resonant tunneling
US5561302A (en) * 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5777347A (en) * 1995-03-07 1998-07-07 Hewlett-Packard Company Vertical CMOS digital multi-valued restoring logic device
US5920088A (en) * 1995-06-16 1999-07-06 Interuniversitair Micro-Electronica Centrum (Imec Vzw) Vertical MISFET devices
DE19533313A1 (en) * 1995-09-08 1997-03-13 Max Planck Gesellschaft Semiconductor transistor device structure for e.g. CMOS FET
JP3403877B2 (en) * 1995-10-25 2003-05-06 三菱電機株式会社 Semiconductor memory device and manufacturing method thereof
JP3217015B2 (en) 1996-07-18 2001-10-09 インターナショナル・ビジネス・マシーンズ・コーポレーション Method for forming field effect transistor
US6191432B1 (en) * 1996-09-02 2001-02-20 Kabushiki Kaisha Toshiba Semiconductor device and memory device
US6399970B2 (en) * 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US5847419A (en) * 1996-09-17 1998-12-08 Kabushiki Kaisha Toshiba Si-SiGe semiconductor device and method of fabricating the same
EP0838858B1 (en) * 1996-09-27 2002-05-15 Infineon Technologies AG CMOS integrated circuit and method of manufacturing the same
US5780922A (en) * 1996-11-27 1998-07-14 The Regents Of The University Of California Ultra-low phase noise GE MOSFETs
US5808344A (en) * 1996-12-13 1998-09-15 International Business Machines Corporation Single-transistor logic and CMOS inverters
EP0867701A1 (en) 1997-03-28 1998-09-30 Interuniversitair Microelektronica Centrum Vzw Method of fabrication of an infrared radiation detector and more particularly an infrared sensitive bolometer
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
DE19720008A1 (en) * 1997-05-13 1998-11-19 Siemens Ag Integrated CMOS circuit arrangement and method for its production
CA2295069A1 (en) * 1997-06-24 1998-12-30 Eugene A. Fitzgerald Controlling threading dislocation densities in ge on si using graded gesi layers and planarization
US5936274A (en) * 1997-07-08 1999-08-10 Micron Technology, Inc. High density flash memory
US5981400A (en) * 1997-09-18 1999-11-09 Cornell Research Foundation, Inc. Compliant universal substrate for epitaxial growth
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US6154475A (en) * 1997-12-04 2000-11-28 The United States Of America As Represented By The Secretary Of The Air Force Silicon-based strain-symmetrized GE-SI quantum lasers
JP3447939B2 (en) * 1997-12-10 2003-09-16 株式会社東芝 Nonvolatile semiconductor memory and data reading method
FR2773177B1 (en) * 1997-12-29 2000-03-17 France Telecom PROCESS FOR OBTAINING A SINGLE-CRYSTAL GERMANIUM OR SILICON LAYER ON A SILICON OR SINGLE-CRYSTAL GERMANIUM SUBSTRATE, RESPECTIVELY, AND MULTILAYER PRODUCTS OBTAINED
US6013134A (en) * 1998-02-18 2000-01-11 International Business Machines Corporation Advance integrated chemical vapor deposition (AICVD) for semiconductor devices
US6689211B1 (en) * 1999-04-09 2004-02-10 Massachusetts Institute Of Technology Etch stop layer system
JP4258034B2 (en) * 1998-05-27 2009-04-30 ソニー株式会社 Semiconductor device and manufacturing method of semiconductor device
JP3403076B2 (en) * 1998-06-30 2003-05-06 株式会社東芝 Semiconductor device and manufacturing method thereof
US6130453A (en) * 1999-01-04 2000-10-10 International Business Machines Corporation Flash memory structure with floating gate in vertical trench
US6162688A (en) 1999-01-14 2000-12-19 Advanced Micro Devices, Inc. Method of fabricating a transistor with a dielectric underlayer and device incorporating same
JP4511739B2 (en) 1999-01-15 2010-07-28 ザ リージェンツ オブ ザ ユニヴァーシティ オブ カリフォルニア Polycrystalline silicon germanium films for forming microelectromechanical systems
US6074919A (en) 1999-01-20 2000-06-13 Advanced Micro Devices, Inc. Method of forming an ultrathin gate dielectric
US6350993B1 (en) * 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
JP3595718B2 (en) * 1999-03-15 2004-12-02 株式会社東芝 Display element and method of manufacturing the same
US6103559A (en) 1999-03-30 2000-08-15 Amd, Inc. (Advanced Micro Devices) Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication
US6251755B1 (en) * 1999-04-22 2001-06-26 International Business Machines Corporation High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe
US6151248A (en) * 1999-06-30 2000-11-21 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6204529B1 (en) * 1999-08-27 2001-03-20 Hsing Lan Lung 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate
US6339232B1 (en) * 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
US6559040B1 (en) * 1999-10-20 2003-05-06 Taiwan Semiconductor Manufacturing Company Process for polishing the top surface of a polysilicon gate
US6249022B1 (en) * 1999-10-22 2001-06-19 United Microelectronics Corp. Trench flash memory with nitride spacers for electron trapping
US6551399B1 (en) * 2000-01-10 2003-04-22 Genus Inc. Fully integrated process for MIM capacitors using atomic layer deposition
DE10025264A1 (en) * 2000-05-22 2001-11-29 Max Planck Gesellschaft Field effect transistor based on embedded cluster structures and method for its production
JP3546169B2 (en) * 2000-05-26 2004-07-21 三菱重工業株式会社 Semiconductor device and manufacturing method thereof
JP2004519090A (en) * 2000-08-07 2004-06-24 アンバーウェーブ システムズ コーポレイション Gate technology for strained surface channel and strained buried channel MOSFET devices
WO2002047168A2 (en) * 2000-12-04 2002-06-13 Amberwave Systems Corporation Cmos inverter circuits utilizing strained silicon surface channel mosfets
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
KR100391988B1 (en) * 2001-02-09 2003-07-22 삼성전자주식회사 DRAM cell and fabrication method thereof
US6724008B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6646322B2 (en) * 2001-03-02 2003-11-11 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6723661B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6348407B1 (en) * 2001-03-15 2002-02-19 Chartered Semiconductor Manufacturing Inc. Method to improve adhesion of organic dielectrics in dual damascene interconnects
US6531324B2 (en) * 2001-03-28 2003-03-11 Sharp Laboratories Of America, Inc. MFOS memory transistor & method of fabricating same
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US6468869B1 (en) * 2001-05-11 2002-10-22 Macronix International Co., Ltd. Method of fabricating mask read only memory
US6900094B2 (en) * 2001-06-14 2005-05-31 Amberwave Systems Corporation Method of selective removal of SiGe alloys
US7301180B2 (en) * 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US6916727B2 (en) * 2001-06-21 2005-07-12 Massachusetts Institute Of Technology Enhancement of P-type metal-oxide-semiconductor field effect transistors
US6974735B2 (en) * 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US6541321B1 (en) * 2002-05-14 2003-04-01 Advanced Micro Devices, Inc. Method of making transistors with gate insulation layers of differing thickness
US7169226B2 (en) * 2003-07-01 2007-01-30 International Business Machines Corporation Defect reduction by oxidation of silicon

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0587520A1 (en) * 1992-08-10 1994-03-16 International Business Machines Corporation A SiGe thin film or SOI MOSFET and method for making the same
EP0683522A2 (en) * 1994-05-20 1995-11-22 International Business Machines Corporation CMOS with strained Si/SiGe layers
JP2000031491A (en) * 1998-07-14 2000-01-28 Hitachi Ltd Semiconductor device, its manufacture, semiconductor substrate and its manufacture

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
WO2002071488A1 (en) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits
WO2002071493A3 (en) * 2001-03-02 2002-12-27 Amberwave Systems Corp Relaxed silicon germanium platform for high speed cmos electronics and high speed analog
US6593641B1 (en) 2001-03-02 2003-07-15 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6646322B2 (en) 2001-03-02 2003-11-11 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
WO2002071493A2 (en) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6900103B2 (en) 2001-03-02 2005-05-31 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6900094B2 (en) 2001-06-14 2005-05-31 Amberwave Systems Corporation Method of selective removal of SiGe alloys
US6916727B2 (en) 2001-06-21 2005-07-12 Massachusetts Institute Of Technology Enhancement of P-type metal-oxide-semiconductor field effect transistors
US6730551B2 (en) 2001-08-06 2004-05-04 Massachusetts Institute Of Technology Formation of planar strained layers
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US7138649B2 (en) 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
US7906776B2 (en) 2001-09-24 2011-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers
US7709828B2 (en) 2001-09-24 2010-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers
US7138310B2 (en) 2002-06-07 2006-11-21 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
WO2003105221A1 (en) * 2002-06-07 2003-12-18 Amberwave Systems Corporation Cmos transistors with differentially strained channels of different thickness
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
WO2004001825A1 (en) * 2002-06-25 2003-12-31 Amberwave Systems Corporation SiGe GATE ELECTRODES ON SiGe SUBSTRATES AND METHODS OF MAKING THE SAME
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
WO2004019391A3 (en) * 2002-08-23 2004-12-02 Amberwave Systems Corp Semiconductor heterostructures having reduced dislocation pile-ups and related methods
EP1530800A2 (en) * 2002-08-23 2005-05-18 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups and related methods
EP2267762A3 (en) * 2002-08-23 2012-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor heterostructures having reduced dislocation pile-ups and related methods
WO2004021420A2 (en) * 2002-08-29 2004-03-11 Massachusetts Institute Of Technology Fabrication method for a monocrystalline semiconductor layer on a substrate
WO2004021420A3 (en) * 2002-08-29 2004-11-11 Massachusetts Inst Technology Fabrication method for a monocrystalline semiconductor layer on a substrate

Also Published As

Publication number Publication date
US20050202640A1 (en) 2005-09-15
US20070082470A1 (en) 2007-04-12
AU2001283138A1 (en) 2002-02-18
US6583015B2 (en) 2003-06-24
US20020068393A1 (en) 2002-06-06
WO2002013262A3 (en) 2002-05-02
JP2004519090A (en) 2004-06-24
US7217668B2 (en) 2007-05-15
US20030207571A1 (en) 2003-11-06
EP1307917A2 (en) 2003-05-07
US6846715B2 (en) 2005-01-25
US20020104993A1 (en) 2002-08-08

Similar Documents

Publication Publication Date Title
US6583015B2 (en) Gate technology for strained surface channel and strained buried channel MOSFET devices
US6709909B2 (en) Semiconductor device and method of manufacturing the same
US6603156B2 (en) Strained silicon on insulator structures
US6620664B2 (en) Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same
US7018882B2 (en) Method to form local “silicon-on-nothing” or “silicon-on-insulator” wafers with tensile-strained silicon
US20040173815A1 (en) Strained-channel transistor structure with lattice-mismatched zone
US20040026765A1 (en) Semiconductor devices having strained dual channel layers
EP1231643A2 (en) MOS field-effect transistor comprising Si and SiGe layers or Si and SiGeC layers as channel regions
US20080020532A1 (en) Transistor with a channel comprising germanium
JP2009105427A (en) Method of manufacturing semiconductor substrate
US7462525B2 (en) Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain
WO2005122272A1 (en) Mis field-effect transistor having strained silicon channel layer
US20050095807A1 (en) Silicon buffered shallow trench isolation for strained silicon processes
JP3712599B2 (en) Semiconductor device and semiconductor substrate
US20090302349A1 (en) Strained germanium field effect transistor and method of fabricating the same
US20210057579A1 (en) Transistor with strained superlattice as source/drain region
US20050070070A1 (en) Method of forming strained silicon on insulator
US20030235957A1 (en) Method and structure for graded gate oxides on vertical and non-planar surfaces
JP3600174B2 (en) Semiconductor device manufacturing method and semiconductor device
JP4282560B2 (en) Manufacturing method of semiconductor substrate

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2002518522

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2001961913

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2001961913

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642