WO2002071493A3 - Relaxed silicon germanium platform for high speed cmos electronics and high speed analog - Google Patents

Relaxed silicon germanium platform for high speed cmos electronics and high speed analog Download PDF

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Publication number
WO2002071493A3
WO2002071493A3 PCT/US2002/003669 US0203669W WO02071493A3 WO 2002071493 A3 WO2002071493 A3 WO 2002071493A3 US 0203669 W US0203669 W US 0203669W WO 02071493 A3 WO02071493 A3 WO 02071493A3
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WIPO (PCT)
Prior art keywords
high speed
analog
silicon germanium
relaxed silicon
cmos electronics
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Application number
PCT/US2002/003669
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French (fr)
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WO2002071493A2 (en
Inventor
Eugene A Fitzgerald
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Amberwave Systems Corp
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Filing date
Publication date
Priority claimed from US09/906,550 external-priority patent/US6593641B1/en
Priority claimed from US09/906,534 external-priority patent/US6830976B2/en
Application filed by Amberwave Systems Corp filed Critical Amberwave Systems Corp
Publication of WO2002071493A2 publication Critical patent/WO2002071493A2/en
Publication of WO2002071493A3 publication Critical patent/WO2002071493A3/en

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
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    • H01L21/02439—Materials
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    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
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    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Structures and methods for fabricating high speed digital, analog, and combined digital/analog system using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
PCT/US2002/003669 2001-03-02 2002-02-07 Relaxed silicon germanium platform for high speed cmos electronics and high speed analog WO2002071493A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US27311201P 2001-03-02 2001-03-02
US60/273,112 2001-03-02
US09/906,550 US6593641B1 (en) 2001-03-02 2001-07-16 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US09/906,534 2001-07-16
US09/906,550 2001-07-16
US09/906,534 US6830976B2 (en) 2001-03-02 2001-07-16 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits

Publications (2)

Publication Number Publication Date
WO2002071493A2 WO2002071493A2 (en) 2002-09-12
WO2002071493A3 true WO2002071493A3 (en) 2002-12-27

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PCT/US2002/003669 WO2002071493A2 (en) 2001-03-02 2002-02-07 Relaxed silicon germanium platform for high speed cmos electronics and high speed analog

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
FR2842350B1 (en) * 2002-07-09 2005-05-13 METHOD FOR TRANSFERRING A LAYER OF CONCEALED SEMICONDUCTOR MATERIAL

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0683522A2 (en) * 1994-05-20 1995-11-22 International Business Machines Corporation CMOS with strained Si/SiGe layers
JP2000031491A (en) * 1998-07-14 2000-01-28 Hitachi Ltd Semiconductor device, its manufacture, semiconductor substrate and its manufacture
GB2342777A (en) * 1998-10-16 2000-04-19 Nec Corp Gate electrodes for integrated mosfets
WO2002013262A2 (en) * 2000-08-07 2002-02-14 Amberwave Systems Corporation Gate technology for strained surface channel and strained buried channel mosfet devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0683522A2 (en) * 1994-05-20 1995-11-22 International Business Machines Corporation CMOS with strained Si/SiGe layers
JP2000031491A (en) * 1998-07-14 2000-01-28 Hitachi Ltd Semiconductor device, its manufacture, semiconductor substrate and its manufacture
GB2342777A (en) * 1998-10-16 2000-04-19 Nec Corp Gate electrodes for integrated mosfets
WO2002013262A2 (en) * 2000-08-07 2002-02-14 Amberwave Systems Corporation Gate technology for strained surface channel and strained buried channel mosfet devices

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
AUGUSTO C J R P ET AL: "Proposal for a new process flow for the fabrication of silicon-based complementary MOD-MOSFETs without ion implantation", THIN SOLID FILMS, ELSEVIER-SEQUOIA S.A. LAUSANNE, CH, vol. 294, no. 1-2, 15 February 1997 (1997-02-15), pages 254 - 258, XP004073084, ISSN: 0040-6090 *
MAITI K ET AL: "STRAINED-SI HETEROSTRUCTURE FIELD EFFECT TRANSISTORS", SEMICONDUCTOR SCIENCE AND TECHNOLOGY, INSTITUTE OF PHYSICS. LONDON, GB, vol. 13, no. 11, 1 November 1998 (1998-11-01), pages 1225 - 1246, XP000783138, ISSN: 0268-1242 *
O'NEILL A G ET AL: "SIGE VIRTUAL SUBSTRATE N-CHANNEL HETEROJUNCTION MOSFETS", SEMICONDUCTOR SCIENCE AND TECHNOLOGY, INSTITUTE OF PHYSICS. LONDON, GB, vol. 14, no. 9, September 1999 (1999-09-01), pages 784 - 789, XP000850219, ISSN: 0268-1242 *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 04 31 August 2000 (2000-08-31) *

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