WO2001088230A1

WO2001088230A1 - Silicon single-crystal wafer manufacturing method, silicon single-crystal wafer, and epitaxial wafer

Info

Publication number: WO2001088230A1
Application number: PCT/JP2001/003946
Authority: WO
Inventors: Makoto Iida; Masahiro Kato; Akihiro Kimura
Original assignee: Shin-Etsu Handotai Co.,Ltd.
Priority date: 2000-05-17
Filing date: 2001-05-11
Publication date: 2001-11-22
Also published as: TWI282379B; JP4296740B2

Abstract

A silicon single-crystal wafer manufacturing method for manufacturing a silicon single-crystal wafer from a silicon single-crystal rod which is so pulled upper so that when a silicon single crystal having a diameter of 300 mm or more is grown by the Czochralski method, at least the central portion of the crystal may be a V-rich region and the cooling rate of the temperature band of 1,000 to 900 º may be 1.25 º/min or less, and an epitaxial wafer having a substrate made of the wafer. To grow a single crystal by the Cz method, therefore, there is established a growing method which causes no small dislocation loop within a diameter of 300 mm or more, thereby providing an epitaxial wafer which has no crystal defect in an epitaxial layer even if the silicon single-crystal wafer is subjected to epitaxial growth.

Description

Description: Manufacturing method of silicon single crystal wafer and silicon single crystal wafer

And Epitaxyanoreja Technical Field

The present invention relates to a silicon single crystal wafer having a small number of crystal defects and a method for producing the same, and in particular, a silicon single crystal wafer having a large diameter of 300 mm or more, a method for producing the same, and the wafer as a substrate. Regarding epitaxy. Background art

As devices become more highly integrated and miniaturized, there is a strong demand for high-performance wafers. On the other hand, conventionally, an epitaxial silicon single crystal wafer (hereinafter simply referred to as silicon wafer), in which an epitaxial layer is grown on a silicon single crystal wafer (hereinafter sometimes simply referred to as silicon wafer). (Sometimes called epitaxy).

In addition, the diameter of the crystal has been increasing to reduce the cost of the depiling process. At present, the diameter of the crystal is 300 mm, and even a diameter of 400 mm is being manufactured and prototyped. There is also a high demand for quality for such large diameter wafers, and large diameter epitaxial wafers are also being manufactured.

By the way, an epitaxy wafer was formed by forming an epitaxy layer (hereinafter sometimes simply referred to as an epi layer) on a silicon wafer having a diameter of 300 mm or more, and the epitaxy layer was investigated. However, such a large-diameter epitaxial wafer having a diameter of 300 mm or more has a problem in that defects that were not apparent in an epitaxial wafer having a diameter of up to 200 mm may occur. I got it.

When this defect is measured with a particle counter on the surface of the epi layer, a 0.09 μm or more LPD (Light Point Defect: a bright spot defect that is observed with an wafer surface inspection device using laser light) About 1) crystal defects It is said that there are about 100 Z-diameters of about 30 Omm ゥ a (about 140 pieces of 100 cm ² ). As a result of observation under a microscope, many of these defects are formed in the epi layer. It was found that the dislocation loop was formed. It is generally known that the presence of such crystal defects on the surface of the epi layer adversely affects devices, such as deteriorating leakage characteristics.

Therefore, the present inventors conducted intensive research on the defects formed in these epi layers. As a result, it was confirmed that microscopic dislocation loops existed at a certain density on the surface of the substrate for epitaxy growth at the location where such an epilayer defect was generated. In a normal substrate with a diameter of 200 mm or less, such defects found on the substrate surface are generated in the I-rich region of the low-speed grown crystal with a reduced pulling speed, and are subjected to selective etching (eg, seco etching). For example, these are observed by non-stirring seco etching used in FPD evaluation) and copper decoration methods. The size of the observed defects is very large, and the size is at least 1 μμπι or more. Also called.

However, the epitaxy growth substrate that had generated dislocation loops in the epitaxy wafer of 300 mm or more was not a substrate made from a low-speed growth crystal, but was obviously a high-speed growth. Some of them were grown in the touch area. Similar to the above, defects were observed by selective etching such as Secco etching (for example, non-stirred Secco etching used for FPD evaluation) and copper decoration method. Is observed as an etch pit in the shape of a droplet of about 5 μm when non-stirred seco etching is performed with an etch-off amount of about 30 μm on one side, and it is impossible to exceed 10 μm at the maximum. And smaller than those present in the I-rich region of the substrate of 200 mm or less. Such defects were very slight, even on substrates up to 200 mm in diameter. However, due to its extremely low density, even when epi growth was performed, it was hardly noticeable and had no problem at all. However, it became clear that when the diameter was 30 O mm or more, such defects were generated at a higher density.

Here, the relationship between the CZ method (Czochralski Method) crystal pulling conditions and the growth-in (Grownin) defect region is described. I will explain.

First, when a CZ silicon single crystal is pulled, the point defects incorporated into the crystal include atomic vacancies (Vacancy) and interstitial silicon (Interstitial — Si). It is known that the concentration of is determined by the relationship (V / G) between the crystal pulling rate V (growth rate) and the temperature gradient G near the solid-liquid interface in the crystal. In a silicon single crystal, a region where many vacancies are taken in is called a V-rich region, and there are many void-type green-in defects due to lack of silicon atoms. I do. On the other hand, the region in which a large amount of interstitial silicon is incorporated is called an I_rich region, and many defects such as dislocation clusters exist due to dislocations caused by the presence of extra silicon atoms.

It is known that there is an N region (Neutra 1 region) between the V-rich region and the I-rich region, which has a shortage of atoms and a small number of atoms. Among them, there is an OSF region (also called an OSF ring region, also called a ring OSF region) in which oxidation induced stacking faults (hereinafter, abbreviated as OSF) occur in a ring shape. Confirmed.

FIG. 2 schematically shows a distribution diagram of a green-in defect region when the vertical axis is the crystal pulling speed and the horizontal axis is the distance from the crystal center. The distribution of this defect region can be changed by adjusting the crystal pulling conditions and the structure inside the furnace of the crystal growth apparatus (hot zone: Hot Z one: HZ) and controlling the VNO G. You.

As can be seen from Fig. 2, in general, the OSF region moves toward the outer periphery of the crystal by increasing the pulling speed of the crystal, and eventually disappears from the outer periphery of the crystal, and the entire surface becomes a crystal in the V-rich region. . Conversely, when the pulling speed is reduced, the OSF region moves toward the center of the crystal, and eventually disappears at the center of the crystal, and passes through the N region to become a crystal of the entire I-rich region. It has been reported that when nitrogen is doped, the width of the OSF region and the N region and the boundary position of the region change. (Proceedings of the 46th Applied Physics Joint Lecture Meeting, Spring 1997) No.1, .471, 29a ZB-9, Iida et al.). Therefore, when controlling the OSF region in a nitrogen-doped crystal, this nitrogen-doped crystal growth What is necessary is just to refer to the relationship between the VZG at the time of formation and the defect area distribution.

In addition, as described in Japanese Patent Application No. 11-92453 filed earlier by the applicant of the present application, even in the case of a V-lithic region of a CZ crystal having a diameter of 200 mm or less, It has been confirmed that a crystal with nitrogen doping has a small dislocation loop that generates an epi defect as seen in the crystal having a diameter of 300 mm or more. However, it is the first knowledge obtained by the present inventors that many such small dislocation loops are generated in the V-rich region of a nitrogen-doped CZ crystal. Disclosure of the invention

Therefore, the present invention has been made in view of such a problem. In growing a CZ single crystal, in the case of nitrogen non-doping, micro dislocation loops do not occur up to a diameter of 200 mm. Investigate the causes that occur at 0 mm or more, establish a growth method that can suppress the generation of crystal defects, and crystal defects that occur in the epitaxial layer when epitaxially growing silicon single crystal wafers obtained from this. It is a main object of the present invention to provide a method for producing a silicon single crystal wafer capable of suppressing the occurrence of a silicon single crystal wafer, and a silicon single crystal wafer and an epitaxial wafer produced therefrom.

In order to solve the above-mentioned problems, the method for producing a silicon single crystal wafer according to the present invention is characterized in that, when growing a silicon single crystal having a diameter of 30 O mm or more by the Czochralski method, at least the center position of the crystal is adjusted. A silicon single crystal rod is drawn from the silicon single crystal rod, which is in the V-rich region and whose cooling rate in the temperature range of 1000 to 900 ° C is pulled up to 1.25 ° C / min or less. (4) It is characterized in that an e-ha is manufactured.

In this way, in the conventional method of growing nitrogen non-doped, it is possible to almost suppress the occurrence of dislocation loops generated at a high density when the diameter is 300 mm or more. —In the rich region, a silicon single crystal wafer with a dislocation loop free diameter of 300 mm or more can be manufactured. In this case, the silicon single crystal wafer can be used as an epitaxial growth wafer.

As described above, the silicon crystal wafer of the present invention is suitable for epitaxial growth. It is an extremely effective substrate. Therefore, if an epi layer is formed on the wafer, a high-quality epitaxy wafer without deteriorating the leak characteristics and the like for a device having no epi defects can be easily manufactured at low cost. be able to.

The silicon single crystal wafer according to the present invention is a silicon single crystal wafer having a V-rich region and a diameter of 30 Omm or more, which is grown by the Czochralski method, wherein the dislocation loop has an entire surface of the silicon wafer. It is characterized by not being present.

As described above, the wafer of the present invention is a high-quality silicon single crystal wafer in which dislocation loops are not present on the entire surface of the wafer even when the diameter grown by the CZ method is 300 mm or more.

In this case, the silicon single crystal wafer can be used as an epitaxial growth wafer.

Thus, a silicon single crystal wafer having a V-rich region and having no dislocation loops over the entire surface of the wafer is a very effective substrate for epitaxial growth.

According to the present invention, there is provided an epitaxy wafer in which an epitaxy layer having no epi defects is formed on the surface of the silicon single crystal wafer.

Further, according to the present invention, an epitaxy wafer formed by the Czochralski method and having an epitaxy layer formed on the surface of a silicon single crystal wafer having a diameter of 300 mm or more and having a V-rich region. The present invention provides an epitaxy wafer having an extremely small number of crystal defects having an LPD density of 0.09 m or more observed on the epitaxy layer of 4.3 pieces / 100 cm ² or less.

As described above, the epitaxial wafer of the present invention has an epitaxial layer in which a crystal center is a V-rich region and dislocation loops do not exist on the entire surface of the silicon. An epitaxy wafer having extremely few epi defects on its surface, and capable of providing an extremely high quality epitaxy wafer for a device without deteriorating the leak characteristics and the like with high yield and high productivity.

As described above, according to the present invention, when growing a CZ method single crystal, in the case of a nitrogen pump, it does not occur up to a diameter of 200 mm, but occurs at a diameter of 300 mm or more. I The formation of micro dislocation loops can be suppressed, and even if epitaxy is performed on silicon single crystal wafers obtained from this, high-quality epitaxy that suppresses the occurrence of dislocation loops, PD crystal defects, etc. in the epitaxy layerゥ Each can be manufactured. Therefore, it is possible to provide an epitaxial wafer without deteriorating leak characteristics and the like for a device, with high productivity and high yield. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic explanatory view of a single crystal pulling apparatus by the CZ method used in the present invention. Fig. 2 is a distribution diagram of a grown-in defect region in a silicon single crystal where the horizontal position is the radial position of the crystal and the vertical axis is the crystal pulling rate (non-doped nitrogen crystal).

FIG. 3 is a result diagram showing the relationship between the length from the crystal shoulder and the dislocation loop density. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described in detail, but the present invention is not limited thereto.

In the present invention, when growing a silicon single crystal with nitrogen non-doping by the CZ method, the micro dislocation loop as described above does not occur up to a diameter of 200 mm, but occurs at a diameter of 300 mm or more. The cause was changed from the viewpoint of the thermal history of the pulled crystal.

As a result, the growth of a crystal with a diameter of 300 mm or more is more than that of a conventional crystal with a diameter of up to 200 mm due to the structure of the pulling champ and HZ. It was presumed that the high cooling rate was the cause in the following low-temperature part.

Therefore, we investigated which temperature zone, especially in the low-temperature region, is involved in the formation of such a small dislocation loop. The method is to change the pulling speed suddenly. Specifically, in growing this crystal, after raising the straight body from the shoulder to 60 cm from the shoulder at a pulling speed of 1.0 mm / min, the crystal tail was cut at the same speed to separate it from the melt. After rounding, the winding speed is 0.5 mm from the position where the crystal is cut off. No: min was wound up by 40 cm.

By pulling up in this way, crystals with different cooling temperature ranges can be obtained depending on the position of the straight body. Then, a wafer was cut out from each part of the crystal, Seccoetching was performed, and a small dislocation loop was evaluated. The position of the temperature band of about 1000 to 900 ° C (42 to 46 from the crystal shoulder) (cm position), the defect density changed greatly, and as the cooling rate was slower, dislocation loops did not occur (see Fig. 3). Thus, a temperature zone effective for reducing the small dislocation loop was confirmed. Also, the temperature width of about 100 ° C corresponds to the crystal length of 4 cm, and the interval between them is wound up at 0.5 mm / min. The transit time is about 80 minutes, and the cooling rate is about 1.25 ° CZm i II. Therefore, it was found that the micro dislocation loop could be reduced by setting the cooling rate in this temperature range to 1.25 ° C / min or less. The lower limit of the cooling rate is not particularly limited as long as at least the center of the crystal is in the V-rich region, but is practically about 0.4 ° C / min.

Next, the general pulling conditions of conventional nitrogen non-doped crystals up to a diameter of 200 mm with little occurrence of small dislocation loops in the V-rich region were investigated. It was found that the transit time in the temperature zone of ° C required about 80 minutes even at the fastest. Therefore, as a condition for preventing the generation of small dislocation loops in the V-rich region, the cooling rate in the temperature range of 1000 to 900 ° C is set to about 1 · 25 ° CZ (100 ° CZ). (° C / 80 min) It was confirmed that the following conditions should be satisfied.

Therefore, in the case of growing a crystal having a diameter of 300 mm or more, an attempt was made to grow a single crystal by applying these pulling conditions. In the upper space of the HZ of the single crystal pulling device, install a heat insulating material of an appropriate size and do not wind it up immediately after growing the crystal, and the cooling rate in the temperature range of 100 to 900 ° C is 1. When the crystal was grown under the conditions of 25 ° C / min or less, it was found that no microscopic dislocation loops occurred.

Hereinafter, the present invention will be described in detail with reference to the drawings.

First, a schematic configuration example of an apparatus for pulling a single crystal by the CZ method used in the present invention will be described with reference to FIG.

As shown in FIG. 1, the single crystal pulling apparatus 30 includes a pulling chamber 31 and a pulling chamber 31. A crucible 32 provided in the crucible 32, a heater 34 disposed around the crucible 32, a crucible holding shaft 33 for rotating the crucible 32, and a rotation mechanism thereof (not shown); A seed chuck 6 for holding the seed crystal 5, a wire 7 for pulling up the seed chuck 6, and a winding mechanism (not shown) for rotating or winding the wire 7 are provided. The crucible 32 is provided with an English crucible on the inner side for containing the silicon melt (hot water) 2 and a graphite crucible on the outer side. Further, a heat insulating material 35 is disposed around the outside of the heater 34.

Further, in order to set the manufacturing conditions relating to the manufacturing method of the present invention, an annular solid-liquid interface heat insulator 8 is provided on the periphery of the solid-liquid interface 4 of the crystal, and an upper surrounding heat insulator 9 is disposed thereon. I have. The solid-liquid interface heat insulating material 8 is provided with a small gap 10 between its lower end and the molten metal surface 3 of the silicon melt 2. The upper surrounding insulation 9 may not be used depending on the conditions. Further, a cylindrical cooling device (not shown) that blows a cooling gas or blocks radiant heat to cool the single crystal may be provided. Separately, recently, a magnet (not shown) is installed outside the pulling chamber 31 in the horizontal direction, and a magnetic field in the horizontal or vertical direction is applied to the silicon melt 2 to suppress the convection of the melt. The so-called MCZ method for stable growth of single crystals is often used.

Hereinafter, the present invention will be described specifically with reference to Examples and Comparative Examples of the present invention, but the present invention is not limited thereto.

(Example 1)

Using the pulling device shown in Fig. 1, a raw material polycrystalline silicon is charged into a 32 inch (800 mm) quartz crucible, and the diameter is 300 mm, the orientation is <100>, and the conductivity type is p-type. A plurality of silicon single crystal rods 1 for producing silicon single crystal wafers were pulled up (no nitrogen doping).

Before the actual pulling, the pulling experiment was repeated by changing the position and size of the upper surrounding heat insulating material 9 installed in the upper space of the HZ, and the pulling speed was 100 mm0 min at 100 mm0 min. The HZ was set so that the cooling rate in the 900 ° C temperature zone was 1.25 ° C / min.

30 Omm diameter silicon single bond from each of the pulled silicon single crystal rods A crystal wafer was cut out to produce a mirror-polished wafer. In order to confirm the grown-in defects and dislocation loops of the fabricated mirror-surface silicon single crystal wafer, the silicon single crystal wafer was subjected to non-stirring seco etching, and then observed using an electron microscope. As a result, many void-type defects were observed and it was confirmed that the entire region was in a V-rich region, but no dislocation loop was observed on the surface of the wafer.

Next, a plurality of epitaxy wafers having a 3 μπι epitaxy layer formed on the surface of these wafers at 112 ° C were manufactured, and a surface inspection device SP 1 (trade name of KLA-Tencor Corporation) was manufactured. Using this, LPDs with a size of 0.09 μm or more were measured. As a result, the LPD density was an average of 30 pieces and a Z diameter of 300 mm ゥ a wafer (0.0425 pieces Zcm ² = 4.3 pieces ZOO cm ² ).

Thus, it can be seen that the LPD density on the epi layer can be greatly improved by setting the cooling rate in the temperature range of 1000 to 900 ° C to 1.25 ° C / min or less. In particular, if the cooling rate is further reduced more than 1.25 ° CZ, the number of defects is further reduced from 4.3 pieces / 100 cm ² .

(Comparative Example 1)

Using the same pulling device as in Example 1, the HZ was set so that the pulling speed was 1.OmmZmin and the cooling rate in the temperature range of 1000 to 900 ° C was 1.3, which was more than one minute. Then, several silicon single crystal rods were pulled up.

A silicon single crystal wafer was fabricated from each of the pulled silicon single crystal rods, an epitaxy wafer was fabricated under the same conditions as in Example 1, and an LPD of at least 0.09 ΐ η was measured. As a result, 100 or more LPDs were observed on the entire surface of the wafer (diameter: 300 mm) for each wafer. Note that the present invention is not limited to the above embodiment. The above embodiment is an exemplification, and has substantially the same configuration as the technical idea described in the claims of the present invention. It is included in the technical scope of the invention.

For example, in the above-described embodiment, the Czochralski method (CZ method) Although the case of growing a single crystal of silicon has been described with reference to an example, the present invention is not limited to this, and the so-called McZ method of applying a horizontal magnetic field, a vertical magnetic field, a cusp magnetic field, or the like to the silicon melt can be used. It goes without saying that it can be applied.

In addition, the present invention is applicable regardless of the conductivity type, resistivity, oxygen concentration, etc. of the single crystal as long as the diameter of the silicon single crystal (ゥ wafer) is 300 mm or more and the cooling rate is a predetermined value or less. Further, the present invention can be similarly applied to, for example, a silicon single crystal doped with carbon to promote oxygen precipitation.

Claims

The scope of the claims

1. When growing a silicon single crystal with a diameter of 30 O mm or more by the Czochralski method, at least the center position of the crystal becomes a V-rich region, and 100 to 900 °. the C rate of cooling temperature zone 1. 2 5 ° C _{/ /} min Ass co down single crystal ingot was pulled as to become the following silicon single crystal Ueha, characterized in that to produce the silicon single crystal Ueha Production method.

2. The method for producing a silicon single crystal wafer according to claim 1, wherein the silicon single crystal wafer is an epitaxial growth wafer. .

3. A silicon single crystal silicon wafer having a V-rich region and a diameter of 300 mm or more grown by the Czochralski method, wherein dislocation loops do not exist on the entire surface of the silicon wafer. Crystal @ eha.

4. The silicon single crystal wafer according to claim 3, wherein the silicon single crystal wafer is an epitaxial growth wafer.

5. An epitaxy wafer wherein the epitaxy layer is formed on the surface of the silicon single crystal as described in claim 3 or claim 4.

6. An epitaxy wafer formed by the Czochralski method and having a V-rich region and a silicon single crystal wafer having a diameter of at least 300 mm and an epitaxy layer formed on the surface of the epitaxy layer. E Pi Taki shear Honoré © er Roh, characterized in that LPD density of 0. 0 9 / xm or size to be observed 4. is three 1 0 0 cm ² or less.