JP4296740B2 - Manufacturing method of silicon single crystal wafer, silicon single crystal wafer and epitaxial wafer - Google Patents

Description

TECHNICAL FIELD The present invention relates to a silicon single crystal wafer having few crystal defects and a method for manufacturing the same, and more particularly to a silicon single crystal wafer having a large diameter of 300 mm or more, a method for manufacturing the same, and an epitaxial wafer using the wafer as a substrate.
With the high integration and miniaturization of background technology devices, there is a strong demand for high-performance wafers. On the other hand, an epitaxial silicon single crystal wafer obtained by growing an epitaxial layer on a silicon single crystal wafer (hereinafter sometimes simply referred to as a silicon wafer or a wafer) (hereinafter sometimes simply referred to as a silicon epitaxial wafer or an epitaxial wafer). Is being used.
In addition, the diameter of the crystal has been increased to reduce the cost of the device process. At present, a crystal having a diameter of 300 mm and further a diameter of 400 mm has been manufactured and prototyped. Even for such a large-diameter wafer, the demand for quality is high, and a large-diameter epitaxial wafer is also manufactured.
By the way, when an epitaxial wafer in which an epitaxial layer (hereinafter sometimes referred to simply as an epi layer) is formed on a silicon wafer having a diameter of 300 mm or more is fabricated and the epitaxial layer is investigated, such a diameter of 300 mm or more is obtained. It has been found that large-diameter epitaxial wafers have a problem that defects that have not been manifested in epitaxial wafers up to 200 mm occur.
When the epilayer surface is measured with a particle counter, this defect is approximately about 0.09 μm size LPD (Light Point Defect: a general term for bright spot defects observed with a wafer surface inspection apparatus using laser light). There are about 100 wafers / 300 mm diameter wafers (about 14/100 cm ² ). As a result of magnifying observation with a microscope, it was found that most of these defects were dislocation loops formed in the epilayer. . In general, it is known that when such crystal defects exist on the surface of the epi layer, the device has an adverse effect such as deterioration of leakage characteristics.
Therefore, the present inventors conducted extensive investigations on defects formed in these epi layers. As a result, it was confirmed that minute dislocation loops were present at a certain density on the surface of the substrate for epitaxial growth at the position where such defects in the epi layer were generated. In a normal substrate having a diameter of 200 mm or less, such defects appearing on the surface of the substrate are generated in the I-rich region of the slow-growing crystal with a reduced pulling rate, and selective etching such as seco etching (for example, evaluation of FPD) The size of the observed defect is very large, which is at least 10 μm or more, and is also called a dislocation cluster.
However, some epitaxial growth substrates in which dislocation loops have been generated in an epitaxial wafer of 300 mm or more are not grown from a low-speed grown crystal, but are grown in a V-rich region, which is clearly a high-speed growth. Similar to the above, defects are observed by selective etching such as Secco etching (for example, non-stirring Secco etching used for evaluation of FPD) and copper decoration method, but the size of the defect is not stirred with an etch-off amount of about 30 μm on one side It is observed as an etch pit having a droplet shape of about 5 μm when Secco etching is performed, does not exceed 10 μm at the maximum, and is smaller than that present in the I-rich region of a substrate of 200 mm or less. I understood it. Such defects were observed only slightly even on substrates up to 200 mm in diameter. However, since its density is extremely low, it was hardly noticeable even when epi-growth was performed, and it was not a problem at all. However, it has become clear that such defects occur at a higher density when the diameter is 300 mm or more.
Here, the relationship between the pulling condition of the CZ method (Czochralski method) crystal and the grown-in defect region will be described.
First, when pulling up a CZ silicon single crystal, the point defects taken into the crystal include atomic vacancies and interstitial silicon (Interstitial-Si). It is known that it is determined from the relationship (V / G) between the pulling rate V (growth rate) of the crystal and the temperature gradient G near the solid-liquid interface in the crystal. In a silicon single crystal, a region in which many atomic vacancies are taken in is called a V-rich region, and there are many void-type grow-in defects due to a shortage of silicon atoms. On the other hand, a region where a large amount of interstitial silicon is taken in is called an I-rich region, and there are many defects such as dislocation clusters due to dislocations generated by the presence of extra silicon atoms.
Further, it is known that an N region (neutral region) with a shortage of atoms and a small excess exists between the V-rich region and the I-rich region, and further, oxidation-induced stacking faults are present in the N region. The existence of an OSF region (also referred to as an OSF ring region or a ring OSF region) in which a ring-shaped (Oxidation-Induced Stacking Fault: hereinafter abbreviated as OSF) has been confirmed.
FIG. 2 schematically shows a distribution map of a grown-in defect region where the vertical axis is the crystal pulling speed and the horizontal axis is the distance from the crystal center. The distribution shape of the defect region can be changed by controlling V / G by adjusting the crystal pulling conditions, the in-furnace structure of the crystal growth apparatus (hot zone: HZ), and the like.
As can be seen from FIG. 2, generally, the OSF region moves toward the outer periphery of the crystal by increasing the pulling speed of the crystal, and eventually disappears from the outer periphery of the crystal, so that the entire surface becomes a V-rich region crystal. On the other hand, when the pulling rate is lowered, the OSF region moves toward the center of the crystal, eventually disappears at the center of the crystal, and becomes an entire I-rich region crystal through the N region. In addition, it has been reported that, when nitrogen is doped, the width of the OSF region and the N region and the boundary position of the region change (No. 1, p. 471, 29aZB-9, Iida et al.). Therefore, when controlling the OSF region in a nitrogen-doped crystal, the relationship between the V / G and the defect region distribution during the growth of the nitrogen-doped crystal may be referred to.
In addition, as described in Japanese Patent Application No. 11-294523 filed earlier by the applicant of the present application, even if it is a V-rich region of a CZ crystal having a diameter of 200 mm or less, if the crystal is doped with nitrogen, the above It has been confirmed that there are minute dislocation loops that cause epi defects as found in crystals of 300 mm or more. However, the fact that many such dislocation loops are generated in the V-rich region of a nitrogen-non-doped CZ crystal is a knowledge obtained for the first time by the present inventors.
DISCLOSURE OF THE INVENTION Accordingly, the present invention has been made in view of such problems, and in the case of nitrogen non-doping when growing a CZ method single crystal, a small dislocation loop does not occur up to a diameter of 200 mm, and is 300 mm or more. Investigate the cause of the occurrence, establish a growth method that can suppress the generation of crystal defects, and when performing epitaxial growth on the resulting silicon single crystal wafer, a silicon single crystal that can suppress crystal defects generated in the epitaxial layer The main object is to provide a method of manufacturing a wafer and a silicon single crystal wafer and an epitaxial wafer manufactured therefrom.
In order to solve the above problems, the method for producing a silicon single crystal wafer according to the present invention, when growing a silicon single crystal having a diameter of 300 mm or more by the Czochralski method, at least the center position of the crystal becomes a V-rich region, In addition, a silicon single crystal wafer is produced from a silicon single crystal rod pulled up so that the cooling rate in the temperature range of 1000 to 900 ° C. is 1.25 ° C./min or less.
In this way, in the conventional nitrogen non-doping growth method, the generation of dislocation loops generated at a high density can be suppressed when the diameter is 300 mm or more, and at least the center position of the wafer is the V-rich region. A silicon single crystal wafer having a diameter of 300 mm or more without dislocation loops can be produced.
In this case, this silicon single crystal wafer can be used as a wafer for epitaxial growth.
Thus, the silicon nest crystal wafer of the present invention is a very effective substrate for epitaxial growth. Therefore, if an epitaxial layer is formed on the wafer, a high-quality epitaxial wafer can be easily produced at low cost without deteriorating leakage characteristics and the like for devices having no epi defects.
The silicon single crystal wafer according to the present invention is a silicon single crystal wafer having a diameter of 300 mm or more having a V-rich region grown by the Czochralski method, wherein dislocation loops do not exist on the entire surface of the wafer. Yes.
As described above, the wafer of the present invention is a high-quality silicon single crystal wafer in which dislocation loops do not exist on the entire surface of the wafer even when the diameter grown by the CZ method is 300 mm or more.
In this case, this silicon single crystal wafer can be used as a wafer for epitaxial growth.
As described above, a silicon single crystal wafer having a V-rich region and having no dislocation loop on the entire surface of the wafer is a very effective substrate for epitaxial growth.
And according to this invention, the epitaxial wafer which formed the epitaxial layer without an epi defect on the surface of the said silicon single crystal wafer is provided.
Furthermore, according to the present invention, there is provided an epitaxial wafer formed by a Czochralski method and having an epitaxial layer formed on the surface of a silicon single crystal wafer having a V-rich region and having a diameter of 300 mm or more, which is observed on the epitaxial layer. An epitaxial wafer having a very low crystal defect in which the LPD density of 0.09 μm size or more is 4.3 pieces / 100 cm ² or less is provided.
Thus, the epitaxial wafer of the present invention has very few epi defects on the surface of the epitaxial layer in which the epitaxial layer is formed on the surface of the silicon single crystal wafer in which the crystal center is the V-rich region and the dislocation loop does not exist on the entire wafer surface. It is an epitaxial wafer that can provide an extremely high quality epitaxial wafer with high yield and high productivity without deteriorating leakage characteristics and the like for devices.
As described above, according to the present invention, in the case of growing a CZ method single crystal, in the case of nitrogen non-doping, it does not occur up to a diameter of 200 mm but suppresses the occurrence of a micro dislocation loop that occurs at 300 mm or more. Even if the silicon single crystal wafer obtained from this is epitaxially grown, a high-quality epitaxial wafer in which generation of dislocation loops, LPD crystal defects, and the like is suppressed in the epitaxial layer can be produced. Therefore, it is possible to provide an epitaxial wafer for a device that does not deteriorate the leakage characteristics and the like with high productivity and high yield.
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail, but the present invention is not limited thereto.
In the present invention, when a silicon single crystal is grown by nitrogen non-doping by the CZ method, the above-described micro dislocation loop does not occur up to a diameter of 200 mm but occurs at a diameter of 300 mm or more. Considered from the viewpoint of heat history of.
As a result, the general growth of crystals with a diameter of 300 mm or more means that, due to the structure of the pulling chamber and the HZ, the cooling rate is faster in the low temperature side portion of 1000 ° C. or lower than the conventional crystals with a diameter of 200 mm or less. It was inferred that this is part of the reason.
Therefore, we investigated which temperature zone in the low temperature region is particularly involved in the formation of such micro-dislocation loops. That method is a method of suddenly changing the pulling speed. Specifically, when growing this crystal, the straight body from the shoulder to 60 cm was pulled up at a pulling speed of 1.0 mm / min, and then the crystal tail was rounded to separate the crystal from the melt at the same speed. Thereafter, from the position where the crystal was cut off, the winding speed was 0.5 mm / min and the film was wound up by 40 cm.
By pulling up by such a method, crystals with different temperature zones in which the cooling rate is lowered can be obtained depending on the position of the straight body portion. Then, the wafer was cut out from each part of the crystal, subjected to Secco etching, and the micro-dislocation loop was evaluated. The density of defects at a temperature zone of about 1000 to 900 ° C. (position of 42 to 46 cm from the crystal shoulder). As the cooling rate changed greatly, the dislocation loop did not occur (see FIG. 3). In this way, an effective temperature zone for reducing microdislocation loops was confirmed. In addition, since the temperature width of about 100 ° C. corresponds to a crystal length of 4 cm, and the interval is wound up at 0.5 mm / min, the passing time of about 1000 to 900 ° C. is about 80 minutes, and the cooling rate is About 1.25 ° C./min. Therefore, it has been found that if the cooling rate in this temperature zone is 1.25 ° C./min or less, the microdislocation loop can be reduced. The lower limit of the cooling rate is not particularly limited as long as at least the center of the crystal is in the V-rich region, but is practically about 0.4 ° C./min.
Next, when a general pulling condition of a crystal up to a diameter of 200 mm with conventional nitrogen non-doping that hardly generates micro dislocation loops in the V-rich region was investigated, the transit time in the temperature range of 1000 to 900 ° C. was the fastest. Even in this case, it was found that it took about 80 minutes. Therefore, as a condition for preventing the occurrence of microdislocation loops in the V-rich region, the cooling rate in the temperature range of 1000 to 900 ° C. may be about 1.25 ° C./min (100 ° C./80 min) or less. It could be confirmed.
Therefore, in the case of crystal growth having a diameter of 300 mm or more, single crystal growth was attempted by applying this pulling condition. A heat insulating material of an appropriate size is installed in the upper space of the HZ of the single crystal pulling apparatus, and the cooling rate in the temperature zone of 1000 to 900 ° C. is 1.25 ° C./min or less without winding immediately after crystal growth. It was found that no micro-dislocation loops were generated at all when the crystal was grown under such conditions.
Hereinafter, the present invention will be described in detail with reference to the drawings.
First, a schematic configuration example of a single crystal pulling apparatus using the CZ method used in the present invention will be described with reference to FIG.
As shown in FIG. 1, the single crystal pulling apparatus 30 includes a pulling chamber 31, a crucible 32 provided in the pulling chamber 31, a heater 34 disposed around the crucible 32, and a crucible for rotating the crucible 32. Holding shaft 33 and its rotating mechanism (not shown), seed chuck 6 holding silicon seed crystal 5, wire 7 pulling up seed chuck 6, and winding mechanism (not shown) for rotating or winding wire 7 Z). The crucible 32 is provided with a quartz crucible on the inner side containing the silicon melt (hot water) 2 and on the outer side with a graphite crucible. A heat insulating material 35 is disposed around the outside of the heater 34.
Moreover, in order to set the manufacturing conditions related to the manufacturing method of the present invention, an annular solid-liquid interface heat insulating material 8 is provided on the outer periphery of the crystal solid-liquid interface 4, and an upper surrounding heat insulating material 9 is disposed thereon. . This solid-liquid interface heat insulating material 8 is installed with a small gap 10 between its lower end and the molten metal surface 3 of the silicon melt 2. The upper surrounding heat insulating material 9 may not be used depending on conditions. Further, a cylindrical cooling device (not shown) that cools the single crystal by blowing cooling gas or blocking radiant heat may be provided. In addition, recently, a magnet (not shown) is installed outside the pulling chamber 31 in the horizontal direction, and a magnetic field in the horizontal direction or the vertical direction is applied to the silicon melt 2 to suppress the convection of the melt. The so-called MCZ method is often used to achieve stable growth.
EXAMPLES Hereinafter, although an Example and comparative example of this invention are given and this invention is demonstrated concretely, this invention is not limited to these.
Example 1
Silicon for producing a silicon single crystal wafer having a diameter of 300 mm, an orientation <100>, and a conductivity type p-type by charging a raw material polycrystalline silicon into a quartz crucible having a diameter of 32 inches (800 mm) with the pulling apparatus shown in FIG. A plurality of single crystal rods 1 were pulled up (no nitrogen doping).
Before the actual pulling up, the experiment was repeated by changing the position and size of the upper surrounding heat insulating material 9 installed in the upper space of the HZ, and the pulling rate was 1000 to 900 ° C. at 1.0 mm / min. HZ was set such that the cooling rate in the temperature zone was 1.25 ° C./min.
A silicon single crystal wafer having a diameter of 300 mm was cut out from each of the pulled silicon single crystal rods to produce a mirror-polished wafer. In order to confirm the grown-in defects and dislocation loops of the produced mirror-surface silicon single crystal wafer, the silicon single crystal wafer was subjected to non-stirring Secco etching and then observed using an electron microscope. As a result, many void-type defects were observed and it was confirmed that the entire surface was a V-rich region, but no dislocation loop was observed on the wafer surface.
Next, a plurality of epitaxial wafers each having a 3 μm epitaxial layer formed at 1125 ° C. on these wafer surfaces were produced, and an LPD of 0.09 μm size or larger was formed using a surface inspection apparatus SP1 (trade name, manufactured by KLA Tencor). It was measured. As a result, the LPD density was an average of 30 wafers / diameter of 300 mm (0.0425 wafers / cm ² = 4.3 wafers / 100 cm ² ).
Thus, it can be seen that if the cooling rate in the temperature range of 1000 to 900 ° C. is 1.25 ° C./min or less, the LPD density on the epi layer can be greatly improved. In particular, if the cooling rate is further reduced from 1.25 ° C./min, defects are further reduced from 4.3 / 100 cm ² .
(Comparative Example 1)
Using the same pulling apparatus as in Example 1, HZ is set so that the pulling rate is 1.0 mm / min, and the cooling rate in the temperature range of 1000 to 900 ° C. is 1.3 ° C./min or more. The silicon single crystal rod was pulled up.
A silicon single crystal wafer was prepared from each of the pulled silicon single crystal rods, an epitaxial wafer was prepared under the same conditions as in Example 1, and an LPD of 0.09 μm size or more was measured. As a result, 100 or more LPDs were observed on the entire wafer surface (diameter: 300 mm) in any wafer.
The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
For example, in the above-described embodiment, the case where a silicon single crystal is grown by the Czochralski method (CZ method) has been described as an example. However, the present invention is not limited to this, and a horizontal magnetic field is applied to the silicon melt. Needless to say, the present invention can also be applied to the so-called MCZ method in which a longitudinal magnetic field, a cusp magnetic field, or the like is applied.
Further, the present invention can be applied regardless of the conductivity type, resistivity, oxygen concentration, etc. of the single crystal as long as the diameter of the silicon single crystal (wafer) is 300 mm or more and the cooling rate is a predetermined value or less. Furthermore, the present invention can be similarly applied to, for example, a silicon single crystal doped with carbon to promote oxygen precipitation.
[Brief description of the drawings]
FIG. 1 is a schematic explanatory diagram of a single crystal pulling apparatus using the CZ method used in the present invention.
FIG. 2 is a distribution diagram of a grown-in defect region (nitrogen non-doped crystal) in a silicon single crystal where the horizontal axis is the radial position of the crystal and the vertical axis is the crystal pulling rate.
FIG. 3 is a result diagram showing the relationship between the length from the crystal shoulder and the dislocation loop density.

Claims (6)

When growing a silicon single crystal having a diameter of 300 mm or more by Czochralski method , the entire surface becomes a V-rich region crystal and the cooling rate in the temperature range of 1000 to 900 ° C. is 1.25 ° C. A method for producing a silicon single crystal wafer, comprising producing a silicon single crystal wafer from a silicon single crystal rod pulled so as to be less than / min.   2. The method for producing a silicon single crystal wafer according to claim 1, wherein the silicon single crystal wafer is a wafer for epitaxial growth. A silicon single crystal wafer which is grown by the Czochralski method , is nitrogen non-doped, is an entire V-rich region , has a diameter of 300 mm or more , and has no dislocation loop on the entire surface of the wafer. .   4. The silicon single crystal wafer according to claim 3, wherein the silicon single crystal wafer is an epitaxial growth wafer.   An epitaxial wafer, wherein an epitaxial layer is formed on the surface of the silicon single crystal wafer according to claim 3 or 4. An epitaxial wafer which is grown by the Czochralski method , is nitrogen non-doped, is an entire V-rich region , has an epitaxial layer formed on the surface of a silicon single crystal wafer having a diameter of 300 mm or more, and is observed on the epitaxial layer An epitaxial wafer having an LPD density of 0.09 μm size or more and 4.3 pieces / 100 cm ² or less.

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