WO2001084604A3 - Verfahren zur herstellung eines integrierten kondensators - Google Patents

Verfahren zur herstellung eines integrierten kondensators Download PDF

Info

Publication number
WO2001084604A3
WO2001084604A3 PCT/EP2001/004525 EP0104525W WO0184604A3 WO 2001084604 A3 WO2001084604 A3 WO 2001084604A3 EP 0104525 W EP0104525 W EP 0104525W WO 0184604 A3 WO0184604 A3 WO 0184604A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
structured
dielectric layer
metal layer
precipitating
Prior art date
Application number
PCT/EP2001/004525
Other languages
English (en)
French (fr)
Other versions
WO2001084604A2 (de
Inventor
Andreas Augustin
Wolfgang Klein
Hans-Joachim Barth
Original Assignee
Infineon Technologies Ag
Andreas Augustin
Wolfgang Klein
Barth Hans Joachim
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Andreas Augustin, Wolfgang Klein, Barth Hans Joachim filed Critical Infineon Technologies Ag
Priority to EP01931633A priority Critical patent/EP1277229B1/de
Priority to DE50110941T priority patent/DE50110941D1/de
Publication of WO2001084604A2 publication Critical patent/WO2001084604A2/de
Publication of WO2001084604A3 publication Critical patent/WO2001084604A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Verfahren zur Herstellung eines integrierten Kondensators mit den folgenden Schritten, nämlich Ausbilden einer strukturierten Metallschicht (1) auf einer Trägerschicht (2); Überziehen der strukturierten Metallschicht (1) und der Trägerschicht (2) mit einer dicken dielekrischen Schicht (3); lokales Hindurchätzen durch die dicke dielektrische Schicht (3) bis hin zu der strukturierten ersten Metallschicht (1) zum Ausbilden einer Ätzöffnung mit einer Seitenwandfläche (4) und einer Grundfläche (5), die durch die freigelegte Oberfläche der strukturierten ersten Metallschicht (1) gebildet wird; Abscheiden einer ersten leitfähigen Schicht (7) auf der gebildeten Grundfläche (5) und der dicken dielektrischen Schicht (3); Abscheiden einer dünnen dielektrischen Schicht (8) auf der ersten leitfähigen Schicht (7); Abscheiden einer zweiten leitfähigen Schicht (9) auf der dünnen dielektrischen Schicht (8); und Ausbilden einer strukturierten zweiten Metallschicht (10) auf der zweiten leitfähigen Schicht (9).
PCT/EP2001/004525 2000-04-28 2001-04-20 Verfahren zur herstellung eines integrierten kondensators WO2001084604A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP01931633A EP1277229B1 (de) 2000-04-28 2001-04-20 Verfahren zur herstellung eines integrierten kondensators
DE50110941T DE50110941D1 (de) 2000-04-28 2001-04-20 Verfahren zur herstellung eines integrierten kondensators

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US56054100A 2000-04-28 2000-04-28
US09/560,541 2000-04-28

Publications (2)

Publication Number Publication Date
WO2001084604A2 WO2001084604A2 (de) 2001-11-08
WO2001084604A3 true WO2001084604A3 (de) 2002-02-28

Family

ID=24238232

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/004525 WO2001084604A2 (de) 2000-04-28 2001-04-20 Verfahren zur herstellung eines integrierten kondensators

Country Status (3)

Country Link
EP (1) EP1277229B1 (de)
DE (1) DE50110941D1 (de)
WO (1) WO2001084604A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428789B1 (ko) * 2001-12-05 2004-04-28 삼성전자주식회사 금속/절연막/금속 캐퍼시터 구조를 가지는 반도체 장치 및그 형성 방법
DE10202697A1 (de) * 2002-01-24 2003-08-14 Infineon Technologies Dresden Verfahren zum Herstellen eines Kondensators in einer Dielektrikumschicht
DE10344604B4 (de) 2003-09-25 2011-08-11 Infineon Technologies AG, 81669 Speichereinheit mit Sammelelektroden
CN102458042B (zh) * 2010-10-27 2013-11-13 光明电子股份有限公司 线路基板制程、线路基板及半导体制程
CN107644866B (zh) * 2017-09-07 2019-12-24 上海华力微电子有限公司 一种mip平板电容结构及其形成方法
CN113921712A (zh) * 2021-12-16 2022-01-11 广州粤芯半导体技术有限公司 版图结构、半导体器件结构及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996017386A1 (en) * 1994-11-28 1996-06-06 Northern Telecom Limited A capacitor for an integrated circuit and method of formation thereof, and a method of adding on-chip capacitors to an integrated circuit
EP0771022A2 (de) * 1995-10-27 1997-05-02 International Business Machines Corporation Präzisionskondensator Metall-Metall für analoge Schaltung
US5808855A (en) * 1995-12-04 1998-09-15 Chartered Semiconductor Manufacturing Pte Ltd Stacked container capacitor using chemical mechanical polishing
US5965942A (en) * 1994-09-28 1999-10-12 Sharp Kabushiki Kaisha Semiconductor memory device with amorphous diffusion barrier between capacitor and plug

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5965942A (en) * 1994-09-28 1999-10-12 Sharp Kabushiki Kaisha Semiconductor memory device with amorphous diffusion barrier between capacitor and plug
WO1996017386A1 (en) * 1994-11-28 1996-06-06 Northern Telecom Limited A capacitor for an integrated circuit and method of formation thereof, and a method of adding on-chip capacitors to an integrated circuit
EP0771022A2 (de) * 1995-10-27 1997-05-02 International Business Machines Corporation Präzisionskondensator Metall-Metall für analoge Schaltung
US5808855A (en) * 1995-12-04 1998-09-15 Chartered Semiconductor Manufacturing Pte Ltd Stacked container capacitor using chemical mechanical polishing

Also Published As

Publication number Publication date
WO2001084604A2 (de) 2001-11-08
EP1277229B1 (de) 2006-09-06
EP1277229A2 (de) 2003-01-22
DE50110941D1 (de) 2006-10-19

Similar Documents

Publication Publication Date Title
EP1096562A3 (de) Verfahren zur Herstellung eines Halbleiterbauelements
EP1391924A4 (de) Halbleiterbauelement und verfahren zu seiner herstellung, leiterplatte und elektronische vorrichtung
WO2003049186A3 (en) Transistor metal gate structure that minimizes non-planarity effects and method of formation
EP1221715A3 (de) Hochdichtemetallkondensator mit einer Grabenätzstopschicht als Felddielektrikum in einem Dual-Damaszene-Verfahren
KR20070028392A (ko) 하드마스크를 사용하여 금속-절연막-금속 커패시터를알루미늄 금속 배선 레벨과 동시에 형성하는 방법
WO2000001010A3 (de) Verfahren zur herstellung von halbleiterbauelementen
TWI256723B (en) Process for manufacturing multiple layer wiring substrate onto which thin film capacitor is incorporated
EP0836224A3 (de) Methode zur Herstellung eines Kondensators mit hoher Kapazität unter Verwendung von Sputtering
TW374224B (en) Dual damascene process for manufacturing low k dielectrics
KR940009759A (ko) 반도체 장치의 필드 산화막 형성 방법
US5057186A (en) Method of taper-etching with photoresist adhesion layer
WO2001084604A3 (de) Verfahren zur herstellung eines integrierten kondensators
EP1420436A3 (de) Herstellungsverfahren eines Präzisions-Kondensators für eine integrierte Schaltung
KR940010206A (ko) 텅스텐 플러그 형성방법
MXPA05008066A (es) Revestimiento metalico protector para interconexiones de cobre.
US20040089903A1 (en) Method for producing surface micromechanical structures, and sensor
KR970051944A (ko) 반도체 장치내에 서브미크론 특성체를 제조하는 방법
EP0905778A3 (de) Verbesserte Mehrlagenleitungsstruktur und Verfahren dafür
EP1073099A3 (de) Verfahren zur Herstellung eines Kondensators mit einem abgeschrägten Kontaktanschluss in einer integrierten Schaltung
TW364205B (en) Method for producing DRAM capacitor
WO2002037557A3 (de) Herstellungsverfahren für eine integrierte schaltung unter zumindest teilweisem umwandeln einer oxidschicht in eine leitfähige schicht
KR930011116A (ko) 반도체장치의 제조방법
TW428279B (en) Manufacturing method of metal interconnects
EP1014436A3 (de) Herstellung eines Substrates
KR920005300A (ko) 다면구조 금속배선 형성방법

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

WWE Wipo information: entry into national phase

Ref document number: 2001931633

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2001931633

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: JP

WWG Wipo information: grant in national office

Ref document number: 2001931633

Country of ref document: EP