WO2001083860A1 - Plaquette de silicium haute qualite et procede de production de silicium monocristallin - Google Patents

Plaquette de silicium haute qualite et procede de production de silicium monocristallin Download PDF

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Publication number
WO2001083860A1
WO2001083860A1 PCT/JP2001/003580 JP0103580W WO0183860A1 WO 2001083860 A1 WO2001083860 A1 WO 2001083860A1 JP 0103580 W JP0103580 W JP 0103580W WO 0183860 A1 WO0183860 A1 WO 0183860A1
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WIPO (PCT)
Prior art keywords
silicon
single crystal
crystal
silicon wafer
silicon single
Prior art date
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PCT/JP2001/003580
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English (en)
Japanese (ja)
Inventor
Ryoji Hoshi
Izumi Fusegawa
Takahiro Yanagimachi
Tomohiko Ohta
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Shin-Etsu Handotai Co.,Ltd.
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Application filed by Shin-Etsu Handotai Co.,Ltd. filed Critical Shin-Etsu Handotai Co.,Ltd.
Publication of WO2001083860A1 publication Critical patent/WO2001083860A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/20—Controlling or regulating
    • C30B15/203—Controlling or regulating the relationship of pull rate (v) to axial thermal gradient (G)
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon

Definitions

  • the present invention relates to a high-quality silicon wafer used as a substrate of a semiconductor device such as a memory, and a silicon single crystal for producing the same, and a method of manufacturing a single crystal.
  • Fig. 5 shows an example of a silicon single crystal pulling apparatus using the Czochralski method (CZ method).
  • the silicon single crystal pulling apparatus comprises a quartz crucible 5 filled with a silicon melt 4, a graphite crucible 6 for protecting the same, a heater 7 and a heat insulating material 8 arranged so as to surround the crucibles 5 and 6.
  • a pulling chamber 2 for accommodating and taking out the grown single crystal 3 is connected to the upper part of the main chamber 1.
  • a seed crystal is immersed in a silicon melt 4 in a quartz crucible 5, then gently pulled up while rotating through a seed draw, and a rod-shaped single crystal.
  • the crucibles 5 and 6 can move up and down in the direction of the crystal growth axis, and raise the crucible to compensate for the decrease in the liquid level of the melt that has crystallized and decreased during crystal growth, thereby increasing the height of the melt surface. Is kept constant.
  • an inert gas such as an argon gas is introduced into the main chamber 1 from a gas inlet 10 provided at an upper portion of the pulling chamber 2 so that the single crystal 3 being pulled and the gas rectifying tube 11 a , And between the lower part of the heat shield member 12 a and the melt surface, and is discharged from the gas outlet 9.
  • Silicon single crystals manufactured by the above-mentioned CZ method are used in large quantities as substrates for semiconductor devices.
  • semiconductor devices are becoming more highly integrated, and elements are becoming increasingly smaller.
  • the thickness of the insulating oxide film used for the gate electrode portion has been further reduced. Even with such a thin insulating oxide film, the insulation resistance There is a need for oxide films with higher reliability, lower leakage current, and higher reliability. It is known that the oxide film breakdown voltage characteristic largely depends on crystal defects introduced and generated during crystal growth.
  • This crystal defect is observed as, for example, a ripple pattern when etched with a mixed solution of potassium dichromate (K 2 Cr 2 0 7 ), hydrofluoric acid, and water.
  • Vacancy a vacancy-type point defect called Vacancy (hereinafter sometimes abbreviated as V) incorporated into a silicon single crystal and an interstitial serial defect.
  • V a vacancy-type point defect incorporated into a silicon single crystal
  • I interstitial serial defect
  • the V- region is a region that has many Vacancy, that is, recesses and voids generated due to lack of silicon atoms
  • the I- region is a silicon atom. Is the region where there are many dislocations and extra silicon atom clusters generated by the existence of extra atoms, and there is no shortage or excess (less) of atoms between the V- region and the I-region. This means that there is a Neutral Region (hereinafter sometimes abbreviated as N-region). Groin-in defects (FPD, LSTD, COP, etc.) occur only when V and I are oversaturated. If so, it turns out that it does not exist as a defect.
  • FPD LSTD, COP, etc.
  • the growth rate is 0.6 mmZm i
  • grown-in defects such as FPDs, LSTDs, and COPs, allegedly caused by voids of vacancy-type point defects, exist at high density throughout the crystal diameter direction. It degrades the oxide film breakdown voltage characteristics. The region where these defects exist is called the V-rich region. If the growth rate is 0.6 mni / min or less, the growth rate decreases, and the inerterstitial becomes dominant.
  • the LZD (LargeD) is considered to be caused by a dislocation loop in which the 0 S F ring is generated from the periphery of the crystal and point defects of the interstitial silicon type gather outside this ring.
  • the crystal growth rate is 0.5 mmZmin or less, which is significantly slower than lmm / min of a normal crystal, and the productivity is reduced and the cost is increased.
  • oxygen is deposited in the middle of the N- region, it has a portion where oxygen precipitation is likely to occur and a portion where oxygen precipitation is unlikely to occur, and there is a problem that oxygen deposition is likely to be uneven.
  • Japanese Patent Application Publication No. 23095 is disclosed.
  • the defect density is specified, but no particular attention is paid to its in-plane distribution. That is, since the outer peripheral portion of the crystal is cooled, the temperature gradient G generally increases sharply, and the defect density decreases in the peripheral portion. In the region where the defect density decreases, the I- Regions with reduced gettering capability, such as regions and OSF ring regions, are likely to appear. In the examples and the like of Japanese Patent Application Laid-Open No. 8-124493, OSF actually occurs in the peripheral portion. Therefore, these disclosed technologies have a disadvantage that the ability of heavy metal gettering, which is very important in the device process, is reduced in the peripheral portion. Disclosure of the invention
  • a silicon wafer according to the present invention is a silicon wafer, and the density of FPD defects in the plane is 20 to 300 pieces except for 1 Omm around the wafer. 7. It is characterized by the fact that it is 111 2 .
  • the V-rich region is dominant over the entire surface of the wafer, and the wafer has no region where oxygen precipitation is reduced.
  • the yield rate of the oxide film withstand voltage characteristics is greatly improved and the IG performance in the peripheral portion is not reduced.
  • the silicon wafer is subjected to a heat treatment at 800 ° C. for 4 hours in a nitrogen atmosphere and at a temperature of 100 ° C. for 16 hours in an oxygen atmosphere, and the amount of oxygen deposition determined from the oxygen concentration before and after the heat treatment. It is preferable that the value AO is at 10 mm around A e of AO i is equal to or more than 80% of the value ⁇ O ic at the center.
  • the oxygen precipitation amount of the wafer specified in this way decreases in the vicinity of the wafer. As a result, the IG capacity will surely not decrease in the peripheral area.
  • the method for producing a silicon single crystal according to the present invention is characterized in that when growing a silicon single crystal by the Czochralski method, the melting point of silicon at the center of the crystal (14020 ° C) is raised to 1400 ° C. G (K / mm), the length of the temperature region from 115 ° C to 180 ° C is L (mm), and the crystal growth rate is F ( mm / min) and when the value calculated from them (FZG c) / (L / F), with the range of 0. 0 1 4 ⁇ 0.
  • the FPD density on the surface of the wafer becomes within the range of 20 to 300 cm 2 . It is possible to achieve a very high yield rate of oxide film breakdown voltage characteristics in the device process, and if the F / G e value is stipulated to a predetermined value, the FPD density in the peripheral area can be increased. There is no extreme drop in OSF, and no OSF occurs. Therefore, the yield and productivity in the device process can be improved and the cost can be reduced.
  • a silicon single crystal having an appropriate FPD defect density in a plane grown by the above-mentioned manufacturing method and free from OSF in the peripheral portion.
  • a silicon wafer which is excellent in withstand voltage characteristics of an oxide film manufactured by slicing from a single crystal, and whose gettering ability does not decrease in a peripheral portion.
  • FIG. 1 is a correlation diagram between the parameter (F / G c) / 1 (L / F) of the present invention and the FPD density.
  • FIG. 2 is an FPD distribution in an APD grown under the growth conditions (Example 2) according to the present invention.
  • Figure 3 shows the distribution in the FPD plane of ewa grown under the conventional growth conditions (Comparative Example 2).
  • FIG. 4 is a schematic diagram of the single crystal pulling apparatus used in the present invention.
  • Figure 5 is a schematic diagram of a conventional single crystal pulling apparatus equipped with a conventional single crystal pulling HZ (hot zone, furnace structure).
  • FIG. 6 is a diagram comparing the C-mode non-defective rate in the oxide film breakdown voltage between Example 2 and Comparative Example 1. BEST MODE FOR CARRYING OUT THE INVENTION
  • a silicon wafer is mixed with a mixed solution of dichromic acid chromium (K 2 Cr 2 O 7 ), hydrofluoric acid and water to a 35 ⁇ m selective wafer without stirring. It is important that the density of the FPD defects observed as ripples when tweaking (approximately 30 minutes) is 20 to 300 defects / cm 2 except for the area around 10 mm around the wafer.
  • the FPD density was measured under the above conditions, the FPD density was observed to be 400 to 2000 Zcm 2 , especially 600 Zcm 2 or more under the conventional general growth conditions. Often done. At this time, the yield ratio of the oxide film withstand voltage measured when the oxide film thickness is 25 nm is about 50%. If the FPD density is reduced by half to 300 particles / cm 2 , the non-defective rate will be 70 to 80%, and it will be almost no problem if the oxide film thickness is actually 10 nm or less, which is actually manufactured by advanced devices. Therefore, it was decided to improve the oxide film breakdown voltage characteristics by reducing the FPD density to less than 300 / cm 2 or less.
  • the FPD density is less than 20 cm 2
  • An OSF region or an I-rich region may appear, which may cause a reduction in precipitation.
  • point defects generally diffuse outward during crystal growth in the crystal periphery, so that there is a very defect-free part in the periphery, regardless of the defect distribution of the wafer. Therefore, the resolution in measurement is also a problem, and therefore, in the present invention, the defect density is not specified in the peripheral portion of 10 mm.
  • the silicon wafer has a temperature of 115 ° C and 100 ° C.
  • the thermal oxidation treatment for confirming the presence or absence of OSF is performed at 110 ° C to 1200 ° C for about 1 hour to 2 hours in a hot oxygen atmosphere, or 1 hour. It is preferable to perform the thermal oxidation treatment in a dry oxygen atmosphere at a temperature of 0000 ° C. to 110 ° C. for about 10 to 20 hours.
  • the silicon wafer was heated at 800 ° C for 4 hours in a nitrogen atmosphere and at 100 ° C for 16 hours in an oxygen atmosphere.
  • the value of oxygen deposition AO is at the peripheral portion of 10 mm, which is obtained by measuring the oxygen concentration before and after the heat treatment and before and after, is 80% or more of the value Oic at the center of the wafer. Preferably, there is.
  • the equilibrium concentration of point defects in the crystal is a function of temperature, and the higher the temperature, the higher the equilibrium concentration.
  • the crystals gradually change from the melting point to lower temperatures.
  • excess point defects are left behind, and they aggregate to form defects such as FPD.
  • the excess point defect concentration increases as the growth rate increases and decreases as the temperature gradient increases. Therefore, the excess point defect is approximately expressed in proportion to the F_G value from the growth rate F and the temperature gradient G near the melting point. Note that the defect distribution generally tends to decrease at the periphery, and the discussion here is for G at the center.
  • the temperature range related to the growth of excess point defects into secondary defects in 2 is from 115 ° C. to 180 ° C. (Japanese Unexamined Patent Application Publication No. No. 0).
  • the inventors have determined that the temperature gradient Gc (K / mm) from the melting point at the center of the crystal to 140 ° C., and the temperature gradient from 150 ° C. to 180 ° C. Given the distance L (mm) and the crystal growth rate F (mm / min) of C, the value (F / Gc) / ⁇ (L / F) calculated from them is that the transit time (LZF) is 4 It was found that when the time was longer than 0 minutes, it was correlated with the FPD defect density. And this value is, 0. 0 1 4 ⁇ 0.
  • the OSF ring does not occur in the peripheral area. Occurrence of OSF
  • the temperature gradient near the growth interface is related to the growth rate (for example, it is disclosed in Japanese Patent Application Laid-Open No. Hei 7-27991). This disclosed technology shows the relationship at the center of the crystal. This discussion is also made in Japanese Patent Application Laid-Open Nos. 8-124293 and 10-152395, but is limited to G at the center. In the present invention, it is important that the FPD density does not extremely decrease in the peripheral portion and that no OSF is generated.
  • the present inventors applied this relationship to the crystal peripheral portion, and examined conditions under which OSF does not occur in the peripheral portion.
  • the relation value FZG e between the temperature gradient G e (K / mm) from the melting point at 1 O mm at the periphery to 140 ° C. and the crystal growth rate F (mm / min) is 0.2 It was found that OSF does not appear in the peripheral part if it is 2 (mn ⁇ ZK 'ni in) or more.
  • the desired silicon quality can be obtained by the silicon single crystal manufactured under such crystal growth conditions and the wafer manufactured from the single crystal.
  • the single crystal pulling apparatus 20 has a member for melting the raw material silicon, a mechanism for pulling the crystallized silicon, and the like, which are housed in the main chamber 1. Have been. A pulling chamber 2 extending upward from the ceiling of the main chamber 1 is connected, and a mechanism (not shown) for pulling the single crystal 3 is provided above the pulling chamber 2.
  • the main chamber 1 is provided with a quartz crucible 5 for containing the molten raw material melt 4 and a graphite crucible 6 for containing the quartz crucible 5, and these crucibles 5 and 6 are driven by a driving mechanism (not shown). It is supported to be able to move up and down freely.
  • the crucible drive mechanism raises the crucible by the liquid level drop so as to compensate for the melt level drop caused by the pulling of the single crystal.
  • a heater 7 for melting the raw material is disposed so as to surround the crucibles 5 and 6. Outside the heater 7, a heat insulating material 8 for preventing heat from the heater 7 from being directly radiated to the main chamber 1 is provided so as to surround the heater 7.
  • An inert gas such as argon gas is introduced from the provided gas inlet 10, passes between the single crystal 3 being pulled and the gas rectifying cylinder 11 b, and melts with the lower part of the heat shield 12 b. It passes between the liquid surface and is discharged from the gas outlet 9.
  • the internal structure of the furnace up to this point is almost the same as the conventional one.
  • the value of the parameter (F / G c) / (L / F) of the growth condition correlated with the density of FPD defects is a desired value of 0.0. 1 4 ⁇ 0. 0 3 5 mm 2 / K ⁇ mi shall fit within the range of eta ° ⁇ 5. To do so, it is necessary to reduce F, increase G, or increase L. However, reducing F is difficult to adopt because it leads to lower productivity. Therefore, to increase L, an upper heat insulator 13 was introduced as shown in Fig. 4.
  • a single crystal rod was set by setting various growth rates F and temperature gradients Gc and Ge. Nurtured. From these crystal growth conditions, the values of the growth-related parameters (F / G c) (L / F) were determined.
  • G c, G e, and L are calculated using a comprehensive heat transfer analysis software called F EMA G (FD D upret, P.N icodeme, Y.Ryckmans, P.W outers, ad M.J Crochet, Int. J. Heat Mass Transfer, 33, 1849 (1990)).
  • F EMA G FD D upret, P.N icodeme, Y.Ryckmans, P.W outers, ad M.J Crochet, Int. J. Heat Mass Transfer, 33, 1849 (1990)
  • FZGe at the periphery of the single crystal was 0.245 mm 2 / K ⁇ min, and F / Ge could be kept within a predetermined range.
  • the sample is oxidized in a dry oxygen atmosphere at 115 ° C for 100 minutes to provide selectivity.
  • Non-defective product A non-defective product having a dielectric breakdown field of 8 MVZ cm or more was judged. The result of the non-defective rate was 76.5% on average and ⁇ was 4.0%, and is shown in Fig. 6 together with the data of Comparative Example 1.
  • the growth rate F was slowed down so that the value of the parameter (F / G c) / (L / F) was satisfied, and the FPD density was satisfied.
  • the F / Ge because no consideration was given to increasing the F / Ge, it is probable that OSF occurred at the periphery and the gettering ability was reduced.
  • the case where a silicon single crystal having a diameter of 200 mm is grown has been described by way of example.
  • the present invention is not limited thereto. It can also be applied to silicon single crystals having a diameter of 250 mm or less and a diameter of 250 to 40 mm or more.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

L'invention concerne une plaquette en silicium possédant sur sa surface des défauts FPD, à l'exception de sa partie périmétrique, sur une largeur de 10 mm, avec une densité comprise entre 20 et 300 pièces/cm2. L'invention concerne également un procédé de production d'une plaquette en silicium par la méthode CZ, caractérisé en ce que la plaquette de silicium croît dans des conditions telles que dans la partie centrale du cristal, une valeur de (F/Gc)/ ∑(L/F) est comprise entre 0,014 et 0,035 mm?2/K min0,5¿, où Gc représente un gradient de température (K/mm) dans la direction de l'axe de redressement dans la plage de température partant du point de fusion du silicium à 1400°, L (mm) représente une longueur du cristal cultivé à une température allant de 1150° à 1080°, F représente une vitesse (ml/min) de croissance cristalline et, dans ladite partie périmétrique de 10 mm de largeur, une valeur de F/Ge est d'au moins 0,22 mm2/K min, Ge représentant un gradient de température (K/mm) dans la plage de température allant du point de fusion du silicium à 1400°, et F représentant une vitesse (ml/min)de croissance cristalline.
PCT/JP2001/003580 2000-04-28 2001-04-25 Plaquette de silicium haute qualite et procede de production de silicium monocristallin WO2001083860A1 (fr)

Applications Claiming Priority (4)

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JP2000130101 2000-04-28
JP2000-130101 2000-04-28
JP2000230901 2000-07-31
JP2000-230901 2000-07-31

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012148918A (ja) * 2011-01-19 2012-08-09 Shin Etsu Handotai Co Ltd 単結晶製造装置及び単結晶製造方法
US9650725B2 (en) 2012-03-16 2017-05-16 Shin-Etsu Handotai Co., Ltd. Method for manufacturing a defect-controlled low-oxygen concentration silicon single crystal wafer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1179889A (ja) * 1997-07-09 1999-03-23 Shin Etsu Handotai Co Ltd 結晶欠陥が少ないシリコン単結晶の製造方法、製造装置並びにこの方法、装置で製造されたシリコン単結晶とシリコンウエーハ
JPH11116391A (ja) * 1997-10-17 1999-04-27 Shin Etsu Handotai Co Ltd 結晶欠陥の少ないシリコン単結晶の製造方法ならびにこの方法で製造されたシリコン単結晶およびシリコンウエーハ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1179889A (ja) * 1997-07-09 1999-03-23 Shin Etsu Handotai Co Ltd 結晶欠陥が少ないシリコン単結晶の製造方法、製造装置並びにこの方法、装置で製造されたシリコン単結晶とシリコンウエーハ
JPH11116391A (ja) * 1997-10-17 1999-04-27 Shin Etsu Handotai Co Ltd 結晶欠陥の少ないシリコン単結晶の製造方法ならびにこの方法で製造されたシリコン単結晶およびシリコンウエーハ

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012148918A (ja) * 2011-01-19 2012-08-09 Shin Etsu Handotai Co Ltd 単結晶製造装置及び単結晶製造方法
US9650725B2 (en) 2012-03-16 2017-05-16 Shin-Etsu Handotai Co., Ltd. Method for manufacturing a defect-controlled low-oxygen concentration silicon single crystal wafer
DE112013001054B4 (de) 2012-03-16 2022-12-15 Shin-Etsu Handotai Co., Ltd. Verfahren zum Herstellen eines Silizium-Einkristall-Wafers

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