WO2001067248A3 - Digitale speicherschaltung - Google Patents

Digitale speicherschaltung Download PDF

Info

Publication number
WO2001067248A3
WO2001067248A3 PCT/EP2001/001939 EP0101939W WO0167248A3 WO 2001067248 A3 WO2001067248 A3 WO 2001067248A3 EP 0101939 W EP0101939 W EP 0101939W WO 0167248 A3 WO0167248 A3 WO 0167248A3
Authority
WO
WIPO (PCT)
Prior art keywords
addressing
columns
address
rows
elements
Prior art date
Application number
PCT/EP2001/001939
Other languages
English (en)
French (fr)
Other versions
WO2001067248A2 (de
Inventor
Thomas Boehm
Helmut Kandolf
Stefan Lammers
Zoltan Manyoki
Original Assignee
Infineon Technologies Ag
Thomas Boehm
Helmut Kandolf
Stefan Lammers
Zoltan Manyoki
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Thomas Boehm, Helmut Kandolf, Stefan Lammers, Zoltan Manyoki filed Critical Infineon Technologies Ag
Priority to JP2001565001A priority Critical patent/JP2003526172A/ja
Publication of WO2001067248A2 publication Critical patent/WO2001067248A2/de
Publication of WO2001067248A3 publication Critical patent/WO2001067248A3/de
Priority to US10/237,410 priority patent/US6618306B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic

Landscapes

  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Gegenstand der Erfindung ist eine digitale Schaltungsanordnung mit einer Speichermatrix (50), die M reguläre Zeilen und N reguläre Spalten enthält und außerdem P <M zusätzliche Zeilen und Q <N zusätzliche Spalten aufweist, und mit einer Adressiereinrichtung (11-42), deren Adressen-Anschlußkontakte (11, 12) gerade zum Adressieren der regulären Zeilen und Spalten ausreichen. Um auch die zusätzlichen Zeilen und Spalten adressieren zu können, insbesondere zu Testzwecken, ist zusätzlich nur ein einziger Steuerbit-Anschlußkontakt (13) und eine Umschalteinrichtung (31-36) vorgesehen, die auf Steuerbits vom Steuerbit-Anschlußkontakt und von dedizierten Exemplaren der Adressen-Anschlußkontakte anspricht, um angelegte Adressenbits wahlweise der Adressierung der regulären Zeilen und Spalten oder der Adressierung der zusätzlichen Zeilen und Spalten zuzuordnen. Damit dies möglich ist, sind die Zahlen P und Q so gewählt sind, daß zur Adressierung von P Elementen mindestens (2) Bits weniger erforderlich sind als zur Adressierung von M Elementen und daß zur Adressierung von Q Elementen mindestens zwei Bits weniger erforderlich sind als zur Adressierung vom N Elementen.
PCT/EP2001/001939 2000-03-08 2001-02-21 Digitale speicherschaltung WO2001067248A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001565001A JP2003526172A (ja) 2000-03-08 2001-02-21 デジタルメモリ回路
US10/237,410 US6618306B2 (en) 2000-03-08 2002-09-09 Semiconductor memory device having row and column redundancy circuit and method of manufacturing the circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10011180.7 2000-03-08
DE10011180A DE10011180B4 (de) 2000-03-08 2000-03-08 Digitale Speicherschaltung

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/237,410 Continuation US6618306B2 (en) 2000-03-08 2002-09-09 Semiconductor memory device having row and column redundancy circuit and method of manufacturing the circuit

Publications (2)

Publication Number Publication Date
WO2001067248A2 WO2001067248A2 (de) 2001-09-13
WO2001067248A3 true WO2001067248A3 (de) 2001-12-20

Family

ID=7633899

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/001939 WO2001067248A2 (de) 2000-03-08 2001-02-21 Digitale speicherschaltung

Country Status (7)

Country Link
US (1) US6618306B2 (de)
JP (1) JP2003526172A (de)
KR (1) KR100747143B1 (de)
CN (1) CN1172241C (de)
DE (1) DE10011180B4 (de)
TW (1) TW499681B (de)
WO (1) WO2001067248A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10311373B4 (de) * 2003-03-14 2005-02-24 Infineon Technologies Ag Integrierter Speicher mit redundanten Einheiten von Speicherzellen und Verfahren zum Test eines integrierten Speichers
KR100675295B1 (ko) * 2005-10-19 2007-01-29 삼성전자주식회사 반도체 메모리 장치
US7420859B2 (en) * 2006-12-07 2008-09-02 Arm Limited Memory device and method of controlling access to such a memory device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0637036A2 (de) * 1993-07-30 1995-02-01 STMicroelectronics, Inc. Überprüfung von Redundanzelementen eines IC-Speichers ohne Programmierung redundanter Ersatzelemente
US5732029A (en) * 1995-05-20 1998-03-24 Samsung Electronics Co., Ltd. Method and circuit for testing memory cells in semiconductor memory device
US5808948A (en) * 1995-12-30 1998-09-15 Samsung Electronics, Co., Ltd. Semiconductor memory device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817197A (ja) * 1994-06-30 1996-01-19 Fujitsu Ltd 半導体記憶装置
JP2882369B2 (ja) * 1996-06-27 1999-04-12 日本電気株式会社 半導体記憶装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0637036A2 (de) * 1993-07-30 1995-02-01 STMicroelectronics, Inc. Überprüfung von Redundanzelementen eines IC-Speichers ohne Programmierung redundanter Ersatzelemente
US5732029A (en) * 1995-05-20 1998-03-24 Samsung Electronics Co., Ltd. Method and circuit for testing memory cells in semiconductor memory device
US5808948A (en) * 1995-12-30 1998-09-15 Samsung Electronics, Co., Ltd. Semiconductor memory device

Also Published As

Publication number Publication date
CN1172241C (zh) 2004-10-20
CN1416546A (zh) 2003-05-07
WO2001067248A2 (de) 2001-09-13
JP2003526172A (ja) 2003-09-02
TW499681B (en) 2002-08-21
KR20020082863A (ko) 2002-10-31
US6618306B2 (en) 2003-09-09
KR100747143B1 (ko) 2007-08-07
US20030039157A1 (en) 2003-02-27
DE10011180B4 (de) 2006-02-23
DE10011180A1 (de) 2001-09-27

Similar Documents

Publication Publication Date Title
WO2004077335A3 (en) Multi-protocol memory card
HK1048875A1 (en) Active matrix type driving circuit.
WO2002030000A3 (en) Data buffer structure for physical and transport channels in a cdma system
WO2003014809A3 (en) Electrostatic discharge protection for pixellated electronic device
GB2351822A (en) Memory system
TWI265528B (en) Addressing circuit for a cross-point memory array including cross-point resistive elements
EP1152430A3 (de) Ramspeichernanordnungen
WO2002078001A3 (en) Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays
EP1793386A3 (de) Eine Speicherzellenvorrichtung und eine Anzeigevorrichtung, die einen mechanischen Schalter verwendet und Verfahren zu dessen Steuerung
ZA200405017B (en) Perfume containing surfactant compositions having perfume burst when diluted and process thereof.
WO2005104527A3 (de) Vorrichtung und verfahren zum aufnehmen eines bildes
AU2003295489A8 (en) Cis-prenyltransferases from the rubber-producing plants russian dandelion (taraxacum kok-saghyz) and sunflower (helianthus annus)
AU2001296983A1 (en) Binary-ternary content addressable memory
DK1315709T3 (da) Aminoalkylbenzoyl-benzofuraner eller benzothiophener, fremgangsmåde til fremstilling deraf og sammensætninger indeholdende samme
GB2380029B (en) Active address content addresable memory
GB0205948D0 (en) Level shifting circuit and active matrix driver
TW200623399A (en) Charge trap insulator memory device
WO2001067248A3 (de) Digitale speicherschaltung
SG107099A1 (en) Memory cell, memory circuit block, data writing and data reading method
TW200715247A (en) Electro-optical device and electronic apparatus
WO2004034362A3 (fr) Systeme d’adressage d’ecran de visualisation
EP1526458A3 (de) Spaltenredundanzschaltung mit reduzierter Signalwegverzögerung
EP1367599A3 (de) Redundanz -Schaltung und -Verfahren für Halbleiterspeicher
IL148193A0 (en) Hard candy with improved storage stability
EP1318522A3 (de) Speicheranordnungen

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 1020027011554

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 01806163X

Country of ref document: CN

ENP Entry into the national phase

Ref country code: JP

Ref document number: 2001 565001

Kind code of ref document: A

Format of ref document f/p: F

WWE Wipo information: entry into national phase

Ref document number: 10237410

Country of ref document: US

WWP Wipo information: published in national office

Ref document number: 1020027011554

Country of ref document: KR

122 Ep: pct application non-entry in european phase