WO2001061735A3 - Implantationsmaske für hochenergieionenimplantation - Google Patents
Implantationsmaske für hochenergieionenimplantation Download PDFInfo
- Publication number
- WO2001061735A3 WO2001061735A3 PCT/DE2001/000596 DE0100596W WO0161735A3 WO 2001061735 A3 WO2001061735 A3 WO 2001061735A3 DE 0100596 W DE0100596 W DE 0100596W WO 0161735 A3 WO0161735 A3 WO 0161735A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- implantation
- mask
- high energy
- energy ion
- ion implantation
- Prior art date
Links
- 238000002513 implantation Methods 0.000 title abstract 3
- 238000005468 ion implantation Methods 0.000 title 1
- 238000000034 method Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Composite Materials (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Physical Vapour Deposition (AREA)
Abstract
Die Erfindung betrifft eine wiederverwendbare Implantationsmaske (5) aus vorzugsweise Silizium mit speziell strukturierten Gräben und Löchern (2 bzw. 3), die direkt oder im Abstand von einem Devicewafer (7) vorgesehen wird, sowie ein Verfahren zum Justieren einer Weiterbehandlungsebene auf einer Implantationsebene bei einem mit einer solchen Implantationsmaske behandelten Halbleiterwafer (7).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10006523.6 | 2000-02-15 | ||
DE2000106523 DE10006523A1 (de) | 2000-02-15 | 2000-02-15 | Implantationsmaske für Hochenergieionenimplantation |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001061735A2 WO2001061735A2 (de) | 2001-08-23 |
WO2001061735A3 true WO2001061735A3 (de) | 2002-07-18 |
Family
ID=7630866
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2001/000596 WO2001061735A2 (de) | 2000-02-15 | 2001-02-15 | Implantationsmaske für hochenergieionenimplantation |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE10006523A1 (de) |
WO (1) | WO2001061735A2 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10143515B4 (de) * | 2001-09-05 | 2006-09-07 | Infineon Technologies Ag | Maskenanordnung für einen Abbildungsprozess, Verfahren zu deren Herstellung sowie Verfahren zum optischen Abbilden bzw. zum Herstellen eines Kompensationsbauelements |
DE10314596B3 (de) * | 2003-03-31 | 2004-11-25 | Infineon Technologies Ag | MOS-Kompensationstransistorbauelement und Herstellungsverfahren dafür |
CN111812941B (zh) * | 2019-04-11 | 2023-10-10 | 中国科学院金属研究所 | 一种高精度硅物理掩膜版及其制作方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4021276A (en) * | 1975-12-29 | 1977-05-03 | Western Electric Company, Inc. | Method of making rib-structure shadow mask for ion implantation |
US4256532A (en) * | 1977-07-05 | 1981-03-17 | International Business Machines Corporation | Method for making a silicon mask |
US4293374A (en) * | 1980-03-10 | 1981-10-06 | International Business Machines Corporation | High aspect ratio, high resolution mask fabrication |
JPS58106822A (ja) * | 1981-12-18 | 1983-06-25 | Hitachi Ltd | 不純物導入方法 |
US4448865A (en) * | 1981-10-30 | 1984-05-15 | International Business Machines Corporation | Shadow projection mask for ion implantation and ion beam lithography |
WO1999040614A2 (en) * | 1998-02-09 | 1999-08-12 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device with linearly doping profile |
DE19835528A1 (de) * | 1998-08-06 | 2000-02-10 | Asea Brown Boveri | Verfahren zur Einstellung der Trägerlebensdauer in einem Halbleiterbauelement |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2454714C3 (de) * | 1974-11-19 | 1979-04-19 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V., 8000 Muenchen | Maskierverfahren zur Herstellung periodischer Strukturen in einem Substrat mittels Ionenimplantation |
GB2078441A (en) * | 1980-06-17 | 1982-01-06 | Westinghouse Electric Corp | Forming impurity regions in semiconductor bodies by high energy ion irradiation |
DE19838263C2 (de) * | 1998-08-22 | 2003-01-30 | Georg Grathwohl | Verfahren zur Herstellung von porösen Keramikkörpern mit offenen Porenkanälen und mikroporöser Matrix |
-
2000
- 2000-02-15 DE DE2000106523 patent/DE10006523A1/de not_active Ceased
-
2001
- 2001-02-15 WO PCT/DE2001/000596 patent/WO2001061735A2/de active Search and Examination
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4021276A (en) * | 1975-12-29 | 1977-05-03 | Western Electric Company, Inc. | Method of making rib-structure shadow mask for ion implantation |
US4256532A (en) * | 1977-07-05 | 1981-03-17 | International Business Machines Corporation | Method for making a silicon mask |
US4293374A (en) * | 1980-03-10 | 1981-10-06 | International Business Machines Corporation | High aspect ratio, high resolution mask fabrication |
US4448865A (en) * | 1981-10-30 | 1984-05-15 | International Business Machines Corporation | Shadow projection mask for ion implantation and ion beam lithography |
JPS58106822A (ja) * | 1981-12-18 | 1983-06-25 | Hitachi Ltd | 不純物導入方法 |
WO1999040614A2 (en) * | 1998-02-09 | 1999-08-12 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device with linearly doping profile |
DE19835528A1 (de) * | 1998-08-06 | 2000-02-10 | Asea Brown Boveri | Verfahren zur Einstellung der Trägerlebensdauer in einem Halbleiterbauelement |
US6159830A (en) * | 1998-08-06 | 2000-12-12 | Asea Brown Boveri Ag | Process for adjusting the carrier lifetime in a semiconductor component |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 007, no. 214 (E - 199) 21 September 1983 (1983-09-21) * |
Also Published As
Publication number | Publication date |
---|---|
WO2001061735A2 (de) | 2001-08-23 |
DE10006523A1 (de) | 2001-08-23 |
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