WO2001057922A1 - Method and apparatus for singulation of electronic devices - Google Patents

Method and apparatus for singulation of electronic devices Download PDF

Info

Publication number
WO2001057922A1
WO2001057922A1 PCT/SG2001/000016 SG0100016W WO0157922A1 WO 2001057922 A1 WO2001057922 A1 WO 2001057922A1 SG 0100016 W SG0100016 W SG 0100016W WO 0157922 A1 WO0157922 A1 WO 0157922A1
Authority
WO
WIPO (PCT)
Prior art keywords
laser beam
panel
devices
prescribed
singulation
Prior art date
Application number
PCT/SG2001/000016
Other languages
French (fr)
Inventor
Choong Whye Kwok
Qiong Chen
Original Assignee
Advanced Systems Automation Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Systems Automation Ltd. filed Critical Advanced Systems Automation Ltd.
Priority to AU2001232606A priority Critical patent/AU2001232606A1/en
Publication of WO2001057922A1 publication Critical patent/WO2001057922A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/38—Removing material by boring or cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Definitions

  • the present invention is related to the packaging of semiconductor devices.
  • the present invention is related to the method and apparatus for the electrical isolation and singulation of integrated circuit (IC) device packages.
  • IC integrated circuit
  • CSP chip scale packages
  • Packages such as QFN (Quad Flat Non- lead) and chip-array BGA are examples of CSPs that are produced in a
  • the individual package can then be singulated, before
  • the traditional ways of singulation are punching, stamping or sawing.
  • the present invention provides, in one aspect, an apparatus for the singulation of IC packages, particularly for packages
  • the apparatus uses a cool, clean and dry process that does not result in the generation of burr or loose particles.
  • the present invention provides a novel method of cutting a panel of IC packages to achieve electrical isolation without singulation. This allows testing to be performed while the packages are still in the partially-cut panel form, substantially reducing the handling difficulties associates with the small CSP packages.
  • the present apparatus and method uses laser ablation technique.
  • the fluence of the laser beam is less
  • the wavelength of the laser used is below 550nm, while the pulse width of the beam is kept between around 100-500ns.
  • the beam spot diameter on the workpiece is well controlled, and in the
  • controlled depth cutting may be achieved using the same multiple scanning technique.
  • the isolated packages can then be tested while still in the partially-cut panel form. After testing, singulation is performed,
  • an optical system for delivery said laser beam onto a prescribed location an optical system for delivery said laser beam onto a prescribed location
  • a transfer system for transferring an IC device into the prescribed location
  • Figure 1 is a schematic diagram of a laser cutting apparatus according to the present invention.
  • FIG. 2 is a schematic diagram of another laser cutting apparatus
  • Figure 3 is a schematic diagram to show the path of the laser beam in a
  • the apparatus and method according to the present invention allows the clean, cool and dry singulation of an IC device.
  • the invention uses laser energy to sequentially ablate various layers of substrate material on a panel of molded IC devices with minimal heat generation.
  • Laser ablation is defined in the present invention as the conversion of the mold flash into plasma and other volatile species due to photodecomposition by the laser beam.
  • Table 1 shows an example of the property of a double frequency Q- switched short wavelength Nd:YAG laser beam which causes ablation of the substrate according to the present invention.
  • packages according to the conditions shown in Table 1 may be achieved using 2-8 scans at a low power e.g. about 2 watts, depending on the
  • the pulse width is less than 300ns
  • the pulse energy is 0.1-10mJ/532nm
  • repetition rate is 10-50kHz
  • the beam spot is 20-200 ⁇ m
  • the fluence larger than 5J/cm 2 .
  • a CABGA (chip-array ball grid array) package with a copper layer of 0.1mm thickness packaged in an epoxy organic material at a depth of 0.1mm depth may be debussed by scanning a laser beam for 3-8 times with a beam spot diameter of 30 ⁇ m.
  • the frequency is 10KHz and the pulse energy 0.2mJ, and the pulse width is 100ns.
  • Figure 1 shows an example of a laser cutting apparatus in which the beam of a double-frequency Q-switched Nd:YAG laser 20 is directed onto
  • a computer control system 30 controls a controller 32 which in turn controls the stage 24 and
  • Figure 2 shows the details of a specific example of an apparatus for
  • the panel 50 with IC devices 42 embedded therein are transferred by a transfer system to holding station 40.
  • the holding station may be, for example, a stage and guide track or a stage with vacuum suction outlets.
  • a laser beam from a laser generator 44 is directed into a scanner or galvanometer 46, which directs the beam to the boundary between the IC devices.
  • the scanner may be programmed such that the laser beam performs controlled-depth cutting or through-cutting along certain cutting routes.
  • Controlled-depth cutting allows the panel to be cut until the electrically conductive layers at the boundaries are cut, but stops short of completely cutting through all the plastic mold material. This allows the individual IC packages to be electrically isolated from each other while being physically maintained as an array. The electrically isolated IC devices can then be sent for testing as a partially-cut panel. After testing, the cutting
  • process may be repeated, but with a higher number of scans to ensure
  • an exhaust inlet 52 is provided to suck away the decomposed fume
  • An air blower (not
  • Figure 3 shows a third embodiment of the present invention in which
  • the laser generator 56 is position sideways.
  • a beam expander 58 is provided to enlarge the beam spot diameter, and a series of mirrors 60 are used to direct the focused beam onto the X-Y scanner or galvanometer 62. The scanner then directs the beam onto the appropriate boundaries of the panel between the IC packages under the guidance of the vision alignment system 63.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Laser Beam Processing (AREA)

Abstract

A laser ablation apparatus for the singulation of IC packages that uses a cool, clean and dry process that does not result in the generation of burr or loose particles. The apparatus provides a novel method of cutting a panel of IC packages to achieve electrical isolation without singulation. The laser beam spot is kept very small while the frequency is high and pulse energy is low.

Description

METHOD AND APPARATUS FOR SINGULATION OF ELECTRONIC DEVICES
FIELD OF THE INVENTION
The present invention is related to the packaging of semiconductor devices. In particular, the present invention is related to the method and apparatus for the electrical isolation and singulation of integrated circuit (IC) device packages.
BACKGROUND OF THE INVENTION
The packaging of semiconductor and IC devices by plastic molding of the chip is well known in the art. The package typically contains a molded plastic covering which protects the IC devices inside. Interconnections extending from the packages allow electrical connection between the device and the external circuitry. Miniaturization now allows chip scale packages (CSP) of as small as 3mmX3mm to be molded by reducing the
package size to approach the chip size. To increase packaging efficiency, recent trends in packaging technology have been towards chip array chip
scale packages , in which an array of chips are molded together in a
single mold cavity as a panel. Packages such as QFN (Quad Flat Non- lead) and chip-array BGA are examples of CSPs that are produced in a
panel array. The individual package can then be singulated, before
being sent for testing and higher level packaging. The traditional ways of singulation are punching, stamping or sawing.
For new packages such as chip array CSP, which have multiple chips
embedded within the same layers of material, punching and stamping cannot be used. Conventional sawing techniques also do not give satisfactory results due to the following reasons. Heat produced by the sawing process requires the use of a coolant. Water is typically used as a coolant because it can also act as an electric conductor for discharging static electricity generated from the sawing process. This wet process, however, increases the chances of device failure during subsequent uses, reducing the reliability of the package. Mechanical stress from the sawing process increases the risk of delamination. For packages such as QFN, which require the cutting of copper layer(s), burr and sticky particles pose difficulties in producing satisfactory singulated products,
and also results in high wear rate of the saw. Furthermore, with the trend towards miniaturization of package sizes, holding of the package becomes increasingly difficult. There is therefore a need to provide a
method and apparatus for the singulation of IC devices that alleviates the
above-stated problems.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides, in one aspect, an apparatus for the singulation of IC packages, particularly for packages
having multilayers of organic and metallic materials. The apparatus uses a cool, clean and dry process that does not result in the generation of burr or loose particles.
In another aspect, the present invention provides a novel method of cutting a panel of IC packages to achieve electrical isolation without singulation. This allows testing to be performed while the packages are still in the partially-cut panel form, substantially reducing the handling difficulties associates with the small CSP packages.
The present apparatus and method uses laser ablation technique.
Ablation is achieved under conditions in which the substrate material is
converted to plasma under short laser pulses which do not give sufficient time for significant thermal penetration to occur. The fluence is controlled
and multiple scanning under high speed is used.
In the preferred embodiment, the fluence of the laser beam is less
than around 10OJ/cm2, the wavelength of the laser used is below 550nm, while the pulse width of the beam is kept between around 100-500ns.
The beam spot diameter on the workpiece is well controlled, and in the
range of about 10-300μm. Multiple scanning is performed, such that for each scan, a certain depth of cutting is achieved. For electrical isolation of the packages (i.e. the copper layers of the substrates are debussed),
controlled depth cutting may be achieved using the same multiple scanning technique. The isolated packages can then be tested while still in the partially-cut panel form. After testing, singulation is performed,
preferably by repeating the laser ablation process, but with increased number of scans as compared to the electrical isolation step.
The apparatus in the preferred embodiment includes a laser generator for generating a high frequency and low pulse energy laser
beam, an optical system for delivery said laser beam onto a prescribed location, and a transfer system for transferring an IC device into the prescribed location.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a schematic diagram of a laser cutting apparatus according to the present invention.
Figure 2 is a schematic diagram of another laser cutting apparatus
according to the present invention.
Figure 3 is a schematic diagram to show the path of the laser beam in a
laser cutting apparatus according to the present invention. DESCRIPTION OF THE INVENTION
The apparatus and method according to the present invention allows the clean, cool and dry singulation of an IC device. The invention uses laser energy to sequentially ablate various layers of substrate material on a panel of molded IC devices with minimal heat generation. Laser ablation is defined in the present invention as the conversion of the mold flash into plasma and other volatile species due to photodecomposition by the laser beam.
Table 1 shows an example of the property of a double frequency Q- switched short wavelength Nd:YAG laser beam which causes ablation of the substrate according to the present invention.
Figure imgf000006_0001
TABLE 1 Generally, controlled depth electrical isolation for chip array CSP
packages according to the conditions shown in Table 1 may be achieved using 2-8 scans at a low power e.g. about 2 watts, depending on the
depth and material that need to be cut. For complete singulation, 10-20 scans may be performed. In the more preferred embodiment, the pulse width is less than 300ns, the pulse energy is 0.1-10mJ/532nm, the
repetition rate is 10-50kHz, the beam spot is 20-200μm and the fluence larger than 5J/cm2.
As an example, a CABGA (chip-array ball grid array) package with a copper layer of 0.1mm thickness packaged in an epoxy organic material at a depth of 0.1mm depth may be debussed by scanning a laser beam for 3-8 times with a beam spot diameter of 30μm. The frequency is 10KHz and the pulse energy 0.2mJ, and the pulse width is 100ns.
Figure 1 shows an example of a laser cutting apparatus in which the beam of a double-frequency Q-switched Nd:YAG laser 20 is directed onto
a panel 22 of IC devices (not shown) on a stage 24 by the use of a
scanner 26 and appropriate optical components 28. A computer control system 30 controls a controller 32 which in turn controls the stage 24 and
the triggering of the laser via a trigger 34 such that the laser beam is
directed at the boundary between the embedded IC devices. A vision
system 25, coupled to the control system and the stage, is provided to
control the route of cutting. No water cooling system is provided such that
the entire process is dry. Figure 2 shows the details of a specific example of an apparatus for
cutting a panel of IC devices. In this apparatus, the panel 50 with IC devices 42 embedded therein, are transferred by a transfer system to holding station 40. The holding station may be, for example, a stage and guide track or a stage with vacuum suction outlets. A laser beam from a laser generator 44 is directed into a scanner or galvanometer 46, which directs the beam to the boundary between the IC devices. The exact
positioning of panel 50 is controlled by a vision alignment system 47. The scanner may be programmed such that the laser beam performs controlled-depth cutting or through-cutting along certain cutting routes.
Controlled-depth cutting allows the panel to be cut until the electrically conductive layers at the boundaries are cut, but stops short of completely cutting through all the plastic mold material. This allows the individual IC packages to be electrically isolated from each other while being physically maintained as an array. The electrically isolated IC devices can then be sent for testing as a partially-cut panel. After testing, the cutting
process may be repeated, but with a higher number of scans to ensure
complete singulation of the IC packages. In this embodiment, an exhaust inlet 52, is provided to suck away the decomposed fume
generated by the ablation of the packaging material. An air blower (not
shown) may also be optionally provided for blowing away the ionized
vapor as it is formed. Figure 3 shows a third embodiment of the present invention in which
the laser generator 56 is position sideways. In this embodiment, a beam expander 58 is provided to enlarge the beam spot diameter, and a series of mirrors 60 are used to direct the focused beam onto the X-Y scanner or galvanometer 62. The scanner then directs the beam onto the appropriate boundaries of the panel between the IC packages under the guidance of the vision alignment system 63.
While the present invention has been described particularly with references to Figs 1 to 3, with specific examples cutting chip array CSP packages, it should be understood that the figures are for illustration only and should not be taken as limitation on the invention. In addition it is clear that the method and apparatus of the present invention has utility in many applications where cutting of molded material is required. It is contemplated that many changes and modifications may be made by one of ordinary skill in the art without departing from the spirit and the scope of
the invention described.

Claims

1. An apparatus for singulating a molded panel with a plurality of IC devices comprising :
a laser generator for generating a laser beam, said laser beam
scanning multiple times at high speed over a prescribed area of said molded panel;
an optical system for delivery and focusing said laser beam; and
a transfer system for transferring said panel into a prescribed position from which ablation by said laser beam can occur;
said apparatus ablating said panel in the absence of a water cooling system to obtain singulated IC devices.
2. A method for cutting a panel of IC devices connected by a multilayer substrate comprising :
generating a laser beam, said laser beam capable of ablating the
substrate in said panel without water cooling;
ablating said panel at a prescribed position to a prescribed depth such that said IC devices are electrically isolated but physically
connected by non-conducting material in said substrate;
testing said IC devices; and singulating said IC devices by complete ablation said substrate at
said prescribed position.
3. A method according to claim 1 wherein the fluence of said laser beam is less than about 100J/cm2.
4. A method according to claim 1 wherein said laser beam scans 10-20 times and at a pulse width of 100ns on said prescribed surface.
5. A method according to claim 2 wherein the fluence of said laser beam is less than about 100J/cm2.
6. A method according to claim 2 wherein said laser beam scans 2-8 times and at a pulse width of 100ns on said prescribed surface to obtain ablation to said prescribed depth, said laser beam further
scanning 10-20 times and at a pulse width of 100ns on said prescribed surface for singulation of said IC devices.
PCT/SG2001/000016 2000-02-04 2001-01-31 Method and apparatus for singulation of electronic devices WO2001057922A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001232606A AU2001232606A1 (en) 2000-02-04 2001-01-31 Method and apparatus for singulation of electronic devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG200000782A SG90093A1 (en) 2000-02-04 2000-02-04 Method and apparatus for singulation of electronic devices
SG200000782-3 2000-02-04

Publications (1)

Publication Number Publication Date
WO2001057922A1 true WO2001057922A1 (en) 2001-08-09

Family

ID=20430527

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SG2001/000016 WO2001057922A1 (en) 2000-02-04 2001-01-31 Method and apparatus for singulation of electronic devices

Country Status (4)

Country Link
AU (1) AU2001232606A1 (en)
SG (1) SG90093A1 (en)
TW (1) TW439107B (en)
WO (1) WO2001057922A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1030004C2 (en) * 2005-09-21 2007-03-22 Fico Singulation B V Device and method for separating electronic components.
DE102007049160A1 (en) * 2007-10-13 2009-04-16 Carl Baasel Lasertechnik Gmbh & Co. Kg A method of separating grouped into a group, having a Kunststoffvergusskörper chip housings

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015184162A (en) * 2014-03-25 2015-10-22 セイコーエプソン株式会社 Electronic component conveyance device and electronic component inspection device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS589360A (en) * 1981-07-10 1983-01-19 Hitachi Ltd Manufacture of hybrid integrated circuit
GB2150360A (en) * 1983-11-21 1985-06-26 Casio Computer Co Ltd A method of manufacturing a small electronic device
JPH04333299A (en) * 1991-05-08 1992-11-20 Toshiba Corp Cutting method of film board
JPH1140523A (en) * 1997-07-22 1999-02-12 Mitsubishi Electric Corp Substrate cutting device and substrate cutting method
JPH11233680A (en) * 1998-02-18 1999-08-27 Mitsubishi Electric Corp Semiconductor device and method and apparatus for chips
JP2000277550A (en) * 1999-03-25 2000-10-06 Mitsubishi Electric Corp Semiconductor device and its manufacture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS589360A (en) * 1981-07-10 1983-01-19 Hitachi Ltd Manufacture of hybrid integrated circuit
GB2150360A (en) * 1983-11-21 1985-06-26 Casio Computer Co Ltd A method of manufacturing a small electronic device
JPH04333299A (en) * 1991-05-08 1992-11-20 Toshiba Corp Cutting method of film board
JPH1140523A (en) * 1997-07-22 1999-02-12 Mitsubishi Electric Corp Substrate cutting device and substrate cutting method
JPH11233680A (en) * 1998-02-18 1999-08-27 Mitsubishi Electric Corp Semiconductor device and method and apparatus for chips
JP2000277550A (en) * 1999-03-25 2000-10-06 Mitsubishi Electric Corp Semiconductor device and its manufacture

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1030004C2 (en) * 2005-09-21 2007-03-22 Fico Singulation B V Device and method for separating electronic components.
WO2007035097A2 (en) * 2005-09-21 2007-03-29 Fico B.V. Device and method for separating electronic components
WO2007035097A3 (en) * 2005-09-21 2007-05-10 Fico Singulation B V Device and method for separating electronic components
US8677592B2 (en) 2005-09-21 2014-03-25 Fico B.V. Methods for separating electronic components utilizing a manipulator to transport the electronic components between first and second cutting tools
DE102007049160A1 (en) * 2007-10-13 2009-04-16 Carl Baasel Lasertechnik Gmbh & Co. Kg A method of separating grouped into a group, having a Kunststoffvergusskörper chip housings
DE102007049160B4 (en) * 2007-10-13 2010-01-28 Carl Baasel Lasertechnik Gmbh & Co. Kg A method of separating grouped into a group, having a Kunststoffvergusskörper chip housings

Also Published As

Publication number Publication date
SG90093A1 (en) 2002-07-23
TW439107B (en) 2001-06-07
AU2001232606A1 (en) 2001-08-14

Similar Documents

Publication Publication Date Title
EP1201108B1 (en) A circuit singulation system and method
US10573538B2 (en) Handler bonding and debonding for semiconductor dies
US20060216911A1 (en) Wafer laser processing method
US20080067160A1 (en) Systems and methods for laser cutting of materials
JP2009544145A (en) Wafer scribing with an infrared laser using short pulses
JP2008300475A (en) Dividing method for wafer
EP1148968B1 (en) Method and apparatus for removal of mold flash
JP7128054B2 (en) Wafer processing method
JP2008130818A (en) Laser processing apparatus
EP3668677B1 (en) Cutting method for polymer resin mold compound based substrates and system thereof
TW201604996A (en) Packaging substrate processing method
KR20160088808A (en) Wafer processing method
WO2015134200A2 (en) Baking tool for improved wafer coating process
JP2014017434A (en) Method for processing wafer
KR20120023258A (en) Wafer processing method and wafer processing apparatus
WO2001057922A1 (en) Method and apparatus for singulation of electronic devices
JP7401183B2 (en) Wafer processing method
JP2003037085A (en) Method and apparatus for cutting substrate using laser irradiation
Toftness et al. Laser technology for wafer dicing and microvia drilling for next generation wafers
US11393697B2 (en) Semiconductor chip gettering
JPH1140523A (en) Substrate cutting device and substrate cutting method
Wang et al. Reliability of High Density Wire Bonding in X band T/R Module
KR20100126114A (en) Laser manufacturing apparatus and method for emc
Shimizu et al. Laser ablation of silicon wafer with a water microdrop
Shimizu et al. Laser ablation with water micro-drop for dicing of silicon wafer

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP