WO2001037102A2 - Modele de face arriere de bus vme virtuel tolerant aux pannes - Google Patents

Modele de face arriere de bus vme virtuel tolerant aux pannes Download PDF

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Publication number
WO2001037102A2
WO2001037102A2 PCT/US2000/031405 US0031405W WO0137102A2 WO 2001037102 A2 WO2001037102 A2 WO 2001037102A2 US 0031405 W US0031405 W US 0031405W WO 0137102 A2 WO0137102 A2 WO 0137102A2
Authority
WO
WIPO (PCT)
Prior art keywords
vmebus
backplane
vmebus backplane
bridge
fault
Prior art date
Application number
PCT/US2000/031405
Other languages
English (en)
Other versions
WO2001037102A3 (fr
Inventor
Thomas A. Odegard
Aaron Levine
Bryan P. Hansen
Larry J. Thomas
Original Assignee
Honeywell Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to IL14973000A priority Critical patent/IL149730A0/xx
Application filed by Honeywell Inc. filed Critical Honeywell Inc.
Priority to NZ519577A priority patent/NZ519577A/en
Priority to KR1020027006389A priority patent/KR20020053086A/ko
Priority to AT00977230T priority patent/ATE261144T1/de
Priority to DK00977230T priority patent/DK1232440T3/da
Priority to EP00977230A priority patent/EP1232440B1/fr
Priority to AU14899/01A priority patent/AU768503B2/en
Priority to JP2001539127A priority patent/JP2003515220A/ja
Priority to DE60008785T priority patent/DE60008785T2/de
Priority to CA002392108A priority patent/CA2392108A1/fr
Publication of WO2001037102A2 publication Critical patent/WO2001037102A2/fr
Publication of WO2001037102A3 publication Critical patent/WO2001037102A3/fr
Priority to IL149730A priority patent/IL149730A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling

Definitions

  • the invention relates to Versa Module Eurocards (VME) backplanes
  • VME-based technology for future system designs.
  • VME backplane technology has problems in certain
  • VME backplane is very susceptible to single point failures.
  • a device manufactured by CES including a 10MB/s VME-to-VMEbus
  • this system does not provide a direct connected system with fault-tolerant capability. Both sides must be capable of acting as
  • both sides must be capable of acting as independent systems as well as one virtual system.
  • SBS Bit 3's Model 418 and 418-50 are high-performance repeaters for VMEbus systems.
  • a SBS Bit 3 repeater extends a VMEbus backplane from one chassis to a second VMEbus chassis. Both chassis
  • the primary chassis can operate as a stand-alone system; it does
  • the secondary chassis does not have a system controller; consequently, it cannot operate without the primary
  • Multimaster which allows multiple VMEbus masters in all chassis software. In the transparent mode the system allows direct communication from primary chassis to secondary chassis with no software overhead
  • window in one chassis can be mapped to any window in the other chassis (e.g., extended supervisory to short nonprivileged).
  • Window sizes are jumper selected from 256 byte to 16 Mbyte (power of two sizes, i.e., 256,
  • the product is compliant to VMEbus Rev. C.1 and supports 8-, 16-, and 32-bit Transfers (bidirectional), supports 16-, 24-, and
  • 32-bit addressing (bidirectional), has two boards and two cables (in a variety of cable lengths), form a VME-to-VME link with automatic detection of
  • remote chassis power up and supports multiple links to the same chassis.
  • the system repeats DO to D31 , A1 to A23, LWORD*, AS * , DSO*, DS1 * .
  • AMO to AM5, DTACK*, and BERR * The problems with this device are it does not provide a direct connected system with fault-tolerant capability and both
  • VMEbus bridge operates as one VMEbus backplane.
  • a preferred fault tolerant virtual VMEbus backplane for computer systems comprise at least two VMEbus backplanes, each VMEbus backplane comprising a power supply and a fault detection apparatus and at
  • each bridge module comprising a switch for connecting and disconnecting each of the VMEbus backplanes.
  • VMEbus backplanes comprise a monolithic structure.
  • the preferred fault detection apparatus comprises a fail discrete in each bridge module.
  • the fault detection apparatus can also comprise fail discretes in preselected modules connected to each VMEbus backplane.
  • detection apparatus preferably comprises a fault detection apparatus in
  • each VMEbus backplane and a transmitter for transmitting the fault signal to a next VMEbus backplane comprise module fail discretes and VMEbus backplane communication tests.
  • the preferred VMEbus backplane communication tests comprise a data transfer bus test, an arbitration bus
  • the bridge modules preferably comprise a structure to connect the VMEbus backplanes to appear as a single VMEbus backplane.
  • the structure to connect the VMEbus backplanes to appear as a single VMEbus backplane comprises direct connections between the at least two VMEbus backplanes.
  • the preferred apparatus further comprises structure to minimize data transmission latency
  • two VMEbus backplanes comprises a direct connection between the at least two VMEbus backplanes.
  • a first computer system comprising a first VMEbus
  • backplane comprises the steps of detecting a fault status in the first and the next computer system, transmitting the fault status to the other computer system, connecting the first VMEbus backplane to the next VMEbus
  • the method further comprises the step of minimizing data transmission latency delays between the first computer system and the next computer system.
  • backplane is connected to a primary bridge and the second VMEbus
  • the step of testing the first VMEbus backplane and the second VMEbus backplane for faults comprises testing in the primary bridge and the secondary bridge.
  • backplane further comprises the step of configuring the first VMEbus backplane as a system controller and configuring the second VMEbus as a non-system controller.
  • the step of connecting the first VMEbus backplane to the secondary VMEbus backplane comprises connecting the first VMEbus
  • the secondary VMEbus backplane with one-for-one connections comprises connecting the first VMEbus backplane to the secondary VMEbus backplane
  • the preferred step of isolating the first VMEbus backplane from the secondary VMEbus backplane and operating in a degraded mode further comprises making the second
  • VMEbus backplane the system controller if the fault signal is transmitted by the primary bridge.
  • the secondary VMEbus backplane and isolating the first VMEbus backplane from the secondary VMEbus backplane comprise decision making logic resident in the primary bridge and the secondary bridge.
  • An object of the present invention is to provide a fault tolerant capability for a VME backplane.
  • Another object of the present invention is to provide a virtual bridge connection between two VME backplanes.
  • Yet another object of the present invention is to provide a fault
  • One advantage of the present invention is that it is transparent to the user and operates like a single VMEbus backplane.
  • Another advantage of the present invention is that it provides low latency high bandwidth data transfers.
  • Another advantage of the present invention is its versatility in that the system can be configured in a variety of ways.
  • Fig. 1 is a block diagram of the top level of the fault-tolerant
  • Fig. 2 is a drawing of the top backplane board outline in accordance
  • Fig. 3 is a drawing of the bottom backplane board outline in
  • Fig. 4 is a block diagram of the bridge module in accordance with the
  • Fig. 5 (5A-5C) are flow charts showing the bridge switch control logic with
  • FIG. 5A showing the initialization and power up test in accordance with the present invention
  • FIG. 5B showing the backplane interconnect logic in accordance with the present invention.
  • FIG. 5C showing the fault processing in accordance with the present invention
  • Fig. 6 is a diagram of the data transfer bus interconnect in accordance with the present invention.
  • Fig. 7 is a diagram of the arbitration bus interconnect in accordance with the present invention.
  • Fig. 8 is a diagram of the priority interrupt bus interconnect in accordance with the present invention.
  • the fault-tolerant VMEbus backplane includes two or more independent backplanes that are electrically connected by bridge module(s) between each backplane.
  • the system includes two
  • VMEbus backplanes 10 and 14 independent VMEbus backplanes 10 and 14.
  • backplane 10 is represented on the bottom of the diagram while the
  • backplane contains a bridge module for interconnecting the VMEbus
  • Primary backplane 10 contains primary bridge module 12.
  • Primary bridge module 12 is physically and electrically connected to primary
  • Secondary backplane 14 contains a functionally identical
  • Secondary bridge module 16 is physically and
  • Interconnect bus 18 can be directly
  • the bridge modules 12 and 16 for each VMEbus backplane reside in slot 1
  • VMEbus backplanes 10 or 14 are the system
  • VMEbus backplane per the VMEbus backplane specification (American National Standard for VME64 ANSI/VITA 1-1994).
  • the physical design for the fault-tolerant virtual bus backplane can be either a monolithic design in which both VMEbusses as well as the
  • interconnect bus are located on one PWB substrate or can be physically separate backplanes with an interconnect harness between them (not shown).
  • interconnect harness between them
  • Fig. 2 shows the top view
  • Fig. 3 shows the bottom of a 14-slot monolithic backplane design.
  • the maximum number of allowable slots is limited to 21 -slots per the VME standard.
  • Bridge modules 12 and 16 provide the logic and/or control for
  • interconnect bus 18 A detailed block diagram of the preferred bridge
  • Local bridge busses 30 and 32 provide a means of
  • each bridge module 12 and 16 contain all the necessary
  • the fail/ready discretes 26 also provide a means to communicate fault conditions in event of a bus failure.
  • FIGS. 5A, 5B, and 5C illustrate the logic used for initialization, test, and backplane interconnect.
  • bridge module is responsible for directing system initialization 36 at a backplane level (individual modules are responsible for their own
  • power-up self-test 38 of the system including backplane read/write tests 40, bus arbitration test 42,
  • each bridge 12 and 16 will set their
  • the bridge in backplane 12 is capable of re-configuring from system
  • secondary bridge 100 will reconfigure as a non-
  • VMEbusses remain isolated and the system enters a degraded mode of operation 108.
  • Primary bridge 12 enters degraded mode of operation 108.
  • the VMEbus includes three different busses, as shown in Fig. 4; data transfer bus 48, arbitration bus 50, and priority interrupt bus 52.
  • modules 12 and 16 are responsible for interconnecting each one of these modules
  • Fig. 6 shows how the data transfer
  • bus is a direct one-for-one connection between primary backplane 10 local
  • control signals 84 and 90 are directly coupled between the two (or more)
  • bridge modules 12 and 16 can be backplanes via interconnect bus 18 located on bridge modules 12 and 16. In the event of a fault, either one or both of bridge modules 12 and 16 can be
  • backplanes can operate independently or as one virtual backplane depending on the configuration of the bridge modules by the end-user.
  • Fig. 7 is a diagram of the arbitration bus interconnect.
  • arbitration bus is a combination daisy-chained 53 and bussed signals bus 54, 56, and 58.
  • the arbitration bus is responsible for arbitrating the control of the
  • bus mastership data transfer bus (bus mastership) in a multiple master system as defined in
  • BCLR * bus clear
  • BSSY * bus busy
  • backplane 10 be wrapped around and routed over to the bridge module 16
  • backplane 14 (or #n) are in a non-system controller mode when the
  • bridge module 16 in this mode, bridge module 16 in
  • bridge module in primary backplane 10 signals 54, 56, 58, and 64
  • Fig. 8 shows a diagram of how the priority interrupt bus is
  • bus is also a daisy-chained/bussed signal bus 66, similar to the arbitration bus.
  • IACK_OUT 68 must be wrapped around from the last module in primary
  • interrupts 1 -7 (IRQ1 * -IRQ7 * ) 72 and interrupt acknowledge
  • (IACK * ) 74 are direct one-for-one connection between primary backplane 10
  • VMEbus interconnect bus
  • secondary backplane 14 VMEbus secondary backplane

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Hardware Redundancy (AREA)
  • Fireproofing Substances (AREA)
  • Curing Cements, Concrete, And Artificial Stone (AREA)
  • Bidet-Like Cleaning Device And Other Flush Toilet Accessories (AREA)
  • Train Traffic Observation, Control, And Security (AREA)
  • Bus Control (AREA)
  • Laying Of Electric Cables Or Lines Outside (AREA)
  • Insulated Conductors (AREA)
  • Debugging And Monitoring (AREA)

Abstract

La présente invention concerne un modèle de système de face arrière pour module Eurocard Versa doté d'une fonctionnalité de tolérance aux pannes, qui est destiné aux applications de haute fiabilité. Selon l'invention, on relie électriquement deux faces arrières indépendantes (10,14) l'une à l'autre, tout en prévoyant des fonctionnalités d'isolation dans le cas d'une défaillance. Le modèle de connexion électrique, ou pontage intégré, assure une connexion virtuelle entre les deux faces arrières du VME (10,14) qui est transparente pour l'utilisateur final. Le modèle de bus VME virtuel intégré de l'invention présente un temps de latence faible, une interconnexion à largeur de bande élevée entre les modules (12,16), que ceux-ci soient placés sur le même bus local (10,14) ou sur le bus pouvant être isolé électriquement (18). Le modèle de face arrière de VME double tolérant aux pannes de l'invention permet d'éliminer les pannes de système totales qui étaient provoquées par une défaillance due à un seul événement.
PCT/US2000/031405 1999-11-18 2000-11-15 Modele de face arriere de bus vme virtuel tolerant aux pannes WO2001037102A2 (fr)

Priority Applications (11)

Application Number Priority Date Filing Date Title
EP00977230A EP1232440B1 (fr) 1999-11-18 2000-11-15 Modele de face arriere de bus vme virtuel tolerant aux pannes
NZ519577A NZ519577A (en) 1999-11-18 2000-11-15 Fault tolerant virtual VMEbus backplane design between two independently capable VMEbuses
KR1020027006389A KR20020053086A (ko) 1999-11-18 2000-11-15 고장허용 가상 ｖｍｅ버스 백플래인
AT00977230T ATE261144T1 (de) 1999-11-18 2000-11-15 Fehlertolerante virtuelle rückwand für vmebus
DK00977230T DK1232440T3 (da) 1999-11-18 2000-11-15 Fejltolerant virtuel bundkortudformning til VMEbus
IL14973000A IL149730A0 (en) 1999-11-18 2000-11-15 FAULT TOLERANT VIRTUAL VMEbus BACKPLANE DESIGN
AU14899/01A AU768503B2 (en) 1999-11-18 2000-11-15 Fault tolerant virtual VMEbus backplane design
CA002392108A CA2392108A1 (fr) 1999-11-18 2000-11-15 Modele de face arriere de bus vme virtuel tolerant aux pannes
DE60008785T DE60008785T2 (de) 1999-11-18 2000-11-15 Fehlertolerante virtuelle rückwand für vmebus
JP2001539127A JP2003515220A (ja) 1999-11-18 2000-11-15 フォールト・トレラント仮想ＶＭＥｂｕｓバックプレーン設計
IL149730A IL149730A (en) 1999-11-18 2002-05-19 VMEbus Virtual Screen Background Design is flawless

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/442,702 1999-11-18
US09/442,702 US6564340B1 (en) 1999-11-18 1999-11-18 Fault tolerant virtual VMEbus backplane design

Publications (2)

Publication Number Publication Date
WO2001037102A2 true WO2001037102A2 (fr) 2001-05-25
WO2001037102A3 WO2001037102A3 (fr) 2001-12-13

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Application Number Title Priority Date Filing Date
PCT/US2000/031405 WO2001037102A2 (fr) 1999-11-18 2000-11-15 Modele de face arriere de bus vme virtuel tolerant aux pannes

Country Status (14)

Country Link
US (1) US6564340B1 (fr)
EP (1) EP1232440B1 (fr)
JP (1) JP2003515220A (fr)
KR (1) KR20020053086A (fr)
AT (1) ATE261144T1 (fr)
AU (1) AU768503B2 (fr)
CA (1) CA2392108A1 (fr)
DE (1) DE60008785T2 (fr)
DK (1) DK1232440T3 (fr)
ES (1) ES2215753T3 (fr)
IL (2) IL149730A0 (fr)
NZ (1) NZ519577A (fr)
TW (1) TW486627B (fr)
WO (1) WO2001037102A2 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633996B1 (en) * 2000-04-13 2003-10-14 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus architecture
US6708283B1 (en) 2000-04-13 2004-03-16 Stratus Technologies, Bermuda Ltd. System and method for operating a system with redundant peripheral bus controllers
US6874052B1 (en) * 2000-09-29 2005-03-29 Lucent Technologies Inc. Expansion bridge apparatus and method for an I2C bus
US7467179B2 (en) * 2002-05-24 2008-12-16 Radisys Canada Inc. Backplane architecture for a data server
US20050246474A1 (en) * 2004-04-29 2005-11-03 Wolfe Sarah M Monolithic VMEbus backplane having VME bridge module
US20050246476A1 (en) * 2004-04-29 2005-11-03 Wolfe Sarah M Method and apparatus of regenerating data signal in monolithic VMEbus backplane
US6996643B2 (en) * 2004-04-29 2006-02-07 Motorola, Inc. Method of VME module transfer speed auto-negotiation
US20070136631A1 (en) * 2005-11-19 2007-06-14 Govani Atul V Method and system for testing backplanes utilizing a boundary scan protocol
US10291415B2 (en) * 2014-05-20 2019-05-14 Bosch Automotive Service Solutions Inc. Embedded extensible instrumentation bus
KR20160011427A (ko) 2014-07-22 2016-02-01 대우조선해양 주식회사 고장탐지가 가능한 시스템 레셋 독립 원격 제어용 산업용 버스 백플레인

Citations (1)

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WO1997032252A1 (fr) * 1996-02-27 1997-09-04 Data General Corporation Systeme de pile de disques dynamiquement extensible et systeme associe de multiplexage de signaux orthogonaux

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JP3206006B2 (ja) * 1991-01-25 2001-09-04 株式会社日立製作所 二重化バス制御方法及び装置
KR100244836B1 (ko) * 1995-11-02 2000-02-15 포만 제프리 엘 컴퓨터시스템 및 다수의 기능카드 중 한개의 기능카드를 격리하는 방법
US6076142A (en) * 1996-03-15 2000-06-13 Ampex Corporation User configurable raid system with multiple data bus segments and removable electrical bridges
US6052753A (en) * 1997-01-21 2000-04-18 Alliedsignal Inc. Fault tolerant data bus

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
WO1997032252A1 (fr) * 1996-02-27 1997-09-04 Data General Corporation Systeme de pile de disques dynamiquement extensible et systeme associe de multiplexage de signaux orthogonaux

Non-Patent Citations (1)

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Title
H. STRASS: "Verteilte Rechenaufgaben" ELEKTONIK, June 1999 (1999-06), pages 96-100, XP000902687 *

Also Published As

Publication number Publication date
ATE261144T1 (de) 2004-03-15
DE60008785T2 (de) 2005-01-20
CA2392108A1 (fr) 2001-05-25
AU768503B2 (en) 2003-12-11
ES2215753T3 (es) 2004-10-16
AU1489901A (en) 2001-05-30
IL149730A (en) 2007-06-03
KR20020053086A (ko) 2002-07-04
WO2001037102A3 (fr) 2001-12-13
US6564340B1 (en) 2003-05-13
NZ519577A (en) 2004-05-28
EP1232440A2 (fr) 2002-08-21
TW486627B (en) 2002-05-11
JP2003515220A (ja) 2003-04-22
DK1232440T3 (da) 2004-06-01
DE60008785D1 (de) 2004-04-08
IL149730A0 (en) 2002-11-10
EP1232440B1 (fr) 2004-03-03

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