WO2001028242A1 - Procede et systeme permettant d'eliminer les effets de bord au debut des lignes dans les signaux video - Google Patents

Procede et systeme permettant d'eliminer les effets de bord au debut des lignes dans les signaux video Download PDF

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Publication number
WO2001028242A1
WO2001028242A1 PCT/US2000/027146 US0027146W WO0128242A1 WO 2001028242 A1 WO2001028242 A1 WO 2001028242A1 US 0027146 W US0027146 W US 0027146W WO 0128242 A1 WO0128242 A1 WO 0128242A1
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WIPO (PCT)
Prior art keywords
pixel
filter
hfc
line
input
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PCT/US2000/027146
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English (en)
Inventor
Dinakaran Chidambaram
Thomas Edward Horlander
John William Gyurek
Guenter Anton Grimm
Original Assignee
Thomson Licensing S.A.
Deutsche Thomson-Brandt Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Thomson Licensing S.A., Deutsche Thomson-Brandt Gmbh filed Critical Thomson Licensing S.A.
Priority to AU77471/00A priority Critical patent/AU7747100A/en
Publication of WO2001028242A1 publication Critical patent/WO2001028242A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0135—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0414—Vertical resolution change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0421—Horizontal resolution change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present invention generally relates to a video signal processing system suitable for converting video signal formats.
  • the present invention relates to a video signal processing system, which comprises a vertical format converter (VFC) and a horizontal format converter (HFC), for converting video signal formats.
  • VFC vertical format converter
  • HFC horizontal format converter
  • Overscan refers to a technique to create an image that is larger than that is actually displayed on a display screen with aberrant edge effects (i.e. horizontal and vertical thin bars on the edges of an image). Because overscan region of an image extends beyond visible region of a display screen, the edge effects or artifacts of the image will not be shown on the display screen.
  • FIG. 1 shows a conventional CRT (cathode ray tube) display 1 00 that displays approximately 93% of an image on a display screen 1 02. The overscan region 1 04 is masked to ensure that edge effects or artifacts will not be displayed on the display screen 1 02.
  • FIG. 2 shows a conventional digital display 1 1 0 on which an entire image is displayed on the digital display panel 1 1 2. As a result, the edge effects or artifacts 1 1 4 are visible.
  • a typical television broadcast station sends out video signals in a standard resolution. The video signals are presented as a series of frames. Each of the frames contains a plurality of lines, and each of the lines contains a plurality of pixels.
  • a conventional digital video processing system typically has a main-channel format converter (FMC) that further comprises a vertical format converter (VFC) and a horizontal format converter (HFC) .
  • FMC main-channel format converter
  • VFC vertical format converter
  • HFC horizontal format converter
  • the HFC portion of the system performs format conversion in horizontal direction
  • the VFC portion of the system performs format conversion in vertical direction.
  • the VFC portion of the system typically includes a memory to store lines of "previous" and "future" pixels. These stored pixel lines are then used to compute the current line of video signals.
  • the HFC portion of the system typically includes a multi-tap filter that performs computing functions on the received video pixels line by line.
  • a multi-tap filter that performs computing functions on the received video pixels line by line.
  • the filter typically would compute zero values.
  • a relatively abrupt transition occurs from computing actual pixel data to computing zero values, thereby producing a visible edge effects or artifacts in the form of a thin bar on the horizontal edges of the display.
  • the first referred to as vertical “filter run-in” occurs at the beginning of frame intervals.
  • the second referred to as vertical “filter runout”, occurs at the end of frame intervals.
  • filter run-in occurs at the beginning of line intervals.
  • filter run-out occurs at the end of line intervals.
  • the present invention provides a method and system for processing digital video signals without generating edge effects or artifacts at the beginning of line intervals.
  • the present invention provides a method for processing pixel lines line by line for a display device.
  • Each of the pixel lines contains a plurality of pixels and has a beginning position.
  • the method includes the steps of: receiving a plurality of pixels, processing the received pixels, outputting the processed pixels to the display device, detecting a beginning position for a pixel line, and eliminating edge effects or artifacts on the display device upon the detection of the beginning position of the pixel line.
  • the present invention also provides the apparatus to perform the steps in above-described method.
  • FIG . 1 shows a conventional CRT display screen that displays approximately 93% of an image on a display screen
  • FIG. 2 shows an image that is displayed on a plasma display with edge effects or artifacts
  • FIG. 3 is a block diagram for an exemplary digital video receiving system that operates according to the principle of the invention
  • FIG. 4 is a block diagram for an exemplary MFC (main-channel format converter);
  • FIG. 5 is a Table I showing the definition for four control signals;
  • FIG. 6 is a Table II showing the definition showing the definition for a set of registers
  • FIG. 7 is a block diagram for an exemplary luma HFC (horizontal format converter);
  • FIG. 8 is a block diagram for an exemplary chroma HFC;
  • FIG. 9 is a block diagram for an exemplary HFC luma filter
  • FIG. 1 0 is a block diagram for an exemplary HFC chroma filter
  • FIG. 1 1 is a block diagram for an exemplary HFC luma control
  • FIG. 1 2 is a block diagram for an exemplary HFC chroma control
  • FIG. 1 3 is a block diagram for an exemplary luma input buffer
  • FIG. 1 4 is a block diagram for an exemplary luma forcing block
  • FIG. 1 5 is a block diagram for an exemplary chroma forcing block
  • FIG. 1 6A shows the contents in the HFC luma filter and HFC chroma filter during three read accesses when UC PSTEP INIT is 0 and zoom factor is 0.5
  • FIG. 1 6B shows the contents in the HFC luma filter and HFC chroma filter during three read accesses when UC_PSTEP_INIT is 4096 and zoom factor is 0.5;
  • FIG. 1 6C shows the contents in the HFC luma filter and HFC chroma filter during three read accesses when UC PSTEP INIT is 81 92 and zoom factor is 0.5;
  • FIG . 1 7 is a coefficient table for the VFC luma filter.
  • FIG. 1 8 is a coefficient table for the VFC chroma filter.
  • FIG. 3 there is shown a block diagram of an exemplary digital video receiving system 300 that operates according to the principles of the invention.
  • the video receiver system includes an antenna 1 0 and input processor 1 5 for receiving and digitizing a broadcast carrier modulated with signals carrying audio, video, and associated data, a demodulator 20 for receiving and demodulating the digital output signal from input processor 1 5, and a decoder 30 outputting a signal that is trellis decoded, mapped into byte length data segments, de-interleaved, and Reed-Solomon error corrected.
  • the corrected output data from decoder unit 30 is in the form of an MPEG compatible transport data stream containing program representative multiplexed audio, video, and data components.
  • a processor 25 processes the data output from decoder 30 such that the processed data can be displayed on a HDTV plasma display unit 75 in accordance with requests input by a user via a remote control unit 1 25. More specifically, processor 25 includes a controller 1 1 5 that interprets requests received from remote control unit 1 25 via remote unit interface 1 20 and appropriately configures the elements of processor 25 to carry out user requests (e.g., channel, website, and/or OSD display). In one exemplary mode, controller 1 1 5 configures the elements of processor 25 to provide MPEG decoded data and an OSD for display on display unit 75.
  • controller 1 1 5 configures the elements of processor 25 to provide MPEG decoded data and an OSD for display on display unit 75.
  • Processor 25 includes a decode PID selection unit 45 that identifies and routes selected packets in the transport stream from decoder 30 to transport decoder 55.
  • the transport stream from decoder 30 is demultiplexed into audio, video, and data components by transport decoder 55 and is further processed by the other elements of processor 25, as described in further detail below.
  • the transport stream provided to processor 25 comprises data packets containing program channel data, ancillary system timing information, and program specific information such as program content rating and program guide information.
  • Transport decoder 55 directs the ancillary information packets to controller 1 1 5 which parses, collates, and assembles the ancillary information into hierarchically arranged tables. Individual data packets comprising the user selected program channel are identified and assembled using the assembled program specific information.
  • the system timing information contains a time reference indicator and associated correction data (e.g. a daylight savings time indicator and offset information adjusting for time drift, leap years, etc.).
  • This timing information is sufficient for a decoder to convert the time reference indicator to a time clock (e.g., United States east coast time and date) for establishing a time of day and date of the future transmission of a program by the broadcaster of the program.
  • the time clock is useable for initiating scheduled program processing functions such as program play, program recording, and program playback.
  • the program specific information contains conditional access, network information, and identification and linking data enabling the system of FIG. 3 to tune to a desired channel and assemble data packets to form complete programs.
  • the program specific information also contains ancillary program content rating information (e.g., an age based suitability rating), program guide information (e.g., an Electronic Program Guide - EPG) and descriptive text related to the broadcast programs as well as data supporting the identification and assembly of this ancillary information.
  • ancillary program content rating information e.g., an age based suitability rating
  • program guide information e.g., an Electronic Program Guide - EPG
  • descriptive text related to the broadcast programs as well as data supporting the identification and assembly of this ancillary information.
  • Transport decoder 55 provides MPEG compatible video, audio, and sub- picture streams to MPEG decoder 65.
  • the video and audio streams contain compressed video and audio data representing the selected channel program content.
  • the sub-picture data contains information associated with the channel program content such as rating information, program description information, and the like.
  • MPEG decoder 65 cooperates with a random access memory (RAM) 67 to decode and decompress the MPEG compatible packetized audio and video data from unit 55 and derives decompressed program representative pixel data. Decoder 65 also assembles, collates and interprets the sub-picture data from unit 55 to produce formatted program guide data for output to an internal OSD module.
  • the OSD module cooperates with RAM 67 to process the sub-picture data and other information to generate pixel mapped data representing subtitling, control, and information menu displays including selectable menu options and other items for presentation on display device 75 in accordance with the present invention.
  • the control and information displays including text and graphics produced by the OSD module, are generated in the form of overlay pixel map data under direction of controller 1 1 5.
  • the overlay pixel map data from the OSD module is combined and synchronized with the decompressed pixel representative data from MPEG decoder 65 under direction of controller 1 1 5.
  • Combined pixel map data representing a video program on the selected channel together with associated sub-picture data is encoded by decoder/processor 65 and output to plasma display device 75, via display drivers 80, for display.
  • MFC 400 includes a VFC (Y) 402, a VFC (U, V) 403, an HFC (Y) 404 and an HFC (U, V) 405.
  • VFC (Y) 402 the color of a pixel can be represented as a dot position in a three-dimensional color space.
  • a color space is a mathematical representation of a set of colors.
  • One color model is called YUV color space, in which color representation is divided into two components, namely, luminance (Y) information and chrominance information (U and V) .
  • a black-white receiving system uses only luminance (Y) information; chrominance (or color) information (U and V) is added in such a way that a black-white receiving system still displays a normal black-white picture.
  • a color receiving system decodes both luminance and chrominance information to display a color picture.
  • the components in FIG. 4 are therefore deployed in two functional sets.
  • the first set of components 402 and 404 is used to process signals and data for luminance (luma)
  • the second set of components 403 and 405 is used to process signals and data for chrominance (chroma).
  • MFC 400 receives a serial (8 bit wide) progressive or interlace (4:2:0 or
  • the MFC output can be progressive or interlace (4:2:2) .
  • the FMC uses handshake signals (RTS and RTR) for data flow control between each block.
  • RTS stands for Ready To Send, and RTR for Ready To Receive.
  • MFC 400 can perform a linear or non-linear zoom in both vertical and horizontal directions.
  • An external microprocessor sets zoom ratio for MFC 400.
  • the limit of vertical conversion is given by input and output clock frequency and line length of input.
  • MFC 400 has the following features:
  • zone 1 , 2, 4 or 5 has a free programmable zoom change per pixel/line
  • VJID Input field ID
  • V OID Output field ID
  • V_RST_DR is used as field /frame reset signal.
  • H/2, H/4, V/2 and V/4 decimation modes change the spatial position.
  • the VFC (402 or 403) or HFC (404 or 405) has an automatic phase correction.
  • Five signals (disp_h2, disp_h4, disp_v2, disp_v4, and xcomp type) are used to detect decimation modes. The definition of these three signals is listed in Table I as shown in FIG. 5.
  • the VFC (402 or 403) assumes that V/2 or V/4 decimation must be done in a field when the VFC input is interlace, and that the V2 or V4 decimation must be done in a frame when the VFC input is progressive.
  • the present invention defines a quantity of steps between two input lines or pixels. The number of steps for vertical dimension (i.e. DISTANCE) depends on the input format, as follows:
  • DISTANCE 1 6384.
  • the number of steps in horizontal direction is defined to 81 92.
  • the present invention defines two programmable values LSTEP and PSTEP as the distance of two output lines or pixels. With this definition, the present invention derives the following formulas:
  • UC xxxx denotes micro control registers, which can either be mapped to input/output ports or to memory. These are the registers used for controlling the behavior of the concerned algorithms. The values of these registers are written by an external microprocessor. The definitions of these registers are listed in table II as shown in FIG. 6.
  • VFC (402 or 403) can perform a linear or non-linear conversion (i.e., expansion or depression) in vertical direction for MFC 400.
  • the input and output of the VFC can be interlace or progressive depending on UC_VIID and
  • VFC output is 4:2:2.
  • the vertical zooms can be linear or non-linear. For this reason, the display is divided into five zones. Four of the five zones have a programmable zoom change per line.
  • the maximum vertical compression depends on the relation of the line length and clock frequency of the input and display of the VFC (402 and
  • the zoom factor can be calculated by the following formula:
  • the HFC (404 or 405) can perform a linear or non-linear conversion in horizontal direction for MFC 400 in a range from 0.33 to 6.
  • a programmable input line length (UC HINP, UC_YHIL or UC_CHINL) is available in the VFC (402 or 403) .
  • the HFC (404 or 405) can also process a pan on subpixels and a phase correction for horizontal decimation modes. The resolution is 1 /1 6.
  • the change of aspect ratio is performed by the HFC luma (or chroma) filter, which will be further discussed below. In case of expansion, a certain re-used/read algorithm on input pixels is used according to zoom relation.
  • the algorithm selects one, two or three input pixels (i.e., Y PXL1 , Y PLX2 and Y_PLX3 for luma; or C_PXL1 , C PLX2 and C PLX3 for chroma) in parallel.
  • the coefficients for calculation are selected according to calculated phases.
  • the HFC luma filter includes a luma input buffer (FIFO) 702 for generating Y_PXL1 , Y PXL2 and YPXL3 in response to luma pixel inputs (Y HFCJN), an HFC (luma) filter 704 for generating luma pixel outputs (Y_HFC_OUT), an HFC (luma) control 706 for generating control signals and a coefficient RAM 708, which has a phase to address conversion circuit, for generating coefficients (YC0, YC1 YC7) .
  • FIFO luma input buffer
  • FIFO luma input buffer
  • luma input buffer 702 is split into three parallel buffers (3x320 pixels) so that it is able to read three pixels in parallel. Data are written to the input buffer with 81 MHz clock and are also read from it with this clock. HFC control 706 selects the coefficients that are stored in coefficient RAM 708 and generates re-use/read signal to read the data from luma input buffer 702.
  • the data stored in luma input buffer 702 has the following format:
  • the HFC chroma filter includes a chroma input buffer (FIFO) 802 for generating C PXL1 , C_PXL2 and C_PXL3 in response to chroma pixel inputs (C HFCJN), an HFC (chroma) filter 804 for generating chroma pixel outputs (C_HFC_OUT), an HFC (chroma) control 806 for generating control signals and a coefficient RAM 808, which has a phase to address conversion circuit, for generating coefficients (CC0, CC1 , , and CC7) .
  • FIFO chroma input buffer
  • C HFCJN chroma input buffer
  • HFC (chroma) filter 804 for generating chroma pixel outputs
  • HFC (chroma) control 806 for generating control signals
  • HFC chroma filter 800 is in principle the same as that of HFC luma filter 700, except that an additional signal EN_U_PXL is needed for HFC chroma filter 804 to identify U and V pixels in an input line.
  • the data stored in luma input buffer 802 has the following format:
  • the write signal For chroma input filter 802, the write signal must start with a U pixel so that the order U, V can always be kept. Thus, a pair of read signals (or two reuse conditions) is necessary to calculate a new U and V pixel.
  • the U pixel calculation is performed with one of the two read signals (EN_U_PXL is low) and the V pixel calculation is performed with the other read signal (EN U PXL is high) .
  • FIG. 9 there is shown a block diagram for an exemplary HFC luma filter 900 illustrating further detail in HFC filter 704 (shown in FIG. 7) .
  • HFC luma filter includes a switch (SET Y DATA) 902, a multiplexer controller 904, a filter buffer 906 that further includes eight taps (TO, T1 , ..., T7; or 91 0,
  • Switch (SET_Y_DATA) 902 receives three inputs (Y_PXL1 , Y_PXL2 and Y_PXL3) at its three input terminals (11 , 12 and 13), and it also receives an input at its input terminal 14 from the output of tap 91 7 (which can be the last input pixel in an input line) .
  • Switch (SET Y DATA) 902 sets its data path to its three input terminals (11 , I2 and 13) under the control of Y PIC and UC_YHINL.
  • Multiplexer controller 904 generates an OUT signal in response to Y_PIC.
  • the OUT signal is low (0) when Y_PIC is 0; the OUT signal is high (1 ) when Y_PIC is 1 .
  • Each of the eight taps includes a four-way multiplexer having four input terminals (0, 1 , 2 and 3) for receiving three external inputs and a feedback input, and a D (flip-flop) register. Because an additional external input is needed, each of four taps 91 1 , 91 2, 91 3 and 914 further includes an additional two-way multiplexer having two input terminals (0 and 1 ).
  • the output of its four-way multiplexer is routed to its D register via input terminal 0 of its two-way multiplexer.
  • each output of the eight taps can be stored in its D register.
  • the stored output for each of the eight taps is routed to the input terminal 1 of the four-way multiplexer in the next-stage tap.
  • the stored output for each of the eight taps is also fed back to the tap via input terminal 0 of its four-way multiplexer.
  • Tap 910 receives three inputs from tap 911, tap 912 and tap 913.
  • Tap 911 receives four inputs from 01 (of switch 902), tap 912, tap 913 and tap
  • Tap 912 receives four inputs from 01 (of switch 902), tap 913, tap 914 and tap 915.
  • Tap 913 receives four inputs from 01 (of switch 902), tap 914, tap 915 and tap 916.
  • Tap 914 receives four inputs from 01 (of switch 902), tap 915, tap 916 and tap 917.
  • Tap 915 receives three input from 01 (of switch 902), tap 916 and tap 917.
  • Tap 916 receives three inputs from 01 and 02 (of switch 902) and tap 917.
  • Tap 917 receives three inputs from 01, 02 and 03 (of switch 902).
  • a four-way multiplexer Within each of four taps 910, 915, 916 and 917, a four-way multiplexer generates an output for its tap. Within each of four taps 912, 913, 914 and 915, a two-way multiplexer generates an output for the tap. Each output of the eight taps (910, 911, ..., or 917) is routed to a respective multipliers (920, 922, ..., or 927), where the tap output is multiplied with a respective coefficient (CYO, CY1, ..., or CY7).
  • the structure descried above enables the eight taps (910, 911, ..., 917) to perform buffer, shift or repeat function.
  • the outputs from multipliers 920, 921, 922 and 923 are routed to adder 932, and the outputs from multipliers 924, 925, 926 and 927 are routed to adder 934.
  • Adder 932 adds the four inputs it received and routes its output to D register 942.
  • Adder 934 adds the four inputs it received and routes its output to D register 944.
  • Adder 946 receives two inputs from D registers 944 and 942 and generates a sum value for these two inputs. For a particular pixel to be displayed on a display screen, the output from adder 946 represents its luma value.
  • Normalizer 950 truncates eight least significant bits in the output from adder 946 and routes its output to limiter 960.
  • Limiter 960 converts the output from normalizer 960 into a value between -128 and 127. Operating together, normalizer 950 and limiter 960 ensure that the output from HFC luma filter 900 is within a displayable
  • all four-way muxes are enabled by Y GO PXL REG, and all two-way muxes are enabled by the OUT signal, and all D registers are enabled by Y_FIL_EN and clocked by 81 MHz clock.
  • Each of the eight multipliers are enabled by Y GO PXL REG, and all two-way muxes are enabled by the OUT signal, and all D registers are enabled by Y_FIL_EN and clocked by 81 MHz clock.
  • D registers 942 and 944 are also enabled by Y FIL EN and clocked by 81
  • D register 962 is enabled by Y_OUTPUT_EN and clocked by 81
  • Y_GO_REG controls the shift function of HFC luma filter 900 when the filter is not operated in "filter run-in” or “filter run-out” mode. Specifically, none, one, two or three pixels are shifted through the filter corresponding to value of Y_G_ REG being 0, 1 , 2 and 3, respectively.
  • Y_FIL_EN enables the shift operation.
  • HFC luma filter 900 either repeats the last input pixel in an input line by switching the last input pixel to Y PXL1 , Y PXL2 and Y_PXL3; or switches Y_PXL2 to Y_PLX3 (when two pixels are before the end of an input line); or switches Y PXL1 to Y_PXL2 and Y_PLX3 (when one pixel before the end of an input line) .
  • switch (SET_Y_DATA) 902 sets its data path based on the values of Y_PIC and UC YHIL according to the following function:
  • UC_YHINL is the pixel number of a luma output line from HFC luma filter 900
  • Y_PIC contains the value of luma pixel input counter (see FIG. 1 1 below).
  • HFC luma filter 900 copies the first input pixel of an input line to next 4 filter taps.
  • Y_GO_REG has a value of 3 in first read access to the HFC luma filter for a new input line, which means that the first input pixel is read to taps T5, T4, T3, T2, T1 and TO with the copy function of CY5, CY4, CY3, CY2 and CY1 .
  • the contents in HFC luma filter 900 after the first read access are as follows:
  • Y GO REG has a value of
  • HFC luma filter 900 the contents in HFC luma filter 900 after the second read access are as follows:
  • HFC luma filter 900 starts to generate outputs.
  • HFC luma 900 generates an output at this time.
  • HFC luma filter 900 generates an output at this time.
  • FIG. 10 there is shown a block diagram for an exemplary HFC chroma filter 1000 illustrating further detail in HFC filter 804 (shown in FIG. 8).
  • the HFC chroma filter includes a switch (SET_C_DATA) 1002, a multiplexer controller 1004, a filter buffer 1006 that further includes eight taps (TO, T1, ...,
  • Switch (SET_C_DATA) 1002 receives three pixel inputs (C PXL1, C PXL2 and C_PXL3) at its three input terminals (11, 12 and 13), and it also receives two inputs at its two input terminals (14 and 15) from the outputs of taps 1016 and
  • Switch (SET_C_DATA) 1002 sets its data path to the three input terminals (11,
  • Multiplexer controller 1004 generates an OUT signal in response to C PIC and C_GO_PXL_REG.
  • the OUT signal is described by the following algorithm:
  • Each of the eight taps includes a four-way multiplexer having four input terminals (0, 1, 2 and 3) for receiving three external inputs and a feedback input, and a D (flip-flop) register. Because additional one or two external inputs are needed, each of four taps 1012, 1013, 1014 and 1015 includes an additional three-way multiplexer having three input terminals (0, 1 and 3). Within each of four taps 1010, 1011, 1016 and 1017, the output of its four-way multiplexer is directly routed to its D register. Within each of four taps 1012, 1013, 1014 and 1015, the output of its four-way multiplexer is routed to its D register via input terminal 0 of its three-way multiplexer.
  • each output of the eight taps can be stored in its D register.
  • the stored output for each of the eight taps is routed to the input terminal 1 of the four-way multiplexer in the next-stage tap.
  • the stored output for each of the eight taps is also fed back to the tap via input terminal 0 of its four-way multiplexer.
  • Tap 1010 receives three inputs from tap 1011, tap 1012 and tap 1013.
  • Tap 1011 receives three inputs from tap 1012, tap 1013 and tap 1014.
  • Tap 1012 receives four inputs from O1 (of switch 1002), tap 1013, tap 1014 and tap 1015.
  • Tap 1013 receives five inputs from 01 and 02 (of switch 1002), tap
  • Tap 1014 receives five inputs from 01 and 02
  • Tap 1015 receives four inputs from 02 (of switch 1002), tap 1016 and tap 1017.
  • Tap 1016 receives three inputs from 01 and 02 (of switch 1002) and tap 1017.
  • Tap 1017 receives three inputs from 01, 02 and 03 (of switch 1002).
  • a four-way multiplexer Within each of four taps 1010, 1011, 1016 and 1017, a four-way multiplexer generates an output for its tap. Within each of four taps 1012, 1013, 1014 and 1015, a two-way multiplexer generates an output for the tap. Each output (CO, C2, C4 or C6) of the four taps (1010, 1012, 1014 and 1016) is routed to a respective two-way multiplexer (1030, 1032, 1034 or 1036).
  • Each output (C1 , C3, C5 or C7) of the four taps (1011, 1013, 1015 and 1017) is routed to a respective D register (1021, 1023, 1025 and 1027), which further routes its output to a respective two-way multiplexer (1030, 1032, 1034 and 1036).
  • Each of the four two-way multiplexers (1030, 1032, 1034 or 1036) selects an output from a respective pair (a U, V pair) of tap outputs ((CO, C1), (C2, C3), (C4, C5) or (C6, C7), and routes the selected tap output to a respective multipliers (1040, 1041, 1042 or 1043), where each of the tap outputs is multiplied with a coefficient (CCO, CC1, CC2 and CC3).
  • the structure descried above enables the eight taps (910, 911, ..., 917) to perform buffer, shift or repeat function.
  • the four outputs from the multipliers (1040, 1041, 1042 and 1043) are routed to adder 1052, which generates a sum for the four outputs.
  • the output from adder 1052 represents its chroma value.
  • the output from adder 1052 is routed to D register 1062, where the output is further routed to normalizer 1064.
  • Normalizer 1064 truncates eight lease significant bits in the output from adder 1052 and routes the truncated value to limiter 1066.
  • Limiter 1066 converts the output from normalizer 1064 into a value between -128 and 127. Operating together, normalizer 1064 and limiter 1066 ensure that the output from HFC chroma filter 1000 is within a displayable range.
  • each of the four-way multiplexers is enabled by
  • each of the two-way multiplexers is enabled by OUT signal; each of the D registers is enabled by C FIL EN and clocked by 81 MHz clock.
  • the five D registers (1021, 1023, 1025, 1027 and 1062) are also enabled by C_FIL_EN and clocked by 81 MHz clock.
  • Each of the four two-way multiplexers (1030, 1032, 1034 or 1036) is enabled by EN_U_PXL (for selecting U, V).
  • Each of the four multipliers (1040, 1041, 1042 or 1043) is controlled by a respective coefficient (CCO, CC1, CC2 or CC3).
  • D register 1068 is enabled by C_OUTPUT_EN and clocked by 81 MHz clock.
  • C_GO_REG controls the shift function of HFC chroma filter 1000 when the filter is not operated in "filter run-in” or “filter run-out” mode. Specifically, none, one, two or three pixels are shifted through the filter corresponding to the value of C_G_ REG being 0, 1, 2 and 3, respectively.
  • C_FIL_EN enables the shift operation.
  • HFC chroma filter 1000 either repeats the last two input pixels (one is for U and the other is for V) in an input line by switching the last input pixel to C_PXL2 and the penultimate pixel to C_PXL1 and C PXL3; or switches C PXL1 to C PXL3 (when two pixels are before the end of an input line); or switches C_PXL1 to C_PXL3 and switches the last input pixel to C_PXL2 (when one pixel before the end of an input line).
  • switch (SET C DATA) 1002 sets its data path based on the values of C_PIC and UC_YHIL according to the following function:
  • UC CHINL is the pixel number of a chroma output line from HFC luma filter 1 000
  • C_PIC contains the value of chroma pixel input counter (see FIG. 1 2 below).
  • HFC chroma filter 1 000 copies the first two input pixels (one is for U and the other is for V) of an input line to next 4 or 2 filter taps.
  • C GO REG has a value of two or three.
  • the value of C_GO_REG is two or three.
  • the contents in the HFC chroma filter are as follows:
  • HFC chroma 1000 starts to generate outputs.
  • HFC luma control 1100 includes a DTO1 block 1102 for generating PSTEP, a DTO2 block 1104 for generating Y PHASE, an HFC coefficient RAM 1106 (which includes a phase to coefficient address conversion) for storing coefficients and providing coefficients YCO, YC1, ..., and YC7, a MOD2 block 1107 for generating Y_OUT_EN, a phase calculation block 1108 for generating Y_PHASE_INIT, a force Y GO PXL block 1110 for generating Y GO PXL, Y_GO_PXL_REG and YJNIT HFC, a read/write protection and HFC buffer control 1112 for generating Y WR EN, Y WMUX, Y_RD1_EN, Y RD2 EN, Y_RD3
  • Y OUTPUT EOL a pixel input counter 1116 for generating Y_PIC
  • Y_INPUT_EOL and an HFC decoder 1118 for generating PDELTA, Y_H_HFC,
  • Y_FIL_EN and Y OUTPUT EN are a function of handshaking signals (RTR, RTS) and the state of the HFC buffer (the number of pixels is available or not).
  • Y_OUT_EN signal controls pixel shift operation for HFC luma filter 900, and is used as enabling signal for DTO2 block 1104 and input counter 1116 (Y PIC).
  • Y_FIL_EN is shifting enabling signal for HFC luma filter 900.
  • Y OUT EN is output enabling signal for HFC luma filter 900 and pixel output counter 1114 (Y POC).
  • Y H HFC is reset pulse of pixel input counter 1116 (Y PIC), MOD2 block 1107 and pixel output counter 1114 (Y POC).
  • Y OUTPUT EOL indicates output end of line signal (it is high at the end of a line), and YJNPUT EOL indicates input end of a line signal (it is high at the end of a line).
  • the 32 different phases (using 5 bits) of HFC luma filter 900 are selected by DTO2 block 1104 (Y PHASE).
  • DTO2 block 1104 runs with a much higher resolution (13 bit) to be able to calculate sub-phases, which may not positioned exactly on the 1/32 filter raster.
  • DTO1 block 1102 counts PDELTA to PSTEP. PSTEP changes only in non-linear zoom mode.
  • DTO1 block 1102 runs half of Y_OUT_EN clock so that PSTEP can change after two new Y_OUT_EN pulses.
  • a set of control registers (UC_HZONE1 - UCJHZONE5, UC_PDELA1, UC_PDELA2, UC_PDELA4, UC PDELA5 and UC PSTEP) is used for controlling PDELTA value.
  • Five zones are available with four non-linear and one linear zoom factors.
  • Pixel output counter 1116 performs zone detection.
  • the value of Y GO PIXL is the number of pixels that are to be read for the next Y OUPUT EN.
  • the value of Y_GO_PXL_REG is the number of pixels that are to be shifted through the filter for the next output pixel.
  • force Y GO PXL block 1110 sets Y GO PXL, Y_GO_PXL_REG and YJNITJHFC to special values.
  • Y PHASEJNIT is the distance between the horizontal VFC output and the
  • HFC input start positions It is based on step definition between two input pixels (distance of two input pixels is 8192).
  • HFC luma filter 900 starts at the
  • UC_HINP position This position must be a multiple of 2 because the chroma and luma VFC output position must be the same (chroma input format is 4:2:2).
  • the UC PSPEPJNIT value has a range of two luma input pixels and is less than 2x8192.
  • Phase calculation block 1108 adds UC_PSTEP_INIT to a phase correction value to generate Y_PHASE_INIT.
  • the phase correction value in Y_PHASE_INIT depends on the horizontal decimation mode and is not the same for chroma and luma.
  • One additional input pixel is needed for luma when the start position for
  • FIG. 12 there is shown a block diagram for an exemplary
  • HFC chroma control 1200 illustrating further detail of HFC (U, V) 405 shown in FIG.4.
  • HFC chroma control 1200 includes a DTO1 block 1202 for generating PSTEP, a DTO2 block 1204 for generating C PHASE, an HFC coefficient RAM
  • a phase calculation block 1208 for generating C PHASEJNIT for generating C PHASEJNIT
  • a force C_GO_PXL block 1210 for generating C_GO_PXL, CJ3O PXL REG and CJNIT_HFC for generating C_WR_EN, C_WMUX, C_RD1_EN, C_RD2_EN, C RD3 EN, C RMUX and C_OUT_EN
  • HFC chroma control 1200 is in principle the same as that for HFC luma control 1100.
  • Phase calculation 1108 shown in FIG. 11 calculates the phase for luma according to the following algorithm:
  • Each zone has PDELTA value and is selected on the actual output pixel that is counted by POC.
  • the PDELTA value is the change of PSTEP per output pixel.
  • PDELPTA is described by the following algorithm:
  • Y_H_HFC and C_H_HFC are non-linear zoom functions for luma and chroma respectively and can be described by the following algorithm:
  • FIG. 1 3 there is shown a block diagram for an exemplary luma input buffer 1 300 illustrating further detail for input buffer 702 (shown in FIG. 7).
  • Y WMUX 2 the incoming pixel will be written to the last buffer. For each new input pixel Y_WMUX is (Y WMUX +1)%3. Up to three pixels can be read with one clock, which means the minimal zoom factor is 1/3. The maximum zoom factor is in principle not limited because a pixel can be repeated without limitaion. So Y GO PXL from the HFC control can be 0, 1 , 2 or 3.
  • the chroma input buffer has a similar structure as that of luma input buffer shown in FIG. 13. The operation of the chroma input buffer is in principle the same as that of the luma input buffer shown in FIG.13.
  • HFC luma control 1100 shown in FIG. 11 read/write protection and HFC buffer control 1112 controls the read and write operation of the HFC input buffer (702 in FIG.7).
  • the control is able to handle a read, a write and a parallel read and write. Internally it needs a counter for number of stored pixie in the
  • Y_WR_EN (2) changes the YJ/VMUX value to (Y WMUX + 1) % 3, and (3) increases the number of stored pixel. If InputRTR or InputRTS is low, the control clears YJ ⁇ /R EN. Read from the buffer: If Y GO PXL value is less than or equal to the number of stored pixel in the buffer, Y OutputRTS signal is high.
  • Y OutputRTS and Y_OutputRTR are high, the control does the following: (1) decodes Y RD1 EN, Y_RD2_EN and Y RD3 EN, (2) changes the Y_RMUX value to (Y_RMUX + YJ3O PXL) % 3, (3) sets the Y_OUT_EN signal, and (4) subtracts the Y GO PXL value from the old value to form the new number of stored pixel in the buffer. If Y OutputRTS or Y OutputRTR is low, the control clears Y_RD1_EN, Y_RD2_EN, Y_RD3_EN and Y_OUT_EN signals.
  • the pixel output counter value (Y POC or C_POC) is set to zero with a high RST signal. With a high EN signal, the counter value is incremented if the counter value is less than the END value. If the count value is equal to the END value, the end of line signal is high (Y_OUTPUT_EOL or C_OUTPUT_EOL).
  • the pixel input counter value (Y_PIC or C PIC) is set to zero with a high RST signal. With a high EN signal, the ADD value is added to the counter value if the counter value is less than the END value. If the count value is equal to the END value, the end of line signal is high (YJNPUT EOL or C JNPUT_EOL).
  • Forcing block 1400 includes a filter run-in block 1402, a forcing block 1404, a limitation block 1406 and a register 1408. Forcing block 1 400 performs control function for luma in "filter run-in" or
  • the forcing block sets Y_GO_PXL and Y_GO_PXL_REG to 3 and YJNIT HFC to 1 .
  • Y_GO_PXL and Y GO PXL is 1 , 2 or 3 (depends on UC PHASE INIT and decimation mode) and YJNIT HFC is low until the next new input line.
  • Y GO PXL and Y_GO_PXL_REG equal two
  • FIG. 1 5 there is shown a block diagram for an exemplary forcing block 1 500 illustrating further detail for force C_GO_PXL block 1 210 shown in FIG. 1 2.
  • Forcing block 1 500 has a similar structure as that of forcing block 1 400 shown in FIG. 1 4.
  • the control function of forcing block 1 500 is in principle the same as that of forcing block 1 300.
  • FIG. 1 6A there are shown the contents in HFC luma filter
  • HFC chroma filter 1 000 during three read accesses to the two filters when UC_PSTEPJNIT is 0 and zoom factor is 0.5.
  • FIG. 1 6B there are shown the contents in HFC luma filter
  • FIG. 1 6C there are shown the contents in HFC luma filter
  • FIG. 1 7 there is shown a coefficient table for the VFC luma filter.
  • HFC luma filter 900 and HFC chroma filter 1 000 can be bypassed by a register. Specifically, if register UC HFC THRU is set to 0, the coefficients from the coefficient RAM are applied. If it is set to 1 , the coefficient bypass mode is activated and the following coefficients are used:
  • HFC luma filter 900 and HFC chroma filter 1 000 can operate in a linear continuous horizontal zoom fashion.
  • zoom ratio is given by UC PSTEP register.
  • Write length to the input buffer is defined from UCJHINP to UCJHINP + UC_YHINL for VFC luma and from UC HINP to UC_HINP + UC_CHINL for VFC chroma.
  • UC_HZONE5 indicates total number of output pixels per pixel line. Continuous zoom is performed through changing registers UC PSTEP, UCJHZONE5, UC HINP, UC_YHINL and UC_CHINL by a program to run through the different zoom ratios one after another.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

L'invention concerne un procédé et un dispositif permettant de traiter les signaux vidéo devant être affichés sur un dispositif d'affichage numérique sans formation d'effets de bord ou d'artefacts au début des intervalles entre les lignes. De manière spécifique, les signaux vidéo sont constitués d'une pluralité de trames de pixels, chacune de ces trames étant elle-même constituée d'une pluralité de lignes de pixels. Un système de traitement de signal vidéo caractéristique comprend un convertisseur en format horizontal (HFC) (404 et 405) permettant de convertir des formats des signaux dans le sens horizontal. Un convertisseur HFC caractéristique comprend un filtre comprenant une pluralité de points de prélèvement (910-917) de pixels permettant de stocker les pixels qui peuvent servir à créer un pixel courant à afficher sur un dispositif d'affichage numérique. Cependant, au début d'une ligne de pixels, il n'y a pas assez de pixels disponibles pour tous les points de prélèvement de pixels, ce qui provoque des effets de bord ou des artefacts dans le sens horizontal sur le dispositif d'affichage numérique, au début des intervalles entre les lignes. On résout ce problème d'effet de bord ou d'artefact par la répétition (902 et 906) d'au moins un pixel placé en première position ou suivant immédiatement cette première position dans chacune des lignes de pixels.
PCT/US2000/027146 1999-10-12 2000-10-03 Procede et systeme permettant d'eliminer les effets de bord au debut des lignes dans les signaux video WO2001028242A1 (fr)

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US60/158,757 1999-10-12

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PCT/US2000/027146 WO2001028242A1 (fr) 1999-10-12 2000-10-03 Procede et systeme permettant d'eliminer les effets de bord au debut des lignes dans les signaux video
PCT/US2000/027149 WO2001028245A1 (fr) 1999-10-12 2000-10-03 Procede et systeme d'elimination des effets de bord aux extremites des lignes des signaux video
PCT/US2000/027148 WO2001028244A1 (fr) 1999-10-12 2000-10-03 Procede et systeme d'elimination des effets de bord au debut d'une trame de signaux video

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PCT/US2000/027148 WO2001028244A1 (fr) 1999-10-12 2000-10-03 Procede et systeme d'elimination des effets de bord au debut d'une trame de signaux video

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Publication number Priority date Publication date Assignee Title
US6765622B2 (en) * 2001-10-26 2004-07-20 Koninklijke Philips Electronics N.V. Line-buffer reuse in vertical pixel-processing arrangement
EP1506672A4 (fr) * 2002-05-17 2010-10-06 Thomson Licensing Procede et systeme de gestion de memoires vfc

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0465732A1 (fr) * 1990-07-11 1992-01-15 Koninklijke Philips Electronics N.V. Appareil pour la dérivation d'un signal de télévision entrelacé à basse définition et des autres constituants d'un signal de télévision à haute définition et appareil pour la reconstruction du signal original
US5528381A (en) * 1992-06-02 1996-06-18 Producers Color Service, Inc. System apparatus and method for identifying video frames suitable for freeze-frame viewing
EP0805430A1 (fr) * 1996-04-26 1997-11-05 Matsushita Electric Industrial Co., Ltd. Adaptateur vidéo et appareil d'affichage d'image numérique
WO1998041011A1 (fr) * 1997-03-12 1998-09-17 Matsushita Electric Industrial Co., Ltd. Systeme de transposition, par abaissement de frequence, des signaux de television a haute definition (t.v.h.d.)

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0465732A1 (fr) * 1990-07-11 1992-01-15 Koninklijke Philips Electronics N.V. Appareil pour la dérivation d'un signal de télévision entrelacé à basse définition et des autres constituants d'un signal de télévision à haute définition et appareil pour la reconstruction du signal original
US5528381A (en) * 1992-06-02 1996-06-18 Producers Color Service, Inc. System apparatus and method for identifying video frames suitable for freeze-frame viewing
EP0805430A1 (fr) * 1996-04-26 1997-11-05 Matsushita Electric Industrial Co., Ltd. Adaptateur vidéo et appareil d'affichage d'image numérique
WO1998041011A1 (fr) * 1997-03-12 1998-09-17 Matsushita Electric Industrial Co., Ltd. Systeme de transposition, par abaissement de frequence, des signaux de television a haute definition (t.v.h.d.)

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AU7847200A (en) 2001-04-23
WO2001028243A1 (fr) 2001-04-19
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AU7747200A (en) 2001-04-23
WO2001028244A1 (fr) 2001-04-19
WO2001028245A1 (fr) 2001-04-19

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