WO2001020947A1 - Procede pour minimiser le nombre de memoires de cellules atm - Google Patents

Procede pour minimiser le nombre de memoires de cellules atm Download PDF

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Publication number
WO2001020947A1
WO2001020947A1 PCT/DE2000/002441 DE0002441W WO0120947A1 WO 2001020947 A1 WO2001020947 A1 WO 2001020947A1 DE 0002441 W DE0002441 W DE 0002441W WO 0120947 A1 WO0120947 A1 WO 0120947A1
Authority
WO
WIPO (PCT)
Prior art keywords
fifo
channel
memories
atm
memory
Prior art date
Application number
PCT/DE2000/002441
Other languages
German (de)
English (en)
Inventor
Athanase Mariggis
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to CA002385019A priority Critical patent/CA2385019A1/fr
Priority to EP00958174A priority patent/EP1212920A1/fr
Publication of WO2001020947A1 publication Critical patent/WO2001020947A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H04J3/1617—Synchronous digital hierarchy [SDH] or SONET carrying packets or ATM cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Definitions

  • the invention relates to a method according to the preamble of claim 1.
  • State-of-the-art transmission methods are generally divided into m transmission methods that transmit information according to a synchronous transfer mode (STM) or asynchronous transfer mode (ATM).
  • STM synchronous transfer mode
  • ATM asynchronous transfer mode
  • the synchronous transfer mode STM is based on the transmission of information using SDH transmission technology (synchronous digital hierarchy).
  • the information is transmitted in transmission frames. These are divided into a control field (SOH, section overhead; POH, path overhead) and a container field.
  • SOH section overhead
  • POH path overhead
  • control information relating to the connection is transmitted, while the latter stores user data (payload).
  • ATM cells such as, for. B. m systems ATM over SDH can be used. At the beginning of the transmission process, these must then be arranged in the frame structure (downstream direction) and removed again on the receiving side (upstream direction).
  • Control information includes, for example, information relating to the security of the transmission, bit errors, line failure, clock accuracy, etc.
  • the control panel has two sub-areas SOH and POH.
  • the sub-area denoted by SOH has control information relating to a transmission section (for example between two switching devices), while in the sub-area designated by POH, control information is transmitted (end-to-end) between two subscribers.
  • STM-1 interfaces are used.
  • a STM-1 interface is phy ⁇ represents sikalisch lunsemcardien by a connection between two SDH intermediary.
  • the STM-1 interface is the basis of SDH transmission. For this reason, the m of SDH Vargsem ⁇ chtung arranged SDH LAD pelfelder the prior art currently on the circuit through ⁇ of STM-1 signals designed.
  • STM-N (N> 1) signals should be switchable. Since this is not currently the case, there are connection problems with the SDH coupling fields used up to now.
  • a method known in the prior art for circumventing these problems is virtual concatenated mode. This is a standardized method with which, for example, an STM-4 data stream is split into 4 STM-1 data streams. During the transmission, 4 STM-1 data streams are fed to the receiving switch, switched through and then combined again to form an STM-4 data stream. For this purpose, however, the STM-1 data streams transmitted in m channels must have a common reference size so that a later composition can take place again.
  • the standard interface for the transfer of ATM cells in non-concatenated mode is the Utopia Level 2 interface.
  • ATM cells are received from this interface and written into channel-specific memories in accordance with the assigned channel number.
  • the m is the channel-specific memory stored ATM cells are now gen jury hereinafter entge of a frame means ⁇ and m is an SDH Rah inserted en Design.
  • the A TM cells are thus at a predetermined Geschwmdig- k eit m channel-specific memory is written and this with a deviating speed again entnom ⁇ men.
  • FIFO cell memories are provided per channel-specific memory, care is taken to ensure that one of the 4 FIFO Cell memory per channel-specific memory is full.
  • the S TM-4 interface then works under full load.
  • the 4 FIFO cell memories per channel-specific memory center out the pauses between the different frequencies during the write and read process.
  • the invention has for its object to show a way how the number of cell memories can be reduced for non-concatenated mode.
  • An advantage of the invention is in particular that the spatial arrangement of the prior art FIFO cell memories is converted, so to speak, into a temporal arrangement. This means that here too the definition of the Utopia Level 2 interface is taken into account by ensuring that if the reading device accesses an ATM cell memory, an ATM cell is always stored in it and thus no empty cells are inserted into the SDH transmission frame have to. This is achieved in that the ATM cells stored in the ATM cell memory are taken from them in a time-interleaved readout process.
  • Figure 1 shows the arrangement of the inventive circuit arrangement in a communication system
  • Figure 2 shows the circuit arrangement erf dungsgewille
  • FIG. 1 shows the arrangement of the circuit arrangement according to the invention in a communication system KS.
  • a switching network SN is disclosed as a central component of the communication system KS, which is useful for switching the ATM cells.
  • ATM porting devices P and devices SDH are shown, between which the Utopia Level 2 interface is arranged. This is also part of both facilities.
  • the circuit arrangement according to the invention is now integrated in the device SDH.
  • frame devices (not shown here in greater detail) are to be considered, which integrate the ATM cells in the SDH transmission frame.
  • the circuit arrangement according to the invention is located in the downstream direction.
  • channel-specific memories are SPO. ..SP3 discloses, each having 2 FIFO cell memories FIFO yy , FIFOv-.
  • a FIFO cell memory can accommodate exactly one ATM cell.
  • 2 FIFO cell memories are required insofar as write / read processes cannot be carried out simultaneously in an ATM cell memory.
  • an ATM cell is removed from one of the ATM cell memories, an additional ATM cell can be written into the remaining ATM cell memory.
  • Gem ä ß Fig. 2 thus shows the channel-specific memory cells SPO, the two FIFO memories FIFOoi, FIFO 02, the channel-specific memory SP1, the two FIFO memory cells FIFO ⁇ ⁇ , etc. FIFO_ on.
  • the channel-specific memory SPO .. ..SP3 m are operatively connected to the Utopia Level 2 interface ⁇ imagine. From this, the ATM cells from the ATM port P ent ⁇ be taken up and in accordance with the channel ChO ... Ch3 m eme of the two FIFO memory cells FIFO xy, xz FIFO memory of the channel-specific relevant SP0 ... SP3 enrolled.
  • the channel-specific memory SPO is thus assigned to the channel ChO
  • the channel-specific memory SP1 etc. is assigned to the channel Ch1.
  • the Utopia Level 2 interface must ensure at all times that the ATM cell memories are filled with ATM cells. The reason for this is that otherwise the framer device integrates empty cells m into the SDH frame.
  • the ATM cells are written into the channel-specific memories at a speed specified by the Utopia Level 2 interface.
  • FIG. 2 shows a frame framer FR.
  • the ATM cells of one of the two FIFO cell memories FIFOy, FIFO z of the relevant channel-specific memory SP0..SP3 are removed and integrated into the SDH transmission frame.
  • the readout processes are supported by a read counter RC which controls the chronological sequence of the readout processes via devices RC0 ... RC3.
  • the ATM cells are removed from the relevant channel-specific memories SP0 ... SP3 again at a speed that differs from the write-in speed, which is specified by the frame device FR.
  • the Utopia Level 2 interface In order to strive for the most efficient transmission possible, the Utopia Level 2 interface must fill the channel-specific memories SP0 ... SP3 with ATM cells or the frame device FR in return read the ATM cells in such a way that the duration of the ATM cells m the FIFO cell memory Before FIFO xy , FIFO xz is as low as possible. For this, the S c h rei b / read operations are mutually agree in a corresponding manner from ⁇ .
  • the write / -Lesevorgang starts this starting transition state from an off ⁇ .
  • all FIFO cell memories FIFO xy , FIFO xz should be filled with ATM cells.
  • the Utopia Level 2 interface therefore does not write any ATM cells into the channel-specific memories SP0 ... SP3.
  • An ATM cell is first read byte by byte from the framer device FR from the ATM cell memory FIFOoi of the channel-specific memory SPO.
  • the decisive factor here is the counter reading of the RCO counter. This results from the application of an offset to the counter RC. In the present case, this is 0 bytes.
  • the count of the counting device RC1 now specifies when the ATM cell stored in the ATM cell memory FIFOn of the channel-specific memory SP1 is to be read out.
  • the counter reading is obtained by applying a further offset to the RC counter. In the present case, this is 13 bytes. This means that the readout of the ATM cell stored in the cell memory FIFOn is only started when 13 bytes of the ATM cell of the ATM cell memory FIFO OI have been read out.
  • the offsets of the counters RC2 and RC3 are 26 and 39 bytes. Reading out takes place cyclically. During the readout process, further ATM cells can be written into the ATM cell memory by the Utopia Level 2 interface. The criterion for this, however, is that the ATM cell memory in question is empty.
  • This method does not empty 4 cell memories at the same time as in the prior art, but rather the cell memories empty sequentially (see FIG. 3). As a result, only 2 ATM cell memories are required per channel-specific memory.
  • the relationships downstream of the channel-specific memories SP0 ... SP3 are on the data lines Data_Ch0. ..Data_Ch3 shown.
  • the ATM cells are indicated by header H and payload P. The timing of the transmission is clearly visible here.
  • the minimization of the ATM cell memory was addressed.
  • the invention is not limited to ATM cells and ATM cell memories. Rather, packets of a general type, such as, for example, IP packets, can also be extracted from packet memories using the method according to the invention. As a consequence, the packet memories m can be minimized in the same way as the ATM cell memories of the exemplary embodiment.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Dans l'état de la technique, en mode sans concaténation, par exemple pour l'interface STM-4, des cellules ATM sont, en tant que flux de données SM-1, converties en signaux STM-4, par l'intermédiaire de l'interface de niveau d'utopie 2. A cet effet, quatre mémoires de cellules ATM sont nécessaires pour chaque canal, en raison des exigences de cette interface. Pour que ce nombre puisse être réduit, les cellules ATM sont, avec un décalage temporel, retirées des mémoires de cellules ATM. On peut ainsi diminuer de moitié le nombre des cellules de mémoires ATM, cela sans que l'on ait à subir des limitations dans le processus de transmission.
PCT/DE2000/002441 1999-09-16 2000-07-25 Procede pour minimiser le nombre de memoires de cellules atm WO2001020947A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA002385019A CA2385019A1 (fr) 1999-09-16 2000-07-25 Procede pour minimiser le nombre de memoires de cellules atm
EP00958174A EP1212920A1 (fr) 1999-09-16 2000-07-25 Procede pour minimiser le nombre de memoires de cellules atm

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19944490.0 1999-09-16
DE19944490 1999-09-16

Publications (1)

Publication Number Publication Date
WO2001020947A1 true WO2001020947A1 (fr) 2001-03-22

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PCT/DE2000/002441 WO2001020947A1 (fr) 1999-09-16 2000-07-25 Procede pour minimiser le nombre de memoires de cellules atm

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EP (1) EP1212920A1 (fr)
CA (1) CA2385019A1 (fr)
WO (1) WO2001020947A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1227609A2 (fr) * 2001-01-26 2002-07-31 Fujitsu Limited Procédé et dispositif de multiplexage de données
EP1315397A2 (fr) * 2001-11-21 2003-05-28 Alcatel Canada Inc. Bus haute vitesse à multiples canaux avec sequencement
EP1424871A2 (fr) * 2002-11-27 2004-06-02 Alcatel Canada Inc. Procédé et appareil pour la transmission de données à dèbit binaire élevée sur un médian ou fond de panier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5941952A (en) * 1996-09-12 1999-08-24 Cabletron Systems, Inc. Apparatus and method for transferring data from a transmit buffer memory at a particular rate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5941952A (en) * 1996-09-12 1999-08-24 Cabletron Systems, Inc. Apparatus and method for transferring data from a transmit buffer memory at a particular rate

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
SEZER S ET AL: "BUFFER ARCHITECTURES FOR PREDICTABLE QUALITY OF SERVICE AT THE ATM LAYER", IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE,US,NEW YORK, NY: IEEE, 1998, pages 1242 - 1248, XP000825940, ISBN: 0-7803-4985-7 *
ZHOU P ET AL: "DESIGN OF PER-VC QUEUEING ATM SWITCHES", ATLANTA, GA, JUNE 7 - 11, 1998,NEW YORK, NY: IEEE,US, vol. CONF. 5, 7 June 1998 (1998-06-07), pages 304 - 308, XP000898720, ISBN: 0-7803-4789-7 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1227609A2 (fr) * 2001-01-26 2002-07-31 Fujitsu Limited Procédé et dispositif de multiplexage de données
EP1227609A3 (fr) * 2001-01-26 2005-09-28 Fujitsu Limited Procédé et dispositif de multiplexage de données
EP1315397A2 (fr) * 2001-11-21 2003-05-28 Alcatel Canada Inc. Bus haute vitesse à multiples canaux avec sequencement
EP1315397A3 (fr) * 2001-11-21 2004-01-14 Alcatel Canada Inc. Bus haute vitesse à multiples canaux avec sequencement
US7286570B2 (en) 2001-11-21 2007-10-23 Alcatel-Lucent Canada Inc High speed sequenced multi-channel bus
EP1424871A2 (fr) * 2002-11-27 2004-06-02 Alcatel Canada Inc. Procédé et appareil pour la transmission de données à dèbit binaire élevée sur un médian ou fond de panier
EP1424871A3 (fr) * 2002-11-27 2006-06-14 Alcatel Canada Inc. Procédé et appareil pour la transmission de données à dèbit binaire élevée sur un médian ou fond de panier
US7327725B2 (en) 2002-11-27 2008-02-05 Alcatel Canada Inc. Method and apparatus capable of transferring very high data rates across a midplane or backplane

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Publication number Publication date
CA2385019A1 (fr) 2001-03-22
EP1212920A1 (fr) 2002-06-12

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