WO2001018809A1 - Dispositif de traitement de signaux reproduits - Google Patents

Dispositif de traitement de signaux reproduits Download PDF

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Publication number
WO2001018809A1
WO2001018809A1 PCT/JP2000/006121 JP0006121W WO0118809A1 WO 2001018809 A1 WO2001018809 A1 WO 2001018809A1 JP 0006121 W JP0006121 W JP 0006121W WO 0118809 A1 WO0118809 A1 WO 0118809A1
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WO
WIPO (PCT)
Prior art keywords
clock
equalization
processing device
reproduction signal
digital
Prior art date
Application number
PCT/JP2000/006121
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English (en)
Japanese (ja)
Inventor
Shinichirou Satoh
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Publication of WO2001018809A1 publication Critical patent/WO2001018809A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/02—Analogue recording or reproducing
    • G11B20/04—Direct recording or reproducing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals

Definitions

  • the present invention relates to a reproduction signal processing device, and more particularly to a reproduction signal processing device that converts an analog reproduction signal into a digital reproduction signal and performs automatic equalization processing.
  • FIG. 7 is a block diagram showing a configuration of a conventional reproduced signal processing device in a digital information recording / reproducing device.
  • the playback signal processing device shown in FIG. 7 includes an analog Z digital converter (A / D converter) 1, a digital phase locked loop (digital PLL) 2, and an automatic equalizer 9. Prepare.
  • the automatic equalizer 9 further includes a transversal filter 4 and a control unit 5.
  • the analog digital converter 1 samples the analog reproduction signal input to the reproduction signal processing device into a multivalued digital reproduction signal.
  • the digital phase synchronization circuit 2 generates a reference clock CK that matches the phase and the reference frequency component included in the digital reproduction signal.
  • the transversal filter 4 performs waveform equalization processing of the digital reproduction signal.
  • the control unit 5 includes an equalization error which is an error between an output equalized waveform of the transversal filter 4 and an equalization target value estimated from the equalized waveform, and an input digital reproduction of the transversal filter 4. Using a signal, a transversal filter 4 is used to minimize the equalization error.
  • the tap coefficient which is a parameter of, is controlled.
  • the digital information recorded on the recording medium is read out by scanning a head (not shown), and an analog reproduced signal obtained by subjecting the read signal to a process for emphasizing a predetermined frequency band is supplied to the analog Z digital converter 1.
  • an analog reproduced signal obtained by subjecting the read signal to a process for emphasizing a predetermined frequency band is supplied to the analog Z digital converter 1.
  • the digital reproduction signal is input to the digital phase locked loop 2 and the transversal filter 4 of the automatic equalizer 9.
  • the digital phase-locked loop 2 extracts the reference clock CK from the input digital reproduction signal, and converts the reference clock CK into an analog / digital converter 1 and an automatic equalizer 9. To enter.
  • the reference clock CK is used as an operation clock in the analog Z digital converter 1 and the automatic equalizer 9.
  • the digital reproduction signal input to the transversal filter 4 is sent to the decoding circuit after the equalization processing in the transversal filter 4.
  • the transversal filter 4 is controlled by a tap coefficient, which is a parameter.
  • the tap coefficient is an equalization target value estimated based on the input digital reproduction signal to the transversal filter 4 and the output signal of the transversal filter 4 in the control unit 5 and the output signal. It is set at any time according to the equalization error of the error.
  • the control unit 5 uses an LMS algorithm that sequentially calculates the root mean square of the equalization target value based on the steepest descent method so as to minimize it.
  • the equalization target value sets the frequency characteristics of an equalizer (FIR filter) when performing digital equalization, and is usually set in consideration of the frequency characteristics of an input signal.
  • FIG. 8 (a) shows the operation clock of analog / digital converter 1 using the reference clock included in the digital playback waveform.
  • FIG. 4 is a diagram showing an example of a digital reproduction waveform when the sampling is performed.
  • the sequence of numbers 1 or 0 shown at the top of the waveform shown in FIG. 8 (a) is an example of a recording code that is a code recorded on a recording medium, and the sample points below the recording code are , Is the sample point corresponding to the recording code.
  • the processing is performed in the following procedure.
  • the data input to the control unit 5 and the data input one sampling ago are added to make it easier to distinguish between the force on the positive side and the force on the negative side based on zero (1 + D processing).
  • the sampling data after this process is shown in Fig. 8 (b).
  • the upper part of the waveform in FIG. 8 (b) shows an example of the result of the positive / negative judgment when the judgment is made so that the positive is 1 and the negative is 0.
  • whether the sign is positive or negative is determined by referring to the most significant bit of the waveform data that has been subjected to 1 + D processing. It should be noted here that the recording code shown in FIG. 8 (a) matches the arrangement of the data of 1 and 0 of the positive / negative judgment result shown in FIG. 8 (b).
  • the equalization target value can be reliably set. This is because the fact that the recording code matches the positive / negative judgment result means that by sequentially following the data sequence of 1 and 0, it is possible to know in advance how many cycles the waveform will have next. Because.
  • Japanese Patent Application Laid-Open No. 62-27424 discloses the setting of a filter coefficient vector of a transversal filter in a waveform equalizer using an adaptive transversal filter.
  • Japanese Patent Laid-Open Publication No. 3-10971 discloses an automatic equalizer capable of automatically controlling characteristic parameters.
  • the reference clock CK of the digital reproduction signal extracted by the digital phase synchronization circuit 2 is used as the operation clock, and the analog clock is used as the operation clock. Since the digital data is supplied to the digital converter 1 and the automatic equalizer 9 to reproduce the digital data, the analog / digital converter 1 and the automatic equalizer 9 reproduce the digital data. During this time, it always works. In other words, the transversal filter 4, which is a component of the automatic equalizer 9, and the control unit 5, which controls the parameters of the transversal filter 4, also always consume power. Moreover, since the ratio of the automatic equalizer 9 in the reproduction signal processing device is slightly more than 20%, the power consumption is not negligible.
  • High power consumption means that the temperature of the chip tends to rise when integrated in LSI or the like. If the SI is a mixed analog / digital chip, as the temperature of the chip rises, the characteristics of the analog elements and other components built into the chip will no longer meet the specifications. That is, in order to sufficiently bring out the total performance of the chip, not only the automatic equalizer 9 but also the power consumption of the entire LSI is desired to be reduced.
  • the frequency of the operation clock supplied to the automatic equalizer 9 and the analog / digital converter 1 May be reduced.
  • the operation clock a divide-by-2 clock having a cycle twice as long as the reference clock CK of the digital reproduction signal extracted by the digital phase synchronization circuit 2 is used.
  • the operation clock is divided by 2
  • the power consumption can be reduced to about half. Accordingly, if the analog Z digital converter 1 is supplied with a divided clock and operated, the number of samples becomes half that of the case where the reference clock CK is supplied.
  • the equalization target value is the data of the data when the digital converter 1 is sampled by the reference clock included in the digital reproduction signal. This is because they are generated using continuity.
  • the number of samples is reduced by half, the continuity of data is impaired, and it is difficult to set a stable and faithful equalization target value, and there is a problem that stable equalization processing cannot be performed.
  • the present invention has been made to solve the above-described problems, and has been made to reduce the power consumption without deteriorating the equalization performance, and to provide a reproduction signal processing apparatus having an automatic equalizer capable of high-speed reproduction.
  • the purpose is to provide equipment.
  • a reproduction signal processing apparatus comprising: an analog / digital converter that samples an analog signal and converts the analog signal into a digital signal; An automatic equalizer that performs equalization processing, a phase locked loop circuit that generates a reference clock that matches a phase and a reference frequency component included in the digital signal, and an integral multiple of the period of the reference clock. And a frequency divider for generating the divided clock as an operation clock and outputting the divided clock to the analog / digital converter and the automatic equalizer.
  • the automatic equalizer is configured to perform a waveform equalization process on the digital signal with a transversal noise detector and a transversal noise generator with an output.
  • the division clock A linear interpolation processing unit for interpolating the lack of the number of samples due to the sampling using, and an equalization target value is estimated based on an output of the linear interpolation processing unit, and the equalization target value and the transversal filter are estimated. And a control unit for controlling the parameters of the transversal filter so that an equalization error, which is an error with the output, is minimized.
  • a divided clock is used in place of the reference clock. This can compensate for the lack of sample points due to this, and has the effect of reducing power consumption and supporting high-speed playback while maintaining equalization performance equivalent to using the reference clock. .
  • the reproduction signal processing device is the reproduction signal processing device according to claim 1, wherein the linear interpolation processing unit is divided into an output equalized signal of the transversal filter.
  • the flip-flop element is configured to perform a delay process for one cycle of a cycle, and an adder that adds the signal after the delay process and the output equalized signal.
  • the present invention it is possible to compensate for the lack of sample points due to the use of the divided clock in place of the reference clock, which is equivalent to the case where the reference clock is used.
  • the effect is that the power consumption can be reduced and high-speed playback can be supported while maintaining the high performance.
  • the reproduction signal processing device is the reproduction signal processing device according to claim 1, wherein the linear interpolation processing unit is replaced with an output of the transversal filter.
  • the present invention it is possible to compensate for the lack of sample points due to the use of the frequency dividing clock instead of the reference clock, which is equivalent to the case where the reference clock is used.
  • the effect of reducing power consumption and supporting high-speed playback while maintaining equalization performance is obtained.
  • the reproduction signal processing device is the reproduction signal processing device according to claim 3, wherein the high-order interpolation processing unit is provided for one cycle of a frequency division clock.
  • a flip-flop element for performing delay processing and a coefficient for weighting a tap coefficient to the signal after the delay processing , And an adder for adding output signals of the plurality of multipliers.
  • the present invention it is possible to compensate for the lack of sample points due to the use of the frequency-divided clock instead of the reference clock, which is equivalent to the case where the reference clock is used.
  • the effect is that the power consumption can be reduced and high-speed playback can be supported while maintaining the high performance.
  • FIG. 1 is a block diagram showing a configuration of a reproduction signal processing device according to Embodiment 1 of the present invention.
  • FIG. 2 (a) is a diagram showing an example of an input digital reproduction signal of the automatic equalizer using the frequency division clock according to the first embodiment of the present invention.
  • FIG. 2 (b) is a diagram showing an example of an output equalized waveform of the automatic equalizer using the frequency division clock according to the first embodiment of the present invention.
  • FIG. 2 (c) is a diagram showing an example of an output equalized waveform of the automatic equalizer using the reference clock.
  • FIG. 3 (a) is a diagram showing an example of an output equalized waveform of the automatic equalizer using the frequency division clock according to the first embodiment of the present invention.
  • FIG. 3 (b) is a diagram showing an example of a result of performing the 10D processing according to the first embodiment of the present invention.
  • FIG. 3 (c) is a diagram showing an example of the interpolated waveform restored using the waveform data subjected to timing adjustment according to the first embodiment of the present invention.
  • FIG. 4 is a block diagram showing a configuration of a reproduced signal processing device according to Embodiment 2 of the present invention.
  • FIG. 5 is a diagram showing an example of a higher-order interpolation processing unit according to Embodiment 2 of the present invention.
  • FIG. 6 is a diagram showing an example of Nyquist interpolation, which is an example of higher-order interpolation processing according to Embodiment 2 of the present invention.
  • FIG. 7 is a block diagram showing a configuration of a conventional reproduction signal processing device.
  • FIG. 8 (a) is a diagram showing an example of an output waveform of an analog Z digital converter in a conventional reproduction signal processing device.
  • FIG. 8 (b) is a diagram showing an example of a result obtained by performing 1 + D processing on an output waveform of an analog Z digital converter in a conventional reproduction signal processing device.
  • FIG. 8 (c) is a diagram showing an example of an output waveform obtained as a result of setting an equalization target value in a conventional reproduction signal processing device and performing equalization.
  • FIG. 1 is a block diagram showing a configuration of a reproduced signal processing device according to the first embodiment.
  • the reproduction signal processing device shown in FIG. 1 includes an analog / digital converter 1, a digital phase synchronization circuit 2, a frequency divider 3, and an automatic equalizer 8.
  • the automatic equalizer 8 further includes a transversal filter 4, a control unit 5, and a linear interpolation processing unit 6.
  • the same reference numerals as those in FIG. 7 denote the same components as those in the conventional reproduction signal processing device, and a description thereof will be omitted.
  • the frequency divider 3 performs a frequency division process on the reference clock CK extracted by the digital phase-locked loop 2 to multiply the period of the reference clock CK by an integer.
  • the linear interpolation processing section 6 includes a flip-flop element and an adder (not shown), and performs sampling in the analog Z digital converter 1 in place of the reference clock CK. Lock using CKZN Interpolation is performed to compensate for the lack of the number of samples.
  • the digital information recorded on the recording medium is read out by scanning a head (not shown), and the read-out signal is processed to emphasize a predetermined frequency band.
  • the digital reproduction signal is input to the digital phase locked loop 2 and the transversal filter 4 of the automatic equalizer 8.
  • the digital phase synchronization circuit 2 extracts a reference clock CK from the input digital reproduction signal, and inputs the reference clock CK to the frequency divider 3.
  • the frequency divider 3 performs a frequency division process for multiplying the period of the reference clock CK by an integer, and outputs a frequency division clock CKZN.
  • the frequency division clock CKZN is used as an operation clock in the analog / digital converter 1 and the automatic equalizer 8.
  • N represents the frequency division ratio
  • the digital reproduction signal input to the transversal filter 4 is sent to the decoding circuit after the equalization processing in the transversal filter 4.
  • the transversal filter 4 is controlled by a tap coefficient which is a lamella.
  • the tap coefficient is converted into a digital reproduction signal input through the transversal filter 4 in the control unit 5 and an equalization error which is an error between an output signal of the transversal filter 4 and an equalization target value. It is set at any time.
  • control unit 5 uses an LMS algorithm that sequentially calculates so that the root mean square of the equalization target value is minimized based on the steepest descent method.
  • the output equalized waveform of the transversal finolector 4 has a higher frequency than the case where the reference clock CK is used because the divided clock CKZN is used as the operation clock. The number of samples is decreasing.
  • the output equalization waveform of the transversal filter 4 is input to the control unit 5 and the linear interpolation processing unit 6 By Interpolation processing is performed on the output equalized waveform, and a signal obtained by interpolating a missing sample by using the frequency-divided clock CKZN is also input to the control unit 5 to use the reference clock CK.
  • the target for the equalization can be set stably as in the case where
  • FIGS. 2 (a) to 2 (c) and 3 (a) to 3 (c) the digital reproduction signal, the equalized waveform, and the equalized waveform were subjected to linear interpolation.
  • 4 shows an example of a waveform.
  • FIG. 2 (a) is a diagram showing an example of a digital reproduction signal, and ⁇ indicates the analog reproduction signal in the analog Z digital converter 1.
  • FIG. 2 (b) is a diagram showing an equalized waveform obtained by equalizing the digital reproduction signal of FIG. 2 (a) by a trans-sulfur filter 4, and ⁇ indicates a sample after waveform equalization processing. Indicates a point.
  • FIG. 2 (c) is a diagram showing an equalized waveform (ideal waveform) when the reference clock is used, and ⁇ indicates the reference clock in the analog Z digital converter 1. Shown below are the sample points when used as a working clip. The solid lines connecting the sample points in Figs. 2 (a) to 2 (c) are added to make it easier to recognize the waveform.
  • FIG. 2 (b) shows that when the divide-by-2 clock is used instead of the reference clock, the output from the analog / digital converter 1 is obtained. It can be seen that the number of samples of the reproduced digital signal decreases as the division ratio increases.
  • the linear interpolation processing performed by the linear interpolation processing unit 6 compensates for the lack of the number of samples due to the use of the frequency division clock.
  • Figs. 3 (a) to 3 (c) show examples of linear interpolation processing on an equalized waveform sampled using the divide-by-2 clock and subjected to equalization processing. is there.
  • Fig. 3 (a) the analog Z digital In the digital converter 1, the point at which the digital reproduction signal is sampled by the divide-by-2 clock is shown, and the symbol ⁇ indicates the point that should be sampled when the reference clock is used. That is, when the reference clock is the operation clock of the analog-to-digital converter 1, both ⁇ and ⁇ are sampled. Note that books and ⁇ may be reversed depending on the timing when sampling is started. Of these, interpolation processing is to restore ⁇ in a pseudo manner using only the ginseng. First, in FIG.
  • 1 + D processing means that one sample point subjected to equalization processing is delayed by one cycle of the operating clock by a flip-flop element, and This is the process in which the sample points subjected to the conversion process are added by an adder. Specifically, for a given sample point, the difference from the reference sample point (in FIG. 3 (a), the leftmost sample point is used as the reference) is calculated as the next sample point, In other words, it is the operation of adding to the sample points delayed by one period of the divide-by-2 clock.
  • the waveform shown in FIG. 3 (c) was obtained by performing timing adjustment processing on the symbol shown in FIG.
  • FIGS. 3 (a) and 3 (c) the symbol ⁇ shown in FIG. 3 (b). It is a waveform after the interpolation processing.
  • FIGS. 3 (a) to 3 (c) the sample points connected by solid lines or broken lines are added to make it easier to recognize the waveform.
  • FIG. 3 (c) the symbol indicates the data actually sampled by the dividing clock, and ⁇ indicates the linear interpolation, that is, the current value of the transversal filter 4 input to the control unit 5.
  • FIG. 3 (c) showing the interpolated sampling data is subjected to 1 + D processing to obtain successive three and By performing a positive / negative determination of each sampling on the result of the 1 + D processing performed on the two, processing equivalent to FIG. 8 (b) is performed.
  • the addition result uses only the most significant bit of the adder. By adding only the most significant bits of the output results of these adders, the result can be divided into five levels from 0 to 4 as described in the conventional technology.
  • the equalization target value can be set as in the case of using.
  • the operation clock used in the analog Z digital converter 1 and the automatic equalizer 8 is a frequency dividing clock.
  • power consumption can be reduced, and the processing interval between components can be longer than when a reference clock is used. Therefore, an increase in circuit scale can be suppressed.
  • the automatic equalizer 8 with the linear interpolation processing unit 6, it is possible to compensate for the lack of sample points due to the use of the frequency dividing clock instead of the reference clock. It is possible to stably set the equalization target value in the part 5, and it is possible to maintain the equalization processing capacity equivalent to the case where the reference clock is used.
  • the division ratio can be increased within the range where interpolation can be performed to the same extent as when sampling with the reference clock. For example, if the frequency division ratio is such that the frequency of the frequency division clock exceeds the minimum repetition frequency of the reproduced signal, the equalization cannot be performed stably.
  • FIG. 4 is a process diagram showing the configuration of the reproduction signal processing apparatus according to the second embodiment.
  • FIG. 4 The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
  • the high-order interpolation processing unit 7 shown in FIG. 4 is missing due to the use of the divided clock instead of the reference clock in the sampling in the analog / digital converter 1.
  • Higher-order interpolation processing such as Nyquist interpolation is performed to supplement the sample points.
  • the Nyquist interpolation processing includes a flip-flop element that performs delay processing for one cycle of the frequency division clock, a plurality of multipliers that weights the signal after the delay processing by Nyquist interpolation, And an adder for adding a plurality of multiplier output signals.
  • the linear interpolation processing in the first embodiment is processing for performing interpolation using a straight line
  • the higher-order interpolation processing in the second embodiment is a processing in which a higher-order This is the process of performing interpolation using.
  • the higher-order interpolation processing unit 7 has the same role as the linear interpolation processing unit 6 described in the first embodiment, that is, the division clock is used for the analog Z-digital converter 1 and the operation clock of the automatic equalizer 8. In the case where the number of samples is reduced by using the information as a reference, the function is to supply waveform data to the control unit 5 as if there was no loss of information.
  • FIG. 5 is a diagram showing an example of the higher-order interpolation processing section 7.
  • the high-order interpolation processing unit 7 may be, for example, an FIR filter including delay elements 10 a to 10 f, multipliers 11 a to llg, and an adder 12. .
  • C 1 to C 7 represent the weighting coefficients of the filter.
  • the Nyquist interpolation processing is performed and the frequency division coefficient is calculated. It can compensate for the lack of the number of samples due to using the lock as an operation clock.
  • the vertical axis in FIG. 6 is a weighting factor. For example, if a certain point is set as a filter weighting factor C 1, a point which is increased by 1 T with respect to the horizontal axis from that point is a weighting factor C 2 And more By setting the point increased by 1 T as the weighting factor C3, each of the weighting factors C1 to C7 can be determined.
  • the filter weight coefficient is set by a register or the like, and the weight can be changed by changing the register value.
  • the amplitude attenuation and the disk slope due to the deterioration of the read head characteristics are compared with the case where the linear interpolation processing unit 6 is used.
  • the ability to restore information for quality degradation of reproduced waveform data such as waveform distortion caused by (tilt) and the effect of noise superimposed on the reproduction system is greatly improved.
  • the reproduced signal processing device employs the high-order interpolation processing unit 7 to interpolate the lack of information due to the use of the frequency division clock.
  • the control unit 5 By supplying the interpolated waveform to the control unit 5, it is possible to set a stable and appropriate equalization target value, so that even when a divided clock is used, the reference clock is used. It is possible to achieve the same equalization performance as when using a hook.
  • the use of the high-order interpolation processing unit 7 reduces the amplitude attenuation due to the deterioration of the characteristics of the read head, the distortion of the waveform caused by the tilt of the disk, and the effects of noise superimposed in the playback system. For example, the capability of restoring information on quality degradation of reproduced waveform data such as the above can be improved.
  • the reproduction signal processing device converts an analog reproduction signal into a digital reproduction signal, and performs automatic equalization processing on the digital reproduction signal. It is suitable for automatic equalization processing on reproduced signals or automatic equalization processing with low power consumption.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

Cette invention se rapporte à un dispositif de traitement de signaux reproduits, qui est conçu pour uniformiser la reproduction haute vitesse et consommer moins d'énergie électrique pour l'opération d'égalisation, tout en ne compromettant pas la capacité d'égalisation. L'opération d'égalisation est effectuée à l'aide d'une horloge de division de fréquence pour l'horloge d'exploitation. Une unité d'interpolation linéaire (6) est prévue pour couvrir les informations manquantes, en raison de l'utilisation de l'horloge de division de fréquence.
PCT/JP2000/006121 1999-09-08 2000-09-08 Dispositif de traitement de signaux reproduits WO2001018809A1 (fr)

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JP11/254584 1999-09-08

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002330185A (ja) * 2000-05-09 2002-11-15 Matsushita Electric Ind Co Ltd 復調器
US7274645B2 (en) 2003-06-10 2007-09-25 Matsushita Electric Industrial Co., Ltd. Reproduction signal processing apparatus and optical disc player including the same
US7304918B2 (en) 2003-09-24 2007-12-04 Matsushita Electric Industrial Co., Ltd. Servo error signal generation circuit and servo error signal generation method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100813074B1 (ko) * 2001-10-25 2008-03-14 엘지전자 주식회사 광 기록매체 등화 장치
JP4121444B2 (ja) * 2003-10-31 2008-07-23 三洋電機株式会社 データ再生装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04245711A (ja) * 1991-01-30 1992-09-02 Nec Corp 適応型フィルタ

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04245711A (ja) * 1991-01-30 1992-09-02 Nec Corp 適応型フィルタ

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002330185A (ja) * 2000-05-09 2002-11-15 Matsushita Electric Ind Co Ltd 復調器
JP4581288B2 (ja) * 2000-05-09 2010-11-17 パナソニック株式会社 復調器
US7274645B2 (en) 2003-06-10 2007-09-25 Matsushita Electric Industrial Co., Ltd. Reproduction signal processing apparatus and optical disc player including the same
US7304918B2 (en) 2003-09-24 2007-12-04 Matsushita Electric Industrial Co., Ltd. Servo error signal generation circuit and servo error signal generation method

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CN1327588A (zh) 2001-12-19
KR100430184B1 (ko) 2004-05-03
CN1151507C (zh) 2004-05-26
KR20010086004A (ko) 2001-09-07

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