Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/10—Address translation
  • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
  • G06F13/4004—Coupling between buses
  • G06F13/4027—Coupling between buses using bus bridges
  • G06F13/404—Coupling between buses using bus bridges with address mapping

Definitions

• the invention relates generally to bus protocol bridging. More particularly, the invention relates to input/output (I O) address translation, such as remapping a continuous logical address space to a potentially discontinuous physical address space, in a bridge.
• I O input/output
• I/O peripheral devices typically operate more efficiently if they are presented with a large contiguous view of system memory (main memory). This allows such devices to make random accesses into a large area of memory containing the data in which they are interested.
• a contiguous view of memory is especially important for graphics cards which must often retrieve an entire texture map in order to render a scene on a display device.
• the address space in which the I/O peripheral device operates that gives the perception of a large contiguous address space is called a "virtual address space.”
• FIG. 1 is a high-level block diagram of a general purpose computer system 100 that illustrates translation of graphics addresses to physical addresses.
• the computer system 100 includes processing means, such as one or more processors 105 and 110, a chipset 120, a main memory 125, a memory bus 124, an Accelerated Graphics Port (AGP) bus 130, and a PCI bus 140.
• the main memory includes a graphics address relocation table (GART) which contains entries for mapping virtual addresses used by a peripheral device, such as graphics accelerator 135, to physical addresses in main memory 125.
• GART graphics address relocation table
• the chipset 120 provides bridging functions between the AGP bus 130, the PCI bus 140, and the memory bus 124. As part of the bridging function, the chipset 120 translates graphics addresses contained in inbound read and write transactions (e.g., read and write transactions originated by the graphics accelerator 135) to corresponding physical addresses in main memory 125 using the GART 126. Consequently, in a computer system configured in accordance with Figure 1, processing of graphics data, such as texture maps, requires multiple accesses to main memory 125. First, the chipset 120 must retrieve an entry from the GART 126 that corresponds to the graphics address specified in the transaction being executed. Then, after the desired physical address has been determined by the chipset 120, the chipset 120 must perform a second access to main memory 125 in order to read or write the data specified by the transaction.
• AGP AGP Advanced GP Advanced GP
• main memory 125 which is typically made up of dynamic random access memories (DRAMs)
• DRAMs dynamic random access memories
• SRAM static random access memory
• main memory 125 accesses for purposes of address translation must compete with other access requests, such as those originated by processor 105 or 110 and received over the system bus 1 15 or those received on the PCI bus 140.
• AGP translations are slowed down by competing traffic.
• the translation unit (not shown) handles multiple types of traffic, e.g., system bus traffic, PCI traffic, and AGP traffic, the situation is further complicated as arbitration logic becomes necessary to resolve contention for the translation unit among the various types of inbound and outbound transactions.
• the I/O expansion bridge includes a first interface unit, a second interface unit, and an address translation unit.
• the first interface unit is configured to be coupled to a system memory and I/O controller through one or more I/O ports.
• the first interface unit enables data transfers over the one or more I/O ports to or from the main memory of a computer system.
• the second interface unit provides bus control signals and addresses to enable data transfers over a bus to or from a peripheral device.
• the address translation unit is coupled to the first interface unit and the second interface unit.
• the address translation unit translates addresses associated with transactions received on the second interface by accessing a local memory containing physical addresses of pages in the main memory of the computer system.
• Figure 1 is a block diagram that illustrates a prior art approach for graphics address translation.
• Figure 2 is a block diagram that illustrates input/output address translation according to one embodiment of the present invention.
• Figure 3 is a block diagram that illustrates graphics address translation according to one embodiment of the present invention.
• FIG. 4 is a block diagram illustrating an exemplary chipset in which embodiments of the present invention may be implemented.
• Figure 5A is a simplified block diagram illustrating high-level interconnection among functional units of a graphics expansion bridge according to one embodiment of the present invention.
• Figure 5B is a simplified block diagram illustrating a more detailed view of a graphics expansion bridge according to one embodiment of the present invention.
• Figure 6 is a high-level flow diagram conceptually illustrating transaction processing according to one embodiment of the present invention.
• Figure 7 is a flow diagram illustrating inbound PCI write transaction processing according to one embodiment of the present invention.
• Figure 8 is a flow diagram illustrating outbound PCI write transaction processing according to one embodiment of the present invention.
• Figure 9 conceptually illustrates graphics (virtual) to physical address space translation according to one embodiment of the present invention.
• Figure 10A illustrates an exemplary virtual address format which may be employed to refer to data residing in 4Kbyte pages in main memory.
• Figure 10B illustrates an exemplary virtual address format which may be employed to refer to data residing in 4Mbyte pages in main memory.
• Figure 11A illustrates an exemplary GART entry format to support address translation to 4Kbyte pages in main memory.
• Figure 11B illustrates an exemplary GART entry format to support address translation to 4Mbyte pages in main memory.
• embodiments of the present invention seek to provide a technique for translating I/O addresses that speeds up the execution of I/O transactions by, among other things, insulating the I O translation device, e.g., an I/O expansion bridge, from other types of traffic, such as system bus transactions.
• the GART may be stored in a local SRAM rather than across the memory bus.
• the interface is local and accesses to fetch GART entries do not have to compete with other types of traffic, transactions can be completed faster and the implementation of the translation device can be simplified.
• the present invention includes various steps, which will be described below.
• the steps of the present invention may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general- purpose or special-purpose processor or logic circuits programmed with the instructions to perform the steps.
• the steps may be performed by a combination of hardware and software.
• bus generally refers to the physical communication medium or channel over which information flows between two or more devices. While a bus with only two devices on it is considered by some to be a "port,” as used herein, the term bus is intended to encompass such ports as well.
• processor bus typically refers to the highest-level bus in the hierarchy of buses of a computer system. This bus is typically used by a system chipset to send information to and from the one or more processors of the computer system.
• Memory bus refers to the bus that connects the memory subsystem to the system chipset and the processor(s). Importantly, in some computer systems, the processor bus and the memory bus may be the same bus.
• a "local I/O bus” is typically a high-speed input output (I O) bus used for connecting various types of peripheral devices to the memory, the system chipset and/or the processor(s) of the computer system. For example, video cards, disk storage devices, high-speed network interfaces, and other performance-critical peripherals are commonly coupled to a bus of this kind.
• Common local I/O buses include the VESA Local Bus (VLB), the Peripheral Component Interconnect (PCI) Bus, and the Accelerated Graphics Port (AGP) Bus.
• VLB VESA Local Bus
• PCI Peripheral Component Interconnect
• AGP Accelerated Graphics Port
• AGP Accelerated Graphics Port
• PCI transaction generally refers to a PCI transaction with AGP semantics that is issued on the AGP bus.
• a "bridge” generally refers to the logic and circuitry embodied in a chipset, for example, to connect two buses and allow the device(s) on one bus to communicate with the device(s) on the other and vice versa.
• a PCI-ISA bridge which is typically part of the system chipset.
• the PCI bus also may also have a bridge to the processor bus, called a PCI expansion bridge (PXB).
• PXB PCI expansion bridge
• a "transaction” comprises one or more of a request (address) phase and a data phase.
• a transaction typically includes a start address, a transaction type, and an indication of the amount of data to be transferred.
• an "inbound transaction” generally refers to a read or write request directed to the computer system by a peripheral device, such as a video card, disk storage device, or high-speed network interface; and an “outbound transaction” generally refers to a read or write request directed to a peripheral device by the computer system.
• FIG. 2 illustrates a general purpose computer system 200 in which one or more of the steps of a method according to one embodiment of the present invention may be performed and in which an apparatus according to one embodiment of the present invention may reside.
• the computer system 200 includes a processing means, such as one or more processors 205 and 210, a chipset 220, a main memory 225, a memory bus 224, and a local I/O bus 230.
• the chipset 220 includes an address translation table 226.
• the address translation table contains entries (not shown) which facilitate the translation of virtual addresses received from a peripheral device 235 to physical addresses in main memory 225.
• the chipset 220 may include one or more integrated circuits upon which various chipset functions, e.g., system bus arbitration, I/O address translation, etc., may be distributed.
• the chipset 220 acts as a bridge between the both the local I/O bus 230 and the system bus 215 and the memory bus 224.
• the chipset 220 accesses the local address translation table 226 to map the continuous I/O address space employed by the peripheral device 235 to the physical address space of the main memory 225.
• the address translation table 226 by locating the address translation table 226 local to the chipset 220 (e.g., in a dedicated on-chip or off-chip SRAM), inbound transactions from the peripheral device 235 may be more efficiently executed.
• FIG. 3 is a high-level block diagram illustrating a general purpose computer system 300 in which an improved virtual address translation technique according to one embodiment of the present invention may be implemented.
• the computer system 300 includes processing means, such as one or more processors 305 and 310, a chipset 320, a main memory 225, a memory bus 324, an Accelerated Graphics Port (AGP) bus 330, and a PCI bus 340.
• the chipset 320 includes a graphics address relocation table (GART) 326.
• the GART 326 contains GART entries (described below) which contain information for accomplishing the translation of virtual addresses received from a graphics accelerator 335 to physical addresses of the main memory 325.
• the GART 326 is locally accessible to the chipset 320 rather than being located across the memory bus 324 in main memory 325.
• the chipset 320 provides a bridging function between the AGP bus 330, the PCI bus 340, and the memory bus 324.
• the chipset 320 translates graphics addresses contained in inbound read and write transactions (e.g., read and write transactions originated by the graphics accelerator 335) to corresponding physical addresses in main memory 325 using the local GART 326.
• inbound read and write transactions e.g., read and write transactions originated by the graphics accelerator 335)
• inbound transactions from peripheral devices, such as the graphics accelerator 335 may be more efficiently processed and executed.
• a fetch from the local SRAM can be performed in approximately 30 nano seconds or less.
• FIG. 4 illustrates an exemplary allocation of functionality among a plurality of units (e.g., chips) according to one embodiment of the present invention.
• the chipset 320 includes a system address controller (SAC) 415, a system data controller (SDC) 420, a PCI expansion bridge (PXB) 425, graphics expansion bridge (GXB) 410, and static RAM (SRAM) 405.
• SAC system address controller
• SDC system data controller
• PXB PCI expansion bridge
• GXB graphics expansion bridge
• SRAM static RAM
• the SAC 420 connects to the address and control sections (not shown) of the system bus 315.
• the SAC is responsible for translating and directing system bus 315 accesses to the appropriate I/O port or main memory 325. It also acts as a routing agent for inbound traffic, directing it to a peer I/O port 412 or 427, main memory 325 or the system bus 315.
• the SDC connects to the data signals (not shown) on the system bus 315, and also to main memory 325 by way of the memory bus 324 and the SAC 420.
• the data for all transfers passes through the SDC, whether from the system bus 315 to main memory 325, from one of the I/O ports 412 or 427 to memory or peer to peer I/O port 412 or 427.
• the connection between the SAC 415 and SDC 420 allows for concurrent data transfers to the system bus 315 and to the I/O ports 412 or 427 thereby maximizing the available bandwidth to each system agent.
• the functionality of the SAC 420 and the SDC may be combined into a single system memory and I/O controller 421 or distributed over additional integrated circuits.
• the PXB 425 provides a bus protocol bridging function between the I/O port 427, such as an F16 bus, and the PCI bus 340.
• a single PXB 425 typically connects to one I/O port 427 and creates two 33Mhz, 32-bit PCI buses.
• the PXB 425 may support a single 64-bit PCI bus.
• a computer system may include multiple PXBs (typically 1 to 4).
• the GXB 410 creates a bridge between the I/O ports 412, e.g., two F16 buses, and the AGP bus 330 by providing a bus protocol bridging function between the I/O ports 412 and the AGP bus 330. In this manner, the GXB 410 adds a high performance, dedicated graphics port to the computer system. Multiple GXBs can be instantiated in a computer system to create a multi-graphics port workstation. The primary function of the GXB 410 is to create a bridge between the I/O ports 412 and the AGP bus 330.
• the GXB 410 does this by accepting outbound transactions from the I/O ports 412, storing them internally, and then delivering them on the AGP bus 330 using the appropriate signaling protocol. Conversely, the GXB 410 accepts inbound transactions issued on the AGP bus 330, again stores them internally, translates the graphics addresses associated with the inbound transactions, and issues the translated inbound transactions onto the I/O port(s) 412. As will be described in further detail below, the GXB 410 performs address translation by accessing the GART 326 stored in an on or off-chip SRAM 405. Several advantages are achieved by the chipset architecture of Figure 4.
• the GXB 410 is isolated from the system bus 315 and associated system traffic thereby eliminating a source of contention for the resources of the GXB 410 and doing away with the need for associated arbitration logic.
• address translation processing will not interfere with main memory traffic and the memory bus 324 is more efficiently utilized.
• the local SRAM accesses to the GART 326 are approximately ten times faster than if the GXB 410 had to go over the memory bus 324. Consequently, the end result is an improved protocol bridge for servicing transactions on the AGP bus 330.
• the improved protocol bridge is simpler, faster, and more efficient than the current bridging techniques described above. Exemplary internal partitionings of the GXB 410 will be described below.
• one or more of the GXB 410 components could be integrated onto a single integrated circuit (IC). Additionally, in alternative embodiments, one or more of the GXB 410 components could be integrated with a processor and/or memory onto a single integrated circuit.
• FIG. 5A is a simplified block diagram illustrating high-level interconnection among functional units of a graphics expansion bridge according to one embodiment of the present invention.
• GXB 410 includes an AGP bus interface unit 505, a data buffer unit 510, a transaction queue unit 515, a GART unit 520, and an I/O port interface unit 525.
• the AGP bus interface unit 505 may be based upon a 66Mhz, 32-bit PCI bus. In practice, to ease implementation, the AGP bus interface unit 505 may be further divided into the core PCI bus and the incremental logic that adds the AGP capabilities.
• the AGP bus interface unit 505 includes arbitration logic (not shown) for managing AGP bus 330 ownership between inbound and outbound transactions. Additionally, bus control signals and addresses are provided by the AGP bus interface unit 505 to enable AGP data transfers over the AGP bus 330. The AGP bus interface unit 505 may also maintain an internal transaction queue and data buffers (not shown) for performing any necessary intra stream reordering and for holding a transaction until adequate resources are available in the transaction queue unit 515 to service it.
• the transaction queue unit 515 implements one or more internal transaction queues for inbound and outbound transactions. Buffer space may also be implemented in the GXB 410 to support various data buffering needs.
• the data buffer unit 510 may contain data buffers for temporarily storing data within the GXB 410.
• the data buffers may be implemented as separate buffers for each transaction type in each direction or as a common buffer.
• the GART 126 is stored in main memory 125. Accordingly, in such implementations, GART functionality is performed proximate to main memory 125. In contrast, according to the present embodiment, GART functionality is performed within the GXB 410 by the GART unit 520. According to one embodiment, the GART unit implements a push model and translates transactions whenever a valid transaction resides in one of the transaction queue(s). In this regard, the GART unit 520 is responsible for accepting inbound transactions from the transaction queue(s) and translating the transactions as necessary. In the embodiment depicted, the GART unit 520 is coupled to a local off-chip SRAM 405 that includes the GART 326.
• the GART 326 may be stored in an on-chip SRAM.
• the GART unit 520 is also responsible for programming the contents of the SRAM 405.
• the SRAM 405 should be initialized as invalid or programmed before any accesses commence.
• the GART unit 520 can be directed to program the SRAM 405 dynamically every time a new application is started, for example. Programming may be achieved by issuing programming access requests from the system bus 315.
• the I/O port interface unit 525 provides the interface to one or more I/O ports by enabling requests and data transfers over the one or more I/O ports. For example, according to one embodiment, the I/O port interface unit 525 interfaces two F16 buses. The I/O port interface unit 525 removes transactions from the inbound transaction queue(s) maintained in the transaction queue unit 515 based upon availability and stream priority, and transmits the transactions across the appropriate I/O port 412. If the request is a write, then data is read from the appropriate buffer in the data buffer unit 510 is sent as well. For outbound transactions, an entry is added to the appropriate outbound transaction queue maintained in the transaction queue unit 515. If necessary, data associated with an outbound transaction is delivered to the appropriate buffer in the data buffer unit 510.
• FIG. 5B is a simplified block diagram illustrating a more detailed view of graphics expansion bridge 410 according to one embodiment of the present invention.
• the transaction queue unit 515 includes an AGP low priority queue 560, an AGP high priority queue 565, a PCI inbound queue 570, SAC inbound control logic 580, SAC outbound control logic 585, and a PCI outbound queue 590.
• the AGP bus interface unit 505 receives inbound AGP transactions from the AGP bus 330 and adds them to the appropriate queue 560, 565, or 570. For example, inbound PCI transactions from the AGP bus 330 are routed to the PCI inbound queue 570 by the AGP bus interface unit 505.
• the SAC outbound control logic 585 receives outbound transactions from the I O ports 412 and queues them onto the PCI outbound queue 590.
• the PCI outbound queue 590 in turn is unloaded by the AGP bus interface unit 505.
• the outbound transactions do not require address translation they do not need to go through the GART unit 520.
• the GART unit 520 includes an arbitration unit 530, an execution unit 535, and a writeback unit 540.
• the arbitration unit 530 performs two main functions: (1) arbitration among the AGP and PCI accesses and SRAM accesses (programming accesses) coming from the configuration control unit 595 and (2) generation of SRAM addresses (GART indices).
• the arbitration function of the arbitration unit 530 involves deciding which transaction of those at the head of the transaction queues 560, 565, and 570 will be translated next.
• the virtual addresses (which are 40 bits wide in one embodiment) associated with the inbound transactions in the transaction queues 560, 565, and 570 are too wide to be fed directly to the SRAM 405.
• the SRAM address generation function (GART index generation function) of the arbitration unit 530 determines an SRAM address based upon the virtual address of the transaction that won the arbitration.
• the arbitration unit 530 may then communicate to the execution unit 535 that it should assert the appropriate control signals for the SRAM operation (e.g., read or write). In this manner, the execution unit 535 can immediately issue an SRAM cycle without having to process the address further.
• the arbitration unit 530 could provide the execution unit 535 with the SRAM address and the execution unit 535 could assemble a full packet and issue it to SRAM 405.
• the SRAM 405 should be run in pipelined mode and every clock the arbitration unit 530 should be able to provide the address for the next transaction to be translated and communicate the availability of the next transaction to the execution unit 535.
• the execution unit 535 initiates and controls various SRAM operations by asserting and deasserting SRAM control signal at the appropriate times.
• the execution unit 535 may perform an execution stage which includes processing an incoming SRAM address from the arbitration unit 530 and executing it by sending it to the SRAM 405.
• GART entries are received by the execution unit 535, they are used to perform address translation or discarded. If the inbound transaction address corresponding to the GART entry is within the GART aperture, then the GART entry is used to perform address translation. However, if the inbound transaction address falls outside the GART aperture (e.g., it is a physical address), then the GART entry is dropped and no translation is performed.
• the execution unit 535 may hold old translations or use a translation look-aside buffer to facilitate address translation.
• the "translated address,” e.g., the original inbound transaction address or the physical address is provided to the writeback unit 540.
• the writeback unit 540 receives SRAM data and using information provided by the execution unit 535 and the configuration control unit 595 formats the data and routes it to the correct destination (e.g., an entry of a queue in the transaction queue unit 515). For example, according to the embodiment depicted, the writeback unit 540 is responsible for overwriting the virtual addresses of the inbound transactions with the translated address provided by the execution unit.
• FIG. 6 is a high-level flow diagram conceptually illustrating transaction processing according to one embodiment of the present invention.
• a transaction is received.
• a determination is subsequently made at step 620 based upon the transaction type whether or not to perform address translation. If the transaction is an inbound transaction (e.g., one received from the AGP bus 330), then transaction processing continues with step 630. Otherwise, if the transaction is an outbound transaction (e.g., one received from the one or more I/O ports 412), then processing continues with step 640.
• step 630 translation processing is performed. While for convenience, GART entries may be speculatively fetched from the SRAM 410, not all inbound transactions are translated.
• inbound transactions specifying a virtual address outside of the AGP range (e.g., the GART aperture) will not be translated.
• outbound transactions bypass the translation processing.
• the transaction is executed on the appropriate bus (e.g., inbound transactions are executed on one or more of the I/O ports 412 and outbound transactions are executed on the AGP bus 330).
• the GXB 410 is configured to process both AGP transactions and PCI transactions received on the AGP bus 330 to provide a level of backwards compatibility.
• the processing flow through the GXB 410 is very similar for each of the PCI, low priority AGP, and high priority AGP stream. Therefore, only the processing of an exemplary PCI transaction will be described herein.
• FIG. 7 is a flow diagram illustrating inbound PCI write transaction processing according to one embodiment of the present invention.
• a PCI cycle runs on the AGP bus 330 delivering the PCI transaction to the GXB 410 followed by the data associated with the PCI transaction.
• the PCI transaction is buffered in the PCI inbound buffer 570.
• the virtual address associated with the PCI transaction is translated to a physical address in main memory 325 as described further below (step 730).
• the PCI transaction's virtual address is overwritten with the translated address at step 740. Due to the speculative nature of the retrieval of GART entries, when translation is not to be performed, the translated address may be the same as the virtual address.
• the translated PCI transaction is buffered in the SAC inbound buffer 580 at step 750 until the transaction can be executed on the appropriate I/O port 412. Finally, the translated PCI transaction is performed by executing a write cycle on the I/O port 412. Outbound PCI Write Transaction Processing
• outbound transactions need not be translated by the GXB 410.
• processing associated with an outbound PCI write transaction will now be described with reference to Figure 8.
• a write request is executed on an I O port 412 and a PCI request is received and routed to the SAC outbound control logic 585 (steps 810 and 820). Data associated with the PCI request is transferred to the data buffer unit 510.
• the outbound PCI write transaction is performed by executing a write cycle on the AGP bus 330.
• a write completion indication may be provided after the outbound PCI write transaction has been completed successfully (steps 850 and 860).
• FIG. 9 conceptually illustrates graphics (virtual) to physical address space translation according to one embodiment of the present invention.
• a virtual address 915 comprises an AGP address 920 and an offset 925.
• the virtual address 915 represents an address in the continuous logical address space employed by the graphics accelerator 335, for example.
• the AGP address 920, a portion thereof, or other information derived from the AGP address 920 is used to retrieve an appropriate entry from the GART 905.
• Information contained within the GART entry identifies a physical page in main memory 325 containing the physical address corresponding to the virtual address 915.
• the physical page identified by the GART entry is combined with the offset 925 from the virtual address 915 to form the main memory address 930.
• the GXB 410 supports two different page sizes in main memory 325.
• the translation of the virtual address 915 depends upon the page size in which the corresponding physical address resides.
• a fixed page size e.g., 4Kbyte or 4Mbyte
• an indication of the page size is stored in a control register in the GXB 410 during system boot.
• the AGP programming model is designed using 4Kbyte pages for GART entries. By allowing a larger page size (e.g., 2Mbyte, 4Mbyte, etc.), the GXB 410 is compatible with high performance computer systems.
• the GART aperture may concurrently include pages of differing sizes.
• the address translation needs to be dynamically controlled as described below.
• Figure 10A illustrates an exemplary virtual address format which may be employed to refer to data residing in 4Kbyte pages in main memory.
• the virtual address 915 is 40 bits wide.
• the AGP address 1020 comprises 28 bits and the offset 1025 comprises 12 bits.
• Figure 10B illustrates an exemplary virtual address format which may be employed to refer to data residing in 4Mbyte pages in main memory.
• the virtual address 915 is again 40 bits wide.
• the AGP address 1021 is reduced to 18 bits and the offset 1025 is increased to 22 bits. It is contemplated that various other page sizes could be accommodated.
• Figure 11A illustrates an exemplary GART entry format 1105 to support address translation to 4Kbyte pages in main memory.
• the entry 1105 is 32 bits wide and includes a parity bit 1115, a coherency bit 1120, a valid bit 1125, a new page address 1130, and a reserved area 1 110.
• Each entry covers one 4Kbyte page.
• One megabyte is sufficient to hold 256k entries or a total of 1GB of translatable space for 4Kbyte pages.
• the parity bit 1115 covers the entire GART entry 1105. It may be generated by hardware and be calculated such that the total number of 1 's, including the parity bit 1115 total to an even or an odd number.
• the coherency bit 1120 indicates whether or not the traffic from the graphics card needs to be coherent with the system bus 315. Coherency is discussed further below.
• the valid bit 1125 indicates whether of not the SRAM 405 contains valid data for this entry. If the valid bit 1125 indicates the data is valid for the entry, then it is ok to use the entry for address translation.
• the new page address 1 130 is 24 bits wide.
• the new page address 1130 comprises a start address of a 4Kbyte physical page in main memory 325 that contains the desired physical address.
• Figure 11B illustrates an exemplary GART entry format to support address translation to 4Mbyte pages in main memory.
• the entry 1106 is 32 bits wide and includes a parity bit 1116, a coherency bit 1121, a valid bit 1126, a new page address 1131, and reserved areas 11 11 and 1136. Each entry covers one 4Mbyte page.
• the parity bit 1116 covers the entire GART entry 1106 and may be calculated such that the total number of l's, including the parity bit 1116 total to an even or an odd number.
• the coherency bit 1121 indicates whether or not the traffic from the graphics card needs to be coherent with the system bus 315. Coherency is discussed further below.
• the valid bit 1126 indicates whether of not the SRAM 405 contains valid data for entry in question. If the valid bit 1126 indicates the data is valid for the entry, then it is ok to use the entry for address translation.
• the new page address 1131 is 14 bits wide.
• the new page address 1131 comprises a start address of a 4Mbyte physical page in main memory 325 that contains the desired physical address.
• the relative positioning of the bits and fields may be different than that illustrated in the examples of Figure 11A and Figure 11B.
• the entry format may also include a page mode bit to indicate the destination page size (e.g., 4Kbyte or 4Mbyte) and provide for dynamic control of the address translation process. In this manner, more than one different page size may be concurrently supported.
• Traffic from the graphics card may or may not want to be coherent with the system bus 325.
• coherency is selectable on a page-by-page basis.
• "coherency” means that the addresses will appear on the system bus 325 so that the one or more processors 305 and 310 may snoop their caches for that address. If the texture map or other image data is marked write combining (WC) by the processor, then that data is not coherent. Addresses on the system bus 325 which hit in a processor's WC buffer are not snooped. Alternatively, the application may know that the data in main memory 325 was not used by the processor (e.g., it came from disk) and wants the graphics card to fetch the data without using system bus 325 bandwidth, so forces the access to be noncoherent.

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Bus Control (AREA)
• Memory System Of A Hierarchy Structure (AREA)

Priority Applications (5)

Applications Claiming Priority (2)

Publications (1)

Family

ID=23520487

Family Applications (1)

Country Status (10)

Cited By (4)

Families Citing this family (40)

Citations (4)

Family Cites Families (26)

• 1999
  • 1999-08-30 US US09/385,209 patent/US6457068B1/en not_active Expired - Lifetime
• 2000
  • 2000-08-18 AU AU67898/00A patent/AU6789800A/en not_active Abandoned
  • 2000-08-18 EP EP00955748A patent/EP1208443B1/en not_active Expired - Lifetime
  • 2000-08-18 KR KR10-2002-7002786A patent/KR100432470B1/ko not_active Expired - Fee Related
  • 2000-08-18 HK HK02104993.7A patent/HK1043222B/en not_active IP Right Cessation
  • 2000-08-18 JP JP2001520657A patent/JP4607405B2/ja not_active Expired - Fee Related
  • 2000-08-18 WO PCT/US2000/022833 patent/WO2001016772A1/en not_active Ceased
  • 2000-08-18 DE DE60026539T patent/DE60026539T2/de not_active Expired - Lifetime
  • 2000-08-18 CN CNB008147264A patent/CN1213374C/zh not_active Expired - Fee Related
  • 2000-09-15 TW TW089117607A patent/TW552515B/zh not_active IP Right Cessation
• 2002
  • 2002-05-09 US US10/142,706 patent/US6618770B2/en not_active Expired - Fee Related

Patent Citations (4)

Also Published As

Similar Documents

Legal Events