HK1043222B - Input/output (i/o) address translation in a bridge proximate to a local i/o bus - Google Patents

Input/output (i/o) address translation in a bridge proximate to a local i/o bus Download PDF

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Publication number
HK1043222B
HK1043222B HK02104993.7A HK02104993A HK1043222B HK 1043222 B HK1043222 B HK 1043222B HK 02104993 A HK02104993 A HK 02104993A HK 1043222 B HK1043222 B HK 1043222B
Authority
HK
Hong Kong
Prior art keywords
bus
address
memory
chipset
main memory
Prior art date
Application number
HK02104993.7A
Other languages
German (de)
English (en)
French (fr)
Chinese (zh)
Other versions
HK1043222A1 (en
Inventor
Raman Nayyar
Douglas R. Moran
Leonard W. Cross
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of HK1043222A1 publication Critical patent/HK1043222A1/en
Publication of HK1043222B publication Critical patent/HK1043222B/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
HK02104993.7A 1999-08-30 2000-08-18 Input/output (i/o) address translation in a bridge proximate to a local i/o bus HK1043222B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/385,209 US6457068B1 (en) 1999-08-30 1999-08-30 Graphics address relocation table (GART) stored entirely in a local memory of an expansion bridge for address translation
PCT/US2000/022833 WO2001016772A1 (en) 1999-08-30 2000-08-18 Input/output (i/o) address translation in a bridge proximate to a local i/o bus
US385209 2006-03-21

Publications (2)

Publication Number Publication Date
HK1043222A1 HK1043222A1 (en) 2002-09-06
HK1043222B true HK1043222B (en) 2006-06-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
HK02104993.7A HK1043222B (en) 1999-08-30 2000-08-18 Input/output (i/o) address translation in a bridge proximate to a local i/o bus

Country Status (10)

Country Link
US (2) US6457068B1 (enExample)
EP (1) EP1208443B1 (enExample)
JP (1) JP4607405B2 (enExample)
KR (1) KR100432470B1 (enExample)
CN (1) CN1213374C (enExample)
AU (1) AU6789800A (enExample)
DE (1) DE60026539T2 (enExample)
HK (1) HK1043222B (enExample)
TW (1) TW552515B (enExample)
WO (1) WO2001016772A1 (enExample)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6457068B1 (en) * 1999-08-30 2002-09-24 Intel Corporation Graphics address relocation table (GART) stored entirely in a local memory of an expansion bridge for address translation
US6785759B1 (en) * 2000-05-10 2004-08-31 International Business Machines Corporation System and method for sharing I/O address translation caching across multiple host bridges
US6789154B1 (en) * 2000-05-26 2004-09-07 Ati International, Srl Apparatus and method for transmitting data
US6748512B2 (en) * 2000-12-08 2004-06-08 Intel Corporation Method and apparatus for mapping address space of integrated programmable devices within host system memory
US7009618B1 (en) * 2001-07-13 2006-03-07 Advanced Micro Devices, Inc. Integrated I/O Remapping mechanism
US7069442B2 (en) 2002-03-29 2006-06-27 Intel Corporation System and method for execution of a secured environment initialization instruction
JP2004087867A (ja) * 2002-08-28 2004-03-18 Renesas Technology Corp 半導体集積回路装置
US7900017B2 (en) * 2002-12-27 2011-03-01 Intel Corporation Mechanism for remapping post virtual machine memory pages
GB0301448D0 (en) * 2003-01-22 2003-02-19 Falanx Microsystems As Microprocessor systems
US6874042B2 (en) * 2003-03-11 2005-03-29 Dell Products L.P. System and method for using a switch to route peripheral and graphics data on an interconnect
US7073010B2 (en) * 2003-12-02 2006-07-04 Super Talent Electronics, Inc. USB smart switch with packet re-ordering for interleaving among multiple flash-memory endpoints aggregated as a single virtual USB endpoint
US7411591B2 (en) * 2003-12-24 2008-08-12 Intel Corporation Graphics memory switch
US7278008B1 (en) 2004-01-30 2007-10-02 Nvidia Corporation Virtual address translation system with caching of variable-range translation clusters
US7334108B1 (en) 2004-01-30 2008-02-19 Nvidia Corporation Multi-client virtual address translation system with translation units of variable-range size
US7296139B1 (en) 2004-01-30 2007-11-13 Nvidia Corporation In-memory table structure for virtual address translation system with translation units of variable range size
US7496706B2 (en) * 2004-06-30 2009-02-24 Intel Corporation Message signaled interrupt redirection table
CN100345136C (zh) * 2004-06-30 2007-10-24 中国科学院计算技术研究所 使64位处理器兼容32位桥接芯片的系统及转换装置
US8533777B2 (en) 2004-12-29 2013-09-10 Intel Corporation Mechanism to determine trust of out-of-band management agents
US20060190655A1 (en) * 2005-02-24 2006-08-24 International Business Machines Corporation Apparatus and method for transaction tag mapping between bus domains
US7469312B2 (en) * 2005-02-24 2008-12-23 International Business Machines Corporation Computer system bus bridge
US7339591B2 (en) * 2005-03-10 2008-03-04 Microsoft Corporation Method to manage graphics address remap table (GART) translations in a secure system
US7370137B2 (en) * 2005-06-06 2008-05-06 Intel Corporation Inter-domain data mover for a memory-to-memory copy engine
US20070005865A1 (en) * 2005-06-29 2007-01-04 Spry Bryan L Enforcing global ordering using an inter-queue ordering mechanism
US7814279B2 (en) * 2006-03-23 2010-10-12 International Business Machines Corporation Low-cost cache coherency for accelerators
US20080028181A1 (en) * 2006-07-31 2008-01-31 Nvidia Corporation Dedicated mechanism for page mapping in a gpu
US8277401B2 (en) * 2006-09-12 2012-10-02 Boa Technology, Inc. Closure system for braces, protective wear and similar articles
US20080259556A1 (en) * 2007-04-20 2008-10-23 Tracy Mark S Modular graphics expansion system
US20090157949A1 (en) * 2007-12-18 2009-06-18 Leibowitz Robert N Address translation between a memory controller and an external memory device
US7900016B2 (en) * 2008-02-01 2011-03-01 International Business Machines Corporation Full virtualization of resources across an IP interconnect
US7904693B2 (en) * 2008-02-01 2011-03-08 International Business Machines Corporation Full virtualization of resources across an IP interconnect using page frame table
CN101414970B (zh) * 2008-11-26 2011-11-30 中兴通讯股份有限公司 Ioc模块分配方法及io交换器
US8291415B2 (en) * 2008-12-31 2012-10-16 Intel Corporation Paging instruction for a virtualization engine to local storage
JP2011118732A (ja) * 2009-12-04 2011-06-16 Yokogawa Electric Corp Ｉ／ｏノード
US8793439B2 (en) * 2010-03-18 2014-07-29 Oracle International Corporation Accelerating memory operations using virtualization information
US9477634B2 (en) * 2010-06-04 2016-10-25 Intersil Americas LLC I2C address translation
CN102880587B (zh) * 2012-10-09 2014-12-24 无锡江南计算技术研究所 基于嵌入式加速核心的独立显卡架构
CN103092797B (zh) * 2012-12-13 2016-02-03 中国航空无线电电子研究所 离散量接口同步控制装置、离散量采集及输出控制方法
JP6385761B2 (ja) * 2014-09-02 2018-09-05 株式会社メガチップス バスブリッジ及びバスブリッジ群
JP6593222B2 (ja) * 2016-02-23 2019-10-23 富士通株式会社 情報処理装置、演算処理装置及び情報処理装置の制御方法
US10372663B2 (en) * 2017-07-25 2019-08-06 Qualcomm Incorporated Short address mode for communicating waveform
CN109413122B (zh) * 2017-08-16 2022-05-13 深圳市中兴微电子技术有限公司 一种数据处理方法、网络处理器及计算机存储介质
TWI720345B (zh) * 2018-09-20 2021-03-01 威盛電子股份有限公司 多核心系統的內連線結構
US11620248B2 (en) * 2021-03-31 2023-04-04 Advanced Micro Devices, Inc. Optical bridge interconnect unit for adjacent processors
KR20240001358U (ko) 2023-02-06 2024-08-13 엄재운 디퓨져 장착구조

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01181163A (ja) 1988-01-13 1989-07-19 Seiko Instr & Electron Ltd 図形表示システム
US5072369A (en) 1989-04-07 1991-12-10 Tektronix, Inc. Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates
US5335329A (en) 1991-07-18 1994-08-02 Texas Microsystems, Inc. Apparatus for providing DMA functionality to devices located in a bus expansion chassis
WO1994016391A1 (en) 1992-12-31 1994-07-21 Intel Corporation Bus to bus interface with address translation
US5479627A (en) * 1993-09-08 1995-12-26 Sun Microsystems, Inc. Virtual address to physical address translation cache that supports multiple page sizes
US5606683A (en) * 1994-01-28 1997-02-25 Quantum Effect Design, Inc. Structure and method for virtual-to-physical address translation in a translation lookaside buffer
DE69429503T2 (de) * 1994-03-24 2002-05-16 Hewlett-Packard Co. (N.D.Ges.D.Staates Delaware), Palo Alto Übersetzungsmechanismus für Ein-/Ausgabeadressen
US6029224A (en) * 1995-06-07 2000-02-22 Lucent Technologies Inc. Self-contained memory apparatus having diverse types of memory and distributed control
US5937436A (en) * 1996-07-01 1999-08-10 Sun Microsystems, Inc Network interface circuit including an address translation unit and flush control circuit and method for checking for invalid address translations
US5983332A (en) * 1996-07-01 1999-11-09 Sun Microsystems, Inc. Asynchronous transfer mode (ATM) segmentation and reassembly unit virtual address translation unit architecture
US5857080A (en) 1996-09-10 1999-01-05 Lsi Logic Corporation Apparatus and method for address translation in bus bridge devices
US6141701A (en) * 1997-03-13 2000-10-31 Whitney; Mark M. System for, and method of, off-loading network transactions from a mainframe to an intelligent input/output device, including off-loading message queuing facilities
US5857086A (en) * 1997-05-13 1999-01-05 Compaq Computer Corp. Apparatus method and system for peripheral component interconnect bus using accelerated graphics port logic circuits
US6249853B1 (en) * 1997-06-25 2001-06-19 Micron Electronics, Inc. GART and PTES defined by configuration registers
US6195734B1 (en) * 1997-07-02 2001-02-27 Micron Technology, Inc. System for implementing a graphic address remapping table as a virtual register file in system memory
US5933158A (en) * 1997-09-09 1999-08-03 Compaq Computer Corporation Use of a link bit to fetch entries of a graphic address remapping table
US5999743A (en) * 1997-09-09 1999-12-07 Compaq Computer Corporation System and method for dynamically allocating accelerated graphics port memory space
US5914730A (en) * 1997-09-09 1999-06-22 Compaq Computer Corp. System and method for invalidating and updating individual GART table entries for accelerated graphics port transaction requests
US5914727A (en) 1997-09-09 1999-06-22 Compaq Computer Corp. Valid flag for disabling allocation of accelerated graphics port memory space
US5905509A (en) * 1997-09-30 1999-05-18 Compaq Computer Corp. Accelerated Graphics Port two level Gart cache having distributed first level caches
US5949436A (en) * 1997-09-30 1999-09-07 Compaq Computer Corporation Accelerated graphics port multiple entry gart cache allocation system and method
US6130680A (en) * 1997-12-01 2000-10-10 Intel Corporation Method and apparatus for multi-level demand caching of textures in a graphics display device
WO1999034293A1 (en) * 1997-12-30 1999-07-08 Micron Technology, Inc. Accelerated graphics port for multiple memory controller computer system
US6252612B1 (en) * 1997-12-30 2001-06-26 Micron Electronics, Inc. Accelerated graphics port for multiple memory controller computer system
US7007126B2 (en) * 1998-02-13 2006-02-28 Intel Corporation Accessing a primary bus messaging unit from a secondary bus through a PCI bridge
US6199145B1 (en) * 1998-02-27 2001-03-06 Intel Corporation Configurable page closing method and apparatus for multi-port host bridges
US6145030A (en) * 1998-03-27 2000-11-07 Intel Corporation System for managing input/output address accesses at a bridge/memory controller
US6192455B1 (en) * 1998-03-30 2001-02-20 Intel Corporation Apparatus and method for preventing access to SMRAM space through AGP addressing
US6326973B1 (en) * 1998-12-07 2001-12-04 Compaq Computer Corporation Method and system for allocating AGP/GART memory from the local AGP memory controller in a highly parallel system architecture (HPSA)
US6457068B1 (en) * 1999-08-30 2002-09-24 Intel Corporation Graphics address relocation table (GART) stored entirely in a local memory of an expansion bridge for address translation

Also Published As

Publication number Publication date
WO2001016772A1 (en) 2001-03-08
US6457068B1 (en) 2002-09-24
JP4607405B2 (ja) 2011-01-05
JP2003508850A (ja) 2003-03-04
AU6789800A (en) 2001-03-26
US6618770B2 (en) 2003-09-09
DE60026539T2 (de) 2006-08-17
EP1208443B1 (en) 2006-03-08
HK1043222A1 (en) 2002-09-06
DE60026539D1 (de) 2006-05-04
CN1213374C (zh) 2005-08-03
KR100432470B1 (ko) 2004-05-20
KR20020064280A (ko) 2002-08-07
TW552515B (en) 2003-09-11
EP1208443A1 (en) 2002-05-29
CN1382277A (zh) 2002-11-27
US20020129187A1 (en) 2002-09-12

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20160818