WO2001009953A1 - Chassis de brochage comprenant une plage de puce affaissee - Google Patents

Chassis de brochage comprenant une plage de puce affaissee Download PDF

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Publication number
WO2001009953A1
WO2001009953A1 PCT/US2000/020898 US0020898W WO0109953A1 WO 2001009953 A1 WO2001009953 A1 WO 2001009953A1 US 0020898 W US0020898 W US 0020898W WO 0109953 A1 WO0109953 A1 WO 0109953A1
Authority
WO
WIPO (PCT)
Prior art keywords
die pad
central portion
peripheral portion
electronic device
peripheral
Prior art date
Application number
PCT/US2000/020898
Other languages
English (en)
Inventor
Louis W. Nicholls
Erasmo Perez
David Roman
Original Assignee
Amkor Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amkor Technology, Inc. filed Critical Amkor Technology, Inc.
Publication of WO2001009953A1 publication Critical patent/WO2001009953A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention involves packages for electronic devices, and leadframes and methods for making such packages.
  • Conventional plastic packages include a planar metal die pad, metal leads surrounding the die pad, an electronic device on the die pad, and conductive connectors, e.g., metal bond wires, to connect the electronic device to the leads.
  • Hardened encapsulant material such as epoxy, forms a package body and encapsulates all of the above elements.
  • the die pad is downset below the leads and below a central horizontal plane of the package. In certain applications, such as cellular phones, a lower surface of the die pad is exposed at the bottom of the package so that the die pad may be conductively connected to a ground plane of a printed circuit board.
  • a ground voltage input pad on the electronic device is connected by a bond wire to the die pad, and the exposed surface of the die pad is connected by a conductive connector (such as a solder ball or a conductive adhesive) to the ground plane of the printed circuit board.
  • a conductive connector such as a solder ball or a conductive adhesive
  • the die pad may separate from the hardened encapsulant material. This problem is known as delamination.
  • the connection between the bond wire and the die pad may fail, which means that the electronic device will either have an intermittent connection to the ground voltage or no connection to ground voltage. Accordingly, there is a need for a more reliable package for these applications.
  • the present invention solves the above problems by including a package with a means to enhance the connection of the die pad to the encapsulant material and a means to enhance the performance of the conductive connection between the electronic device and the die pad.
  • the above package is made using an inventive metal leadframe.
  • a leadframe of the present invention includes a metal die pad and a plurality of metal leads adjacent to the die pad.
  • the die pad has a central portion that is downset from one or more peripheral portions that are adjacent to the central portion. In one embodiment of the die pad, the peripheral portion surrounds the die pad. In another embodiment of the die pad, two peripheral portions are adjacent to parallel sides of a rectangular die pad. Another embodiment of the die pad includes one or more protrusions along peripheral sides of a central portion of the die pad.
  • a method of making such a leadframe also is within the present invention. Step 1 of the method includes providing a metal sheet. Step 2 patterns the metal sheet to form a die pad and leads adjacent to the die pad.
  • the die pad includes a central portion and one or more peripheral portions that are laterally spaced from the central portion.
  • One or more open spaces are between the central portion of the die pad and the peripheral portions of the die pad.
  • the open spaces are spanned by metal connectors.
  • Step 3 downsets the central portion of the die pad from the leads and the peripheral portion (or portions) of the die pad so that the leads, the central area of the die pad and the peripheral portion (or portions) of the die pad are in different, albeit parallel, horizontal planes. In other words, the peripheral portion of the die pad is below the leads, and the central portion of the die pad is below the peripheral portion.
  • the peripheral portion of the die pad may surround the central area. Alternatively, separate peripheral portions each adjacent to a side of the central area of the die pad may be formed. In addition, protrusions adjacent to a perimeter of the central portion of the die pad may be formed.
  • a package within the present invention is made from the inventive leadframe(s).
  • the package includes an electronic device on the downset central portion of the die pad.
  • the electronic device is conductively connected to the leads and the peripheral portion (or portions) of the die pad.
  • the electronic device also may be conductively connected to any peripheral protrusions in the central area of the die pad.
  • An encapsulant material forms the package body and covers the peripheral portion(s) of the die pad and fills in underneath the peripheral portions of the die pad and any protrusions in the central portion of the die pad. This underfilling locks the die pad to the encapsulant material.
  • the surface of the die pad opposite the electronic device remains exposed for connection to a printed circuit board ground voltage pad.
  • the closeness of the peripheral portions to the bonding areas of the electronic device shorten the length of the bond wires connecting the device to the peripheral portion(s) of the die pad. Further, by having the peripheral portion of the die pad entirely within the package body and surrounded by encapsulant material, any thermal stresses on the bond wire that connects the device to the peripheral portion of the die pad are reduced.
  • a method of making the above described package also is within the present invention.
  • the method includes, as Step 1, providing a leadframe as described above.
  • Step 2 places an electronic device on said second surface.
  • Step 3 places a conductive connector between each of a plurality of leads and the electronic device.
  • Step 4 places a conductive connector between the electronic device and the peripheral portion of die pad, which is vertically closer to the bonding areas of the electronic device than the central portion of the die pad.
  • TQFP Thin Shrink Small Outline
  • SOIC Small Outline Integrated Circuit
  • Figure 1 is a cross-sectional view of a package containing an electronic device.
  • Figure 2 is a perspective view of a leadframe used to make the package of Figure 1.
  • Figure 3 is a perspective view of a first alternative leadframe.
  • Figure 4 is a perspective view of a second alternative leadframe.
  • FIG. 1 is a cross sectional view of a package 10 within the present invention.
  • Package 10 includes a package body formed of a hardened adhesive and insulative encapsulant material 11. Within encapsulant material 11 is an electronic device 12. Device 12 includes a top surface 13 and an opposite bottom surface 14. Top surface 13 includes a plurality of conductive pads 15 that are connected to internal circuitry of device 12. A plurality of metal leads 27 are adjacent to die pad 16 of package 10.
  • Die pad 13 includes a central portion 17, a first peripheral portion 18, and a second peripheral portion 19 that is on an opposite side of central portion 17 from first peripheral portion 18.
  • Central portion 17 has a planar first surface 20 on which device 12 is placed and an opposite planar second surface 21 that is exposed at the bottom of package 10. None or no significant encapsulant material covers second surface 21.
  • the entirety of first peripheral portion 18 and second peripheral portion 19 of die pad 16 is covered with encapsulant material 11.
  • First peripheral portion 18 of die pad 16 includes a first upper surface 22 and an opposite lower second surface 23.
  • Second peripheral portion 19 of die pad 16 includes a first upper surface 24 and an opposite lower second surface 25.
  • Bond wire connection areas 26 on upper first surfaces 22 and 25 are in a common horizontal plane that is closer to the central horizontal plane of the package than the horizontal plane of central portion 17 of die pad 16 is to the central horizontal plane of package 10. In other words, bond wire connection areas 26 are vertically closer to top surface 13 of device 12 and leads 27 than central portion 17 of die pad 16 is to top surface 13 of device 12 because central portion 17 of die pad 16 is downset from bond wire connection areas 26 of peripheral portions 18 and 19 of die pad 16. Conductive metal bond wires 28 connect pads 15 to leads 27. Another bond wire
  • bond wire 28 connects bonding area 26 of first peripheral portion 18 of die pad 16 to a ground voltage input pad 15 of electronic device 12.
  • a bond wire 28 also connects bonding area 26 of second peripheral portion 19 to a ground voltage input pad 15.
  • a plurality of bond wires 28 may connect between electronic device 12 and peripheral portions 18 and 19 of die pad 16.
  • exposed second surface 21 may be conductively connected to an external ground voltage pad of a printed circuit board (not shown).
  • the surfaces of leads 27 and bond wire attachment area 26 may be plated, for example with silver, to facilitate the connection of bond wires.
  • FIG. 1 is a perspective view of a leadframe 40 used to make package 10 of Figure
  • Figure 2 shows that central portion 17 of die pad 16 has a rectangular perimeter with four sides.
  • a tie bar 42 connects peripheral portions 18 and 19 of die pad 16 to the outer frame (not shown) of the leadframe.
  • first peripheral portion 18 and second peripheral portion 19 of die pad 16 are adjacent to and extend fully across parallel sides of central portion 17.
  • Upper surface 20 of central area 17 and upper surface 22 of peripheral portion 18 and upper surface 24 of peripheral portion 19 of die pad 16 are planar and face in the same direction.
  • upper surfaces 22 and 24 are connected to ground voltage input pads of device 12 by bond wires 28.
  • Sloped downset sections 41 of peripheral portions 18 and 19 of die pad 16 of Figure 2 show that central portion 17 is downset and spaced laterally apart from peripheral portions 18 and 19.
  • upper surface 20 of central portion 17 of die pad 16 is a parallel but vertically lower horizontal plane that upper surfaces 22 and 24 of peripheral portions 18 and 19, respectively.
  • Upper surfaces 22 and 24 are in a common horizontal plane.
  • encapsulant material fills in under peripheral portions 18 and 19 and locks die pad 16 to the encapsulant material.
  • Figure 3 is an alternative leadframe 50 that can be used to make a package similar to package 10 of Figure 1.
  • the sole difference between the packages would be in the configuration of the die pad and possibly in the connection of the electronic device to the die pad.
  • Leadframe 50 of Figure 3 is identical to leadframe 40 of Figure 3, except for the addition of two protrusions 51 which are located near the perimeter of central portion 17 of die pad 54.
  • the two protrusions 51 are located centrally and adjacent to parallel sides of central portion 17 and are located 90 degrees apart from peripheral portions 18 and 19 of die pad 54.
  • Each protrusion 51 extends upward from upper surface 20 of central portion 17 of the die pad.
  • Each protrusion 51 includes a planar upper first surface 52, which in a common horizontal plane with first surfaces 22 and 24 of peripheral portions 18 and 19, respectively, of die pad 54.
  • Downset portion 41 on protrusions 51 show that central portion 17 of die pad 54 is downset from upper surface 52 of protrusions 51, and both are below leads 28.
  • bond wires 28 may connect ground voltage input pads 15 of an electronic device 12 to upper first surfaces 52 of protrusions 51 as well as to peripheral portions 18 and 19 of the die pad 54.
  • FIG 4 shows an alternative leadframe 60 within the present invention.
  • leadframe 60 has features in common with leadframe 40 of Figure 2 and can be used to make a package like package 10 of Figure 1.
  • the difference between leadframe 40 of Figure 2 and leadframe 60 of Figure 4 is that a peripheral portion 62 of die pad 61 surrounds central portion 17 of die pad 61.
  • Ten sloped downset portions 41 of peripheral portion 62 connect peripheral portion 62 to central portion 17 of die pad 61 and space peripheral portion 62 laterally and vertically apart from central portion 17.
  • encapsulant material covers peripheral portion 62, and encapsulant material under lower surface 64 of peripheral portion 62 locks the die pad to the encapsulant material.
  • one or more bond wires 28 may connect ground voltage input pads 15 of an electronic device 12 to upper surface 63 of peripheral portion 62.
  • Upper surface 63 of peripheral portion 62 is in a parallel but vertically separate horizontal plane than central portion 17 of die pad 61.
  • a method of making the leadframes of the present invention such as the leadframes in Figures 2-4, also is within the present invention.
  • Step 1 of the method provides a planar metal sheet. Any of the common leadframe metals may be used, such as copper, copper alloys, or Alloy 42.
  • Step 2 patterns the leadframe. The patterning makes holes of various sizes and shapes in the metal sheet. Step 2 is performed using conventional methods such as progressive stamping, or chemical etching using a photoresist mask.
  • an array of leadframes is made in a single sheet of metal, and the leadframes and packages are processed in parallel.
  • a next step plates the portions of the die pad and leads to which bond wires or equivalent conductors will be connected.
  • Common plating metals such as silver or nickel palladium, are used.
  • Step 3 is a double downset step. Step 3 downsets peripheral portions 18 and 19 of die pad 16 below leads 27, and downsets the central portion 17 of the die pad below peripheral portions 18 and 19.
  • Downsetting is a stamping type of method that stretches the metal between adjacent parts. For example, referring to leadframe 60 of Figure 4, there are ten metal downset connectors 41 between peripheral portion 62 and central portion 17 of die pad 61, and these connectors are stretched and sloped during the downset step. The amount of downsetting varies depending, for example, on the thickness of the package.
  • Step 1 provides a leadframe such as shown in Figures 2-4 or equivalent.
  • Step 2 places an electronic device 12 on an upper surface 20 of central portion 17 of die pad 16, and attaches the electronic device with a conventional adhesive using conventional techniques.
  • Step 3 connects bond wires 28 between conductive pads 15 on device 12 and leads 27.
  • Step 4 connects one or more bond wires 28 from ground voltage input pads 15 of device 12 to upper surface 22 of peripheral portion 18 and/or to upper surface 24 of peripheral portion 19 of die pad 16.
  • Step 5 encapsulates the package using conventional techniques, such as injection or transfer molding using epoxy or other plastic molding compounds.
  • encapsulation material covers electronic device 12, bond wires 28, upper surface 20 and peripheral portions 18 and 19.
  • Encapsulant material fills in beneath lower surfaces 23 and 25 of peripheral portions 18 and 19, respectively. This locks die pad 16 to the encapsulant material.
  • encapsulant material does not cover, or does not significantly cover, lower surface 21 of central area 17 of die pad 16. Lower surface 21 remains exposed at the bottom surface of the package ( Figure 1).
  • a completed package is mounted by soldering leads 27 to a printed circuit board, and by conductively connecting the exposed lower surface 21 of the die pad to a ground voltage pad on the printed circuit board.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

On décrit un boîtier en plastique, des châssis de brochage et des procédés de fabrication dudit boîtier. Le boîtier comprend une plage de puce dont une surface inférieure est exposée au niveau d'une surface inférieure dudit boîtier, et une partie périphérique qui s'étend vers le haut dans une partie centrale du boîtier. Un fil de connexion connecte la partie périphérique de la plage de puce à un plot d'entrée de tension de masse d'un dispositif électronique encapsulé, ceci formant une connexion protégée. La matière d'encapsulation vient ensuite se loger sous la partie périphérique en relief de la plage de puce et immobilise ainsi la plage de puce sur la matière d'encapsulation.
PCT/US2000/020898 1999-07-30 2000-07-31 Chassis de brochage comprenant une plage de puce affaissee WO2001009953A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US36559699A 1999-07-30 1999-07-30
US09/365,596 1999-07-30

Publications (1)

Publication Number Publication Date
WO2001009953A1 true WO2001009953A1 (fr) 2001-02-08

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PCT/US2000/020898 WO2001009953A1 (fr) 1999-07-30 2000-07-31 Chassis de brochage comprenant une plage de puce affaissee

Country Status (1)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004036646A1 (fr) * 2002-10-09 2004-04-29 Micronas Gmbh Dispositif de support pour circuits monolithiquement integres
US7064420B2 (en) 2002-09-30 2006-06-20 St Assembly Test Services Ltd. Integrated circuit leadframe with ground plane
US20110089556A1 (en) * 2009-10-19 2011-04-21 National Semiconductor Corporation Leadframe packages having enhanced ground-bond reliability

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169753A (ja) * 1987-01-07 1988-07-13 Nec Yamagata Ltd リ−ドフレ−ム
JPS63308359A (ja) * 1987-06-10 1988-12-15 Mitsui Haitetsuku:Kk リ−ドフレ−ムの製造方法
JPH05235233A (ja) * 1992-02-26 1993-09-10 Toshiba Corp リ−ドフレ−ム
US5479050A (en) * 1990-10-18 1995-12-26 Texas Instruments Incorporated Leadframe with pedestal
US5789806A (en) * 1995-08-02 1998-08-04 National Semiconductor Corporation Leadframe including bendable support arms for downsetting a die attach pad

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169753A (ja) * 1987-01-07 1988-07-13 Nec Yamagata Ltd リ−ドフレ−ム
JPS63308359A (ja) * 1987-06-10 1988-12-15 Mitsui Haitetsuku:Kk リ−ドフレ−ムの製造方法
US5479050A (en) * 1990-10-18 1995-12-26 Texas Instruments Incorporated Leadframe with pedestal
JPH05235233A (ja) * 1992-02-26 1993-09-10 Toshiba Corp リ−ドフレ−ム
US5789806A (en) * 1995-08-02 1998-08-04 National Semiconductor Corporation Leadframe including bendable support arms for downsetting a die attach pad

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 012, no. 435 (E - 683) 16 November 1988 (1988-11-16) *
PATENT ABSTRACTS OF JAPAN vol. 013, no. 147 (E - 741) 11 April 1989 (1989-04-11) *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 687 (E - 1478) 16 December 1993 (1993-12-16) *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064420B2 (en) 2002-09-30 2006-06-20 St Assembly Test Services Ltd. Integrated circuit leadframe with ground plane
SG132500A1 (en) * 2002-09-30 2007-06-28 Stats Chippac Ltd Integrated circuit leadframe with ground plane
WO2004036646A1 (fr) * 2002-10-09 2004-04-29 Micronas Gmbh Dispositif de support pour circuits monolithiquement integres
KR101003061B1 (ko) 2002-10-09 2010-12-22 미크로나스 게엠베하 모노리식 집적 회로용 캐리어 장치
US20110089556A1 (en) * 2009-10-19 2011-04-21 National Semiconductor Corporation Leadframe packages having enhanced ground-bond reliability
US8093707B2 (en) * 2009-10-19 2012-01-10 National Semiconductor Corporation Leadframe packages having enhanced ground-bond reliability

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