WO2000070764A1 - Interface de bus compacte a isolement electrique integre - Google Patents

Interface de bus compacte a isolement electrique integre Download PDF

Info

Publication number
WO2000070764A1
WO2000070764A1 PCT/DE2000/001382 DE0001382W WO0070764A1 WO 2000070764 A1 WO2000070764 A1 WO 2000070764A1 DE 0001382 W DE0001382 W DE 0001382W WO 0070764 A1 WO0070764 A1 WO 0070764A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
circuit according
data terminal
terminal device
bus
Prior art date
Application number
PCT/DE2000/001382
Other languages
German (de)
English (en)
Inventor
Dieter Munz
Harald GÜNTHER
Michael Staudt
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO2000070764A1 publication Critical patent/WO2000070764A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40013—Details regarding a bus controller
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks

Definitions

  • the invention relates to an integrated circuit which has an adapter unit for bidirectional connection of a bus to a data terminal device, the integrated circuit being provided with at least one connection for the bus.
  • the object of the invention is to show a new bus interface whose power consumption is.
  • a bus interface implemented as an integrated circuit with the features according to the invention has a lower power consumption than conventional bus interfaces due to the integration of a magneto-sensitive device for potential isolation in the integrated circuit.
  • a bus interface implemented by means of the claimed integrated circuit requires less space on the board used.
  • a reduction of the module costs, the assembly costs and the storage costs is achieved by means of the invention.
  • Further advantages of the invention consist in the fact that a compact bus interface according to the invention is suitable for supply voltages that are significantly smaller than 5 V. Furthermore, higher data rates can be achieved by means of the circuit claimed than by means of known bus interfaces.
  • FIGURE 1 shows a first embodiment of the invention
  • FIGURE 2 shows a second embodiment of the invention.
  • Figure 1 shows a first embodiment of the invention.
  • the compact bus interface shown has an integrated circuit 1. This is provided with connections 2, 3, 4, 5 and 6.
  • the connections 2, 3 and 4 are connected via signal lines to a data terminal device, not shown, which preferably has a microcomputer. This is provided for the generation of data to be transmitted via the bus 7 to another data terminal device and for the processing of data which are received via the bus 7 from another data terminal device.
  • connections 2 and 3 are input connections via which signals generated by the data terminal device are fed to the integrated circuit 1.
  • control signals are present at connection 2, which contain activation information, and useful signal data to be transmitted at connection 4.
  • Reference number 4 denotes an output connection via which data from the integrated circuit 1 are output to the data terminal device. These data are data transmitted via the bus 7 and are provided for the data terminal device.
  • the signal present at the input terminal 2 is first fed to a first transmitter logic 8 within the integrated circuit 1.
  • This has the task of converting the input signal mentioned into a current signal, which is particularly well suited for magnetosensitive transmission.
  • a signal inversion can take place in the transmitter logic 8, for example.
  • a transmitter U1 is connected to the first transmitter logic 8 and is provided for magneto-sensitive transmission of the output signal of the transmitter logic 8. This magnetosensitive transmission is carried out in order to isolate the potential between the data terminal device and the bus 7 to reach. As a result, the signals to be transmitted are transmitted potential-free between the various terminal devices.
  • the transformer U1 has a conductor loop on the input side, via which the output signal of the transmitter logic 8 is carried. This signal generates a magnetic field which changes as a function of the signal in the area surrounding the conductor loop and which is indicated in FIG. 1 by the dashed lines. This changing magnetic field is recognized by a magnetic field detector or magnetosensitive receiver 9, which is separated from the conductor loop by an insulator, but is located in the area of the magnetic field mentioned.
  • the magnetic field detector of the device Ül for potential isolation can be implemented in the form of a Hall element. Furthermore, the magnetic field detector mentioned can also be an AMR sensor (anisotropic magnetic resistance), which reacts to a changing magnetic field with a change in resistance. Such AMR sensors have a permalloy layer.
  • GMR sensors of this type have a combination of three layers, two of which are soft magnetic and one is hard magnetic.
  • a further improvement in the sensitivity of the magnetic field detector is possible in that it is implemented as a TMR sensor (tunneling magnetic resistance).
  • the hard magnetic layer is provided with an additional insulator.
  • the signal detected by the magnetosensitive receiver 9 is a signal that is galvanically separated from the data terminal device a matching unit 10 supplied.
  • This adapter unit is a transceiver and contains the transmission and reception logic necessary for data communication via the bus 7.
  • the signal present at the input connection 3 is fed to a second magnetosensitive transmitter U2 within the integrated circuit 1 via a second transmitter logic 11 and also passed on to the adapter unit 10 via its magnetosensitive receiver 12.
  • the structure and the mode of operation of the transmitter logic 11 and the transmitter U2 with the magnetosensitive receiver 12 correspond to the structure and the mode of operation of the modules 8, U1 and 9 already explained above.
  • the output signals of the adaptation unit 10 which can be, for example, an RS485 driver or a SIM1 driver, are passed on to the bus 7 via an output connection 5 of the integrated circuit 1 and are fed to a further data terminal via the latter.
  • a response signal generated by this further data terminal device is transmitted via the bus 7 and made available to the integrated circuit 1 at its input connection 6.
  • the signal present there is forwarded to the adaptation unit 10 and, after processing in it, is passed to a further transmitter logic 13.
  • This converts the present signal into a signal that is particularly well suited for magnetosensitive transmission.
  • a third magnetosensitive transmitter U3 with a magnetosensitive detector 14 is provided on the further transmitter logic 13. The signal detected by this is provided at the output terminal 4 of the integrated circuit 1 and from there is supplied to the data terminal device, not shown.
  • a magnetosensitive transducer U1 for poling is installed in an integrated circuit 1 having a matching unit 10. tential isolation between a data terminal and a bus 7 integrated.
  • Such a solution simplifies the construction of bus interfaces, enables more cost-effective production, allows high data rates, saves electricity and is also suitable for supply voltages that are significantly less than 5 V.
  • FIG. 2 shows a second embodiment of the invention.
  • the compact bus interface shown has an integrated circuit 15. This is provided with connections 16 and 21.
  • the connection 16 is an input connection via which the integrated circuit is supplied with input signals from a data processing device which are to be transmitted via the bus 22 to a receiving device likewise connected to the bus 22.
  • the output signals of the integrated circuit 15 to be transmitted via the bus 22 are output to the bus 22 via the connection 21, which is a bidirectional connection.
  • the input signal present at the input connection 16 is fed within the integrated circuit 15 to a microcomputer 17, which performs the function of a data terminal device for the data processing device connected to the input 16 of the integrated circuit. From the microcomputer 17, the signals to be transmitted are fed to a matching unit 20 via a magnetosensitive coupling element 18, which is constructed in the same way as the magnetosensitive transducers explained above in connection with FIG. This provides the data to be sent via the bus 22 at its output 21.
  • Response signals of a further data device connected to the bus, which are received via the connection 21, are forwarded to the adaptation unit 20 and are subjected to receive signal processing there.
  • the response signals output by the adaptation unit 20 are transmitted via a circuit 15 integrated magnetosensitive coupling element 19 forwarded to the microcomputer 17, in which a signal adaptation to the signal format in the received data terminal takes place.
  • the signals adapted in this sense are passed on to the data terminal via the connection 16.
  • a magnetosensitive transmitter 18 for potential isolation between the data device and the bus 22 is consequently integrated in an integrated circuit 15 having a matching unit 20.
  • the data terminal device itself also belongs to the integrated circuit 15.
  • the bus interface can be produced more cost-effectively. It also takes up less space, is energy efficient, allows high data rates and is also suitable for supply voltages that are significantly less than 5 V.
  • the basic principle described on the basis of the above exemplary embodiments can be used with all common bus couplings. Compared to known bus couplings, it saves external wiring and thus offers a space-saving and cheaper alternative to the known bus interfaces.
  • the claimed integrated circuit in connection with an RS485 interface, the Profibus of the applicant, an ETHERNET bus interface, the IEEE 1394-1995 and the ASI bus, the CAN bus, the SPI bus and an RS 422 interface be used.
  • the invention also makes it possible to combine assemblies realized in the form of a plurality of modules in known solutions to form a single integrated circuit in a housing.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention concerne un circuit intégré muni d'un adaptateur pour une connexion bidirectionnelle d'un bus à un terminal de données. Le circuit intégré est muni d'au moins une connexion pour le bus. Il renferme en outre un dispositif magnétosensible pour l'isolement électrique. L'adaptateur est disposé entre le dispositif magnétosensible pour l'isolement électrique et la connexion pour le bus.
PCT/DE2000/001382 1999-05-12 2000-05-03 Interface de bus compacte a isolement electrique integre WO2000070764A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19922123.5 1999-05-12
DE1999122123 DE19922123A1 (de) 1999-05-12 1999-05-12 Kompakte Busschnittstelle mit integrierter Potentialtrennung

Publications (1)

Publication Number Publication Date
WO2000070764A1 true WO2000070764A1 (fr) 2000-11-23

Family

ID=7907986

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/001382 WO2000070764A1 (fr) 1999-05-12 2000-05-03 Interface de bus compacte a isolement electrique integre

Country Status (2)

Country Link
DE (1) DE19922123A1 (fr)
WO (1) WO2000070764A1 (fr)

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US6873065B2 (en) 1997-10-23 2005-03-29 Analog Devices, Inc. Non-optical signal isolator
US20030042571A1 (en) 1997-10-23 2003-03-06 Baoxing Chen Chip-scale coils and isolators based thereon
US6262600B1 (en) 2000-02-14 2001-07-17 Analog Devices, Inc. Isolator for transmitting logic signals across an isolation barrier
DE10262239B4 (de) 2002-09-18 2011-04-28 Infineon Technologies Ag Digitales Signalübertragungsverfahren
US7075329B2 (en) 2003-04-30 2006-07-11 Analog Devices, Inc. Signal isolators using micro-transformers
DE10353469A1 (de) * 2003-11-15 2005-06-23 Itw Morlock Gmbh Elektrischer Steckverbinder
DE102004030767A1 (de) * 2004-06-25 2006-01-19 Siemens Ag AS-Interface-Netzwerk für große Entfernungen
DE102004032513B4 (de) * 2004-07-06 2013-04-04 Continental Teves Ag & Co. Ohg Schaltungsanordnung zum kontaktlosen Abgreifen von elektrischen Signalen von mindestens einer Signalleitung
DE102005047971B4 (de) * 2005-10-06 2008-01-17 Dr.-Ing. Gschwind Elektronik Gmbh Belastungsmessvorrichtung
US7719305B2 (en) 2006-07-06 2010-05-18 Analog Devices, Inc. Signal isolator using micro-transformers
DE102006039607A1 (de) * 2006-08-24 2008-04-30 Schleifring Und Apparatebau Gmbh Magnetischer Drehübertrager
US9293997B2 (en) 2013-03-14 2016-03-22 Analog Devices Global Isolated error amplifier for isolated power supplies
US9660848B2 (en) 2014-09-15 2017-05-23 Analog Devices Global Methods and structures to generate on/off keyed carrier signals for signal isolators
US10536309B2 (en) 2014-09-15 2020-01-14 Analog Devices, Inc. Demodulation of on-off-key modulated signals in signal isolator systems
US10270630B2 (en) 2014-09-15 2019-04-23 Analog Devices, Inc. Demodulation of on-off-key modulated signals in signal isolator systems
US9998301B2 (en) 2014-11-03 2018-06-12 Analog Devices, Inc. Signal isolator system with protection for common mode transients
US10324144B2 (en) 2016-12-20 2019-06-18 Infineon Technologies Austria Ag Lateral transmission of signals across a galvanic isolation barrier

Citations (6)

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Publication number Priority date Publication date Assignee Title
US4801883A (en) * 1986-06-02 1989-01-31 The Regents Of The University Of California Integrated-circuit one-way isolation coupler incorporating one or several carrier-domain magnetometers
US5399965A (en) * 1992-02-21 1995-03-21 Deutsche Itt Industries Gmbh Floating data interface
WO1998037672A1 (fr) * 1997-02-21 1998-08-27 Analog Devices, Inc. Isolateur logique a immunite transitoire elevee
US5831426A (en) * 1996-08-16 1998-11-03 Nonvolatile Electronics, Incorporated Magnetic current sensor
DE19718420A1 (de) * 1997-04-30 1998-11-12 Siemens Ag Integrierte Datenübertragungsschaltung mit Potentialtrennung zwischen Ein- und Ausgangsschaltkreis
WO1999021332A1 (fr) * 1997-10-23 1999-04-29 Analog Devices, Inc. Isolateur de signal a couplage magnetique comprenant un element de reception mr ou gmr protege par un ecran de faraday

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4801883A (en) * 1986-06-02 1989-01-31 The Regents Of The University Of California Integrated-circuit one-way isolation coupler incorporating one or several carrier-domain magnetometers
US5399965A (en) * 1992-02-21 1995-03-21 Deutsche Itt Industries Gmbh Floating data interface
US5831426A (en) * 1996-08-16 1998-11-03 Nonvolatile Electronics, Incorporated Magnetic current sensor
WO1998037672A1 (fr) * 1997-02-21 1998-08-27 Analog Devices, Inc. Isolateur logique a immunite transitoire elevee
DE19718420A1 (de) * 1997-04-30 1998-11-12 Siemens Ag Integrierte Datenübertragungsschaltung mit Potentialtrennung zwischen Ein- und Ausgangsschaltkreis
WO1999021332A1 (fr) * 1997-10-23 1999-04-29 Analog Devices, Inc. Isolateur de signal a couplage magnetique comprenant un element de reception mr ou gmr protege par un ecran de faraday

Non-Patent Citations (1)

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Title
CLARK R ET AL: "GALVANISCHE TRENNUNG FUER DIE DATENUEBERTRAGUNG", ELEKTRONIK,DE,FRANZIS VERLAG GMBH. MUNCHEN, vol. 46, no. 13, 24 June 1997 (1997-06-24), pages 102 - 106, XP000735476, ISSN: 0013-5658 *

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Publication number Publication date
DE19922123A1 (de) 2000-11-23

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