WO2000061372A1 - Circuit d'attaque pour une tete d'impression thermique a jet d'encre - Google Patents

Circuit d'attaque pour une tete d'impression thermique a jet d'encre Download PDF

Info

Publication number
WO2000061372A1
WO2000061372A1 PCT/IT2000/000122 IT0000122W WO0061372A1 WO 2000061372 A1 WO2000061372 A1 WO 2000061372A1 IT 0000122 W IT0000122 W IT 0000122W WO 0061372 A1 WO0061372 A1 WO 0061372A1
Authority
WO
WIPO (PCT)
Prior art keywords
power transistor
transistor
drive circuit
circuit
state
Prior art date
Application number
PCT/IT2000/000122
Other languages
English (en)
Inventor
Angelo Menegatti
Renato Conta
Original Assignee
Olivetti Lexikon S.P.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olivetti Lexikon S.P.A. filed Critical Olivetti Lexikon S.P.A.
Publication of WO2000061372A1 publication Critical patent/WO2000061372A1/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04541—Specific driving circuit
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/0455—Details of switching sections of circuit, e.g. transistors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/0458—Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads based on heating elements forming bubbles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2202/00—Embodiments of or processes related to ink-jet or thermal heads
    • B41J2202/01—Embodiments of or processes related to ink-jet heads
    • B41J2202/13—Heads having an integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Definitions

  • This invention relates to a drive circuit for a thermal ink jet printhead, comprising a thermal resistor suitable for generating a jet of ink in the presence of a predetermined current, a power transistor connected to the thermal resistor and suitable for assuming an ON state for activating the predetermined current, and a logic circuit connected to the power transistor for selectively controlling the power transistor to assume the ON state.
  • This known circuit comprises a thermal resistor for generating a bubble of steam and ejecting a droplet of ink, a power transistor having the “drain” connected to the thermal resistor and the “source” to earth, a logic drive circuit for selectively controlling the power transistor and a voltage booster circuit placed between the logic drive circuit and the power transistor for elevating the level of the voltage output by the logic drive circuit and applying this converted level as the "gate” voltage (V G ) to the "gate” of the power transistor to bring it into the ON state and accordingly activate the heating of the thermal resistor.
  • the voltage booster circuit is necessary for commanding the power transistor in a region of the characteristics RON — V G in which total resistance of the transistor in the ON state (RON or total ON Resistance) , namely the sum of the Resistance due to the physical characteristics of the transistor alone (RONC or channel ON Resistance) and of the parasitic resistance due to the interconnections (R P ) , is low, in substance in the region of 3.5 ⁇ 4.5 ⁇ .
  • the object of this invention is the production of a MOS technology integrated circuit that does not require the insertion of voltage booster circuits for driving the transistors that supply energy to the thermal resistors of the printhead.
  • This technical problem is solved by the drive circuit for a thermal ink jet printhead characterised in that the power transistor is produced using the MOS technology and is suitable for assuming the ON state with a gate voltage V G of between 4.5 and 5.5 Volt.
  • Fig. 1 represents a block diagram of a printhead
  • Fig. 2 represents a section of the power transistor of Fig.l
  • Fig.3 represents curves Ro N —> V G typical of power transistors in accordance with the known art and according to this invention.
  • a drive circuit 10 for a printhead comprises a predefined number of thermal resistors 11, corresponding to the number of nozzles in the printhead, an equivalent number of power transistors 12, an equivalent number of logic control circuits 14 and one or more shift registers 15 of width measured as a number of bits at least equal to the number of the resistors 11.
  • Each resistor 11 has its first terminal connected to a reference voltage (voltage V C c) , of between 6.5 and 12.5 Volt for example, and its second terminal connected to a corresponding transistor, in particular to the drain 12b of the transistor 12 and is suitable for generating the thermal energy necessary for the activation of a jet of ink by a corresponding nozzle associated therewith in the printhead, when the transistor 12 is active (ON) .
  • V C c reference voltage
  • Each logic circuit 14 with two inputs and one output, has the first input connected to a timing circuit (strobe) , not depicted in the figure, by means of a connection 18, the second input to an output of the register 15, and the output to the corresponding transistor 12, in particular to its controlling electrode (gate) 12a.
  • strobe timing circuit
  • Each logic circuit 14 is suitable for activating the conduction of the transistor 12 subject to the presence of a bit with value 1 output by the register 15 and for a time determined by the timing circuit by means of a strobe signal on the connection 18.
  • the register 15, of known type, is suitable for storing a temporary map of bits with value 0 or 1 representative of the nozzles to be activated through the respective resistors 11 and for simultaneously commanding the selective activation of the resistors 11, by means of the corresponding logic circuits 14 and transistors 12.
  • Each transistor 12 has the source 12c connected to ground and, as already described, the gate 12a to the output of the respective logic circuit 14, and the drain 12b to the second terminal of the respective resistor 11 and is suitable for switching from an OFF state (non-conduction) to the ON state in relation to the voltage V G applied to the gate 12a.
  • Each transistor 12, a distinguishing element of this invention, is produced according to MOS technology, as is all of the drive circuit 10.
  • the drive logic is CMOS type and the transistor 12 is LDMOS type (Lateral Double-diffusion Metal Oxide Semiconductor) and comprises, in accordance with a section thereof, a P type substrate 21 (Fig. 2) , known in itself, an N- doped region (Nwell) 22, known in itself, which extends to the entire area of the electrodes.
  • LDMOS type Layer Double-diffusion Metal Oxide Semiconductor
  • the transistor 12 comprises, in correspondence with the source 12c, a P+ doped region 23 adjacent to an N+ doped region, of known type, and, set between the Nwell region 22 and the P+ and N+ regions, 23 and 24 respectively, a P- doped region, of known type, which extends by diffusion underneath the area of the electrode of the gate 12a and determines the value of L reported in the formula (1), as will be described in detail later.
  • the transistor 12 comprises, in correspondence with the drain 12b, an N+ doped region, of known type.
  • the transistor 12 finally also comprises, in correspondence with the gate 12a, a layer of oxide 27 having a thickness T 0 ⁇ the value of which, as is known, is inversely proportional to the value of the capacitance Cox shown in the formula (1) .
  • the transistor 12 an LDMOS type transistor, the advantage is obtained of being able to control the value of L irrespective of the width of the gate electrode 12a.
  • the advantage is also obtained of limiting the threshold voltage V TH to values of between 0.6 and 1.0 V and accordingly of obtaining a further lowering of the RONC of the transistor 12. If, in fact, we refer again to the formula (1) :
  • the drive circuit 10 does not differ from that of the known drive circuits, but it is advantageous in that the power transistor 12, of the LDMOS type for example, can be driven with the same voltage as that generally used in the logic circuit 14, of the CMOS type for example, and in the shift register 15, namely 5 Volt.
  • the drive circuit 10 in accordance with this invention, presents the further advantages of not requiring a voltage booster circuit for each power transistor and of being technologically feasible without any special expedients .
  • the transistor 12 may be produced using other types of MOS technology that enable the value of L to be controlled and in particular the thickness T 0 ⁇ of the layer of oxide 27 for obtaining the desired values of the gate voltage V G and of the total RON, without departing from the spirit of the invention.
  • the transistor 12 may be of the NMOS or NDDD- NMOS (Double Diffusion Drain NMOS) type.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Particle Formation And Scattering Control In Inkjet Printers (AREA)

Abstract

L'invention concerne un circuit intégré destiné à attaquer des têtes d'impression à jet d'encre. Ce circuit (10) comprend une résistance thermique (11) destinée à générer une bulle de vapeur et à éjecter une gouttelette d'encre, un circuit d'attaque logique (14, 15), et un transistor de puissance (12), lequel est connecté à la résistance thermique (11) et commandé directement par le circuit logique (14, 15). Le transistor (12) est fabriqué selon la même technique que ledit circuit logique (14, 15), et attaqué au moyen d'une tension de grille VG variant entre 4,5 et 5,5 volts. Enfin, ce circuit (10) ne nécessite aucune insertion de dispositifs pour augmenter la tension entre le circuit logique (14, 15) et le transistor de puissance (12), la résistance totale RON du transistor, variant entre 3,5 4.5 Φ, pouvant néanmoins être maintenue.
PCT/IT2000/000122 1999-04-12 2000-04-05 Circuit d'attaque pour une tete d'impression thermique a jet d'encre WO2000061372A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ITTO990280 IT1307033B1 (it) 1999-04-12 1999-04-12 Circuito di pilotaggio per testina di stampa termica a gettod'inchiostro.
ITTO99A000280 1999-04-12

Publications (1)

Publication Number Publication Date
WO2000061372A1 true WO2000061372A1 (fr) 2000-10-19

Family

ID=11417712

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IT2000/000122 WO2000061372A1 (fr) 1999-04-12 2000-04-05 Circuit d'attaque pour une tete d'impression thermique a jet d'encre

Country Status (2)

Country Link
IT (1) IT1307033B1 (fr)
WO (1) WO2000061372A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1221720A2 (fr) 2000-12-28 2002-07-10 Canon Kabushiki Kaisha Dispositif semi-conducteur, son procédé de fabrication, et dispositif à jet d'encre
US7018012B2 (en) 2003-11-14 2006-03-28 Lexmark International, Inc. Microfluid ejection device having efficient logic and driver circuitry
WO2018156171A1 (fr) * 2017-02-27 2018-08-30 Hewlett-Packard Development Company, L.P. Évaluation de capteur de buse

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0816082A2 (fr) 1996-06-26 1998-01-07 Canon Kabushiki Kaisha Tête d'enregistrement et appareil d'enregistrement l'utilisant

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0816082A2 (fr) 1996-06-26 1998-01-07 Canon Kabushiki Kaisha Tête d'enregistrement et appareil d'enregistrement l'utilisant

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MANZINI S ET AL: "HOT-ELECTRON INJECTION AND TRAPPING IN THE GATE OXIDE OF SUBMICRON DMOS TRANSISTORS", INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S,US,NEW YORK, NY: IEEE, 1998, pages 415 - 418, XP000801105, ISBN: 0-7803-4752-8 *
VESTLING L ET AL: "A NOVEL HIGH-FREQUENCY HIGH-VOLTAGE LDMOS TRANSISTOR USING AN EXTENDED GATE RESURF TECHNOLOGY", IEEE INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS,US,NEW YORK, NY: IEEE, vol. CONF. 9, 1997, pages 45 - 48, XP000800154, ISBN: 0-7803-3994-0 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1221720A2 (fr) 2000-12-28 2002-07-10 Canon Kabushiki Kaisha Dispositif semi-conducteur, son procédé de fabrication, et dispositif à jet d'encre
EP1221720A3 (fr) * 2000-12-28 2007-08-01 Canon Kabushiki Kaisha Dispositif semi-conducteur, son procédé de fabrication, et dispositif à jet d'encre
EP2302677A1 (fr) * 2000-12-28 2011-03-30 Canon Kabushiki Kaisha Procédé de fabrication d'un dispositif semi-conducteur
US7018012B2 (en) 2003-11-14 2006-03-28 Lexmark International, Inc. Microfluid ejection device having efficient logic and driver circuitry
WO2018156171A1 (fr) * 2017-02-27 2018-08-30 Hewlett-Packard Development Company, L.P. Évaluation de capteur de buse
US10632742B2 (en) 2017-02-27 2020-04-28 Hewlett-Packard Development Company, L.P. Nozzle sensor evaluation

Also Published As

Publication number Publication date
ITTO990280A1 (it) 2000-10-12
IT1307033B1 (it) 2001-10-23

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