WO2000059277A1 - Procede de production de cartes a circuit imprime - Google Patents

Procede de production de cartes a circuit imprime Download PDF

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Publication number
WO2000059277A1
WO2000059277A1 PCT/JP2000/001799 JP0001799W WO0059277A1 WO 2000059277 A1 WO2000059277 A1 WO 2000059277A1 JP 0001799 W JP0001799 W JP 0001799W WO 0059277 A1 WO0059277 A1 WO 0059277A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
plating
insulating layer
printed wiring
wiring board
Prior art date
Application number
PCT/JP2000/001799
Other languages
English (en)
Japanese (ja)
Inventor
Yoshinori Takazaki
Original Assignee
Ibiden Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co., Ltd. filed Critical Ibiden Co., Ltd.
Publication of WO2000059277A1 publication Critical patent/WO2000059277A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor

Definitions

  • the present invention relates to a method for manufacturing a printed wiring board.
  • the build-up layer in such a multilayer printed ffiilS plate is formed by the following procedure. 1) First, an additive adhesive for forming an absolute thickness is applied on the base so as to have a thickness of about several tens ⁇ . 2) By exposing and developing the formed layer, the inner diameter is 100 / ⁇ ! A via forming hole of about 200 / ⁇ m is formed. 3) After performing the roughening treatment, the catalyst nucleation, and the activation treatment, electroless plating is performed to form a base plating layer on the entire surface of the insulating layer. 4) After that, apply the electrolytic panel to the underlayer. At the same time, a via-hole formed by depositing a plating layer in the via-forming hole is formed. 5) A conductor pattern of a predetermined shape is formed by depositing on the insulating layer and etching the tacky layer. 6) Repeat steps 1 to 5 as necessary.
  • the present invention has been made in view of the above, and an object of the present invention is to provide a method of manufacturing a printed wiring board which can relatively easily form a filled via in a build-up layer without increasing cost. Is to do.
  • the invention according to claim 1, which solves the above problem, is a method for manufacturing a printed wiring board in which a filled via is formed by a plating method on an insulating layer constituting a build-up layer, wherein the insulating layer having a predetermined thickness is provided. After forming a small-diameter via-forming hole, a base plating layer is formed on the entire insulating layer using an electroless plating bath, and then an electrolytic plating bath formed by adding an additive having a leveling action is formed. An electrolytic panel having a substantially flat surface on the insulating layer and filling the via-forming hole by passing an electric current having a substantially constant voltage value to the electrolytic plating on the underlying plating layer. This is a method for manufacturing a printed wiring board that forms an plating film.
  • the relationship between the thickness of the insulating layer and the opening diameter of the via-forming hole is as follows: thickness 20 ⁇ ! ⁇ 40 ⁇ ⁇ Insulating layer with a hole diameter of 25 / zm to 50 / zm in the self-insulating layer, and 25 ⁇ m in the insulating layer with a thickness of about 60 / m 2.
  • the invention according to claim 3 is the method for manufacturing a printed wiring board according to claim 1 or 2, wherein the thickness of the electrolytic panel plating film is about 10 ⁇ m. .
  • the diameter of the via forming hole is reduced, and as a result, the via forming hole is easily filled by the deposition from the bottom surface or the side surface. It is guessed.
  • the additive having a leveling action added to the electrolytic plating bath is also used. It is presumed that it works favorably in achieving complete filling. That is, it is considered that the additive is easily adsorbed around the opening of the via forming hole. For this reason, the deposition of plating on the portion concerned is considerably inhibited, and the deposition rate of plating becomes relatively slow. On the other hand, it is considered that the additive is unlikely to be adsorbed at the bottom of the small-diameter via forming hole, which is a recessed portion. For this reason, plating deposition on the portion concerned is not so hindered, and the plating deposition rate becomes relatively high.
  • the invention described in claim 2 explicitly specifies the relationship between the thickness of the insulating layer and the opening diameter of the via forming hole by specific numerical values.
  • the invention described in claim 3 has not only a structure suitable for multilayering and high-density mounting of a printed wiring board as described above, but also an excellent thinning of a conductor pattern. That is, it clearly indicates that the structure allows high-density wiring.
  • both the base plating layer and the plating layer deposited thereon are made of copper. Since it is composed of, higher cost is prevented.
  • the metals are of the same kind, they are easily compatible with each other, and a high adhesiveness is given to the interface between them, so that a highly reliable filled via can be obtained.
  • copper has excellent conductivity, so a low-resistance filled via can be obtained.
  • FIG. 1 is a partial schematic cross-sectional view showing a build-up multilayer printed wiring board according to an embodiment of the present invention
  • FIG. 2 is a partial schematic cross-sectional view for explaining a method of manufacturing the same wiring board
  • FIG. FIG. 4 is a partial schematic cross-sectional view for explaining the method for manufacturing the same wiring board
  • FIG. 4 is a partial schematic cross-sectional view for explaining the method for manufacturing the same wiring board
  • FIG. Sectional view, Figure 6 shows the same wiring board
  • FIG. 7A is a graph showing the degree of filling of the via-forming hole when the insulating layer is set to 4
  • FIG. 7B is a schematic diagram of the via
  • FIG. 7A is a graph showing the degree of filling of the via-forming hole when the insulating layer is set to 4
  • FIG. 7B is a schematic diagram of the via
  • FIG. 7A is a graph showing the degree of filling of the via-forming hole when the insulating layer is set to 4
  • FIG. 2 is a schematic diagram showing a graph and a via showing a graph.
  • a base substrate 3 that constitutes the build-up multilayer printed wiring board 1 is a so-called top surface plate having an inner layer conductor pattern 2 on both surfaces of a rigid insulating base material.
  • the inner conductor pattern 2 is formed by etching a copper foil.
  • a build-up layer 4 formed by alternately laminating insulating layers 5, 6 and conductor layers 7, 8 is formed on both sides of the base R3.
  • both buildup layers 4 have a two-layer structure.
  • the first insulating layer 5 is formed on the base substrate 3, and a first conductor layer (conductor pattern) 7 is formed on the upper surface thereof.
  • the second insulating layer 6 is formed on the first insulating layer 5, and a second conductor layer (component connection pad) 8 is formed on the upper surface thereof.
  • the insulating layers 5 and 6 are made of epoxy resin or the like.
  • the conductor layers 7 and 8 are made of copper, which is a metal having suitable conductivity.
  • the thickness of the conductor patterns 7 and 8 is 1 / ⁇ ! ⁇ 20, preferably 5 ⁇ ! ⁇ 1 ⁇ .
  • the thickness of the insulating layers 5 and 6 is 20 / ⁇ ! About 100 ⁇ , preferably 30 ⁇ ! It is set to about 60 ⁇ m.
  • the multilayer printed wiring board 1 has a small diameter filled via 9.
  • the small-diameter filled via 9 is formed in the build-up layer 4, more specifically, in the insulating layers 5 and 6 constituting the build-up layer 4.
  • These finoledo vias 9 are formed by filling the via forming holes 10 formed in the layers 5 and 6 mainly with the electrolytic plating layer 11. It is a thing.
  • a base plating layer (not shown) is interposed. Since the undercoating layer is extremely thin compared to the electrolytic plating layer 11, it is omitted in FIG. 1 for convenience.
  • the via-forming hole 10 provided in the first insulating layer 5 is located at a position corresponding to the interlayer connection portion 2 a in the inner-layer conductor pattern 2.
  • the via forming hole 10 provided in the second insulating layer 6 is located at a position corresponding to the interlayer connection portion 7 a in the conductor pattern 7.
  • the opening diameter D 1 of such a via-forming hole 10 is less than 10, preferably less than 75 / im, more preferably 25 ⁇ ! It is set to about 50 m.
  • the filled via 9 of the first insulating layer 5 connects the inner conductor pattern 2 and the conductor pattern 7 between layers.
  • the filled via 9 of the second insulating layer 6 connects the conductor pattern 7 and the component connection pad 8 between layers.
  • An electronic component (not shown) is surface-mounted on the component connection pad 8 by soldering.
  • the base substrate 3 is manufactured by a conventional method.
  • a copper-clad laminate is used as a starting material, and a conductive pattern 2 is formed on both sides of a glass epoxy insulating base material by etching according to a subtractive process (see FIG. 2).
  • an adhesive for forming an insulating layer is uniformly applied to both surfaces of the base substrate 3, and the cap is dried.
  • This adhesive is a so-called additive adhesive in which a readily soluble resin filler is dispersed in an epoxy resin matrix. As a result, the first insulating layer 5 having a predetermined thickness is formed.
  • the base substrate 3 After exposing a portion of the first insulating layer 5 corresponding to the interlayer connection portion 2a of the conductor pattern 2 using an unillustrated exposing machine, the base substrate 3 is then put into a developing machine for development. I do. As a result, a small-diameter via-forming hole 10 is formed at a predetermined location, and the interlayer connection portion 2a is exposed from that portion (see FIG. 3).
  • a laser method may be used. When the photo method is used as described above, it is necessary to impart photosensitivity to the additive adhesive. There is no particular need when using the laser method.
  • the entire surface of the first and fifth layers 5 and the entire inner wall surface of the via hole 10 are roughened by treating the base substrate 3 having undergone the drilling step with a roughening agent.
  • the fine anchor A suitable roughened surface having a concave portion is obtained.
  • the roughening agent is
  • An agent that dissolves easily soluble components in a dressing refers to a solution of, for example, chromic acid, chromate, sulfuric acid, hydrochloric acid, permanganic acid, and the like.
  • a defoaming treatment may be performed after the roughening treatment.
  • a catalyst nucleus 12 such as Pd serving as a core at the time of electroless plating deposition is applied to the entire surface of the first insulating layer 5, and a process of activating it is performed.
  • the catalyst nucleus 12 is also provided on the side surface of the via-forming hole 10 and on the surface of the interlayer connecting portion 2a exposed at the bottom surface of the via-forming hole 10 (see FIG. 4).
  • an undercoating layer (underlying copper plating layer) is formed on the entire surface of the first insulating layer 5 by performing electroless plating.
  • the plating at this time is so-called thin plating, and its thickness is 0. ⁇ ⁇ ! It is extremely thin, up to 3.0 / xm.
  • an electroless copper plating bath is preferably selected.
  • Electroless copper plating bath Product name (K C-500, manufactured by Japan Energy Co., Ltd.) Processing temperature: 68 ° C to 70 ° C
  • electrolytic panel plating is performed using an electrolytic plating bath to which an additive having a repelling effect is added.
  • an electrolytic plating layer 11 is deposited on the base plating layer.
  • thick plating is performed by using an electroplating bath as the electrolytic plating bath, and the electrolytic plating process is performed to form the surface of the first insulating layer 5.
  • An electrolytic plating layer 11 having a predetermined thickness is formed on the entire surface, and at the same time, a field via 9 is formed as a result of the electrolytic plating layer 11 being formed in the via forming hole 10 (see FIG. 5). ).
  • the bath may be agitated as needed.
  • Electrolytic copper plating bath Cu S04 60 ⁇ : I 00 g / l,
  • N a C 1 40-8 Omg / liter.
  • Processing time 60 minutes to 120 minutes
  • an etching resist (not shown) is formed on the surface of the electrolytic plating layer 11 on the first insulating layer 5, and in this state, etching is performed using an etchant capable of dissolving copper. As a result, the electrolytic plating layer 11 is partially dissolved and removed, and the conductor pattern 7 having a predetermined shape is formed on the first insulating layer 5 (see FIG. 6).
  • the graph in FIG. 7A shows the degree of filling of the via hole 10 when the insulating layers 5 and 6 are set to 40 in.
  • the graph in Fig. 7 (b) shows the via shape when the insulating layers 5 and 6 are set to 30 ⁇
  • the graph in Fig. 7 (c) shows the via shape when the insulating layers 5 and 6 are set to 60 / zm.
  • the degree of filling of the forming hole 10 is shown.
  • the horizontal axis indicates the via diameter D1 (specifically, the opening diameter D1 ( ⁇ ) of the via forming hole 10)
  • the vertical axis indicates the via plating height ⁇ m.
  • the thickness of the insulating layers 5 and 6 is indicated by T1 ( ⁇ ), and the thickness of the plating layer 11 deposited on the insulating layers 5 and 6 is ⁇ 2 ( ⁇ m). It is shown.
  • the via diameter D1 was set in six steps (six, 25 ⁇ , 50 ⁇ , 75 ⁇ , 100 ⁇ m, 125 ⁇ m, and 150 ⁇ m).
  • the via-forming hole 10 was easily filled with the electrolytic plating layer 11.
  • the diameter of the via-forming hole 10 is reduced, and an electrolytic panel is attached thereto using a plating bath in which an additive having a repelling action is added. Is in use. Therefore, a thicker electrolytic plating layer 11 is formed at the center of the via-forming hole 10 due to the leveling action provided by the additive. Therefore, a depression is less likely to occur in the center of the electrolytic plating layer 11, and a filled via 9 as shown in FIG. 1 can be obtained.
  • both the base plating layer and the electrolytic plating layer 11 deposited on the base plating layer are both made of copper, the cost is further increased. Can be prevented. Further, since the metals are of the same kind, they are easily compatible with each other, and a high adhesion is provided to the interface between them, so that a highly reliable filled via 9 can be obtained. Further, copper is excellent in conductivity, so that a low-resistance finoledo via 9 can be obtained.
  • the build-up layer 4 may not be formed on both sides of the base substrate 3, and may be formed on only one side. In addition, it is of course possible to adopt a configuration in which the number of build-up layers 4 is one or three or more.
  • the base substrate 3 is not limited to one having the conductor pattern 2 on both sides, but may be one having only one side (single-sided plate). Of course, the base substrate 3 may be a multilayer board. Furthermore, it is permissible to use a mere Si without a conductor pattern 2 as the base S3 ⁇ 43. That is, the printed wiring board embodying the present invention is not necessarily a multilayer printed wiring board.
  • the plating bath used for forming the electrolytic plating layer 11 is not limited to the electrolytic plating bath containing copper as metal ions as described in the embodiment. Instead, it is possible to use, for example, an electrolytic plating bath containing a metal ion such as nickel, chromium, palladium, aluminum or gold. Similarly, for the electroless plating bath used for forming the base plating layer, metal ions other than copper (nickel, chromium, palladium, aluminum Or gold etc.) can be selected.
  • the present invention is a method for manufacturing a high-density wiring and a printed wiring board capable of high-density mounting in which a filled via can be formed in a build-up layer relatively easily without increasing cost.

Abstract

L'invention concerne un procédé de production de cartes à circuit imprimé permettant de former de façon relativement simple une traversée pleine sur une couche d'empilement sans induire de frais élevés. Le procédé de production de cartes à circuit imprimé consiste à pratiquer une traversée (9) pleine sur une couche isolante (5) constituant une couche d'empilement par galvanoplastie, puis, après formation de la couche isolante (5) d'une épaisseur prédéterminée comportant un trou (10) de traversée à diamètre réduit, on forme la couche isolante en entier avec une couche primaire de galvanoplastie grâce à un bain autocatalytique, puis on applique un placage électrolytique sur la couche primaire de galvanoplastie grâce à un bain galvanoplastique auquel est ajouté un additif à pouvoir nivelant qui remplit le trou de traversée et forme sur la couche isolante (5) un film de placage électrolytique à surface sensiblement plate.
PCT/JP2000/001799 1999-03-25 2000-03-23 Procede de production de cartes a circuit imprime WO2000059277A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11/81180 1999-03-25
JP8118099A JP2000277918A (ja) 1999-03-25 1999-03-25 プリント配線板の製造方法

Publications (1)

Publication Number Publication Date
WO2000059277A1 true WO2000059277A1 (fr) 2000-10-05

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PCT/JP2000/001799 WO2000059277A1 (fr) 1999-03-25 2000-03-23 Procede de production de cartes a circuit imprime

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WO (1) WO2000059277A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180324A (ja) * 2005-12-28 2007-07-12 Victor Co Of Japan Ltd プリント基板及びその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04143289A (ja) * 1990-10-03 1992-05-18 Asahi Chem Ind Co Ltd 厚膜メッキ導体の形成方法
JPH06318783A (ja) * 1993-05-10 1994-11-15 Meikoo:Kk 多層回路基板の製造方法
JPH0779078A (ja) * 1993-09-08 1995-03-20 Shinko Electric Ind Co Ltd 多層配線基板及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04143289A (ja) * 1990-10-03 1992-05-18 Asahi Chem Ind Co Ltd 厚膜メッキ導体の形成方法
JPH06318783A (ja) * 1993-05-10 1994-11-15 Meikoo:Kk 多層回路基板の製造方法
JPH0779078A (ja) * 1993-09-08 1995-03-20 Shinko Electric Ind Co Ltd 多層配線基板及びその製造方法

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